CN106057682B - A kind of integrated approach of the vertical nano-wire device of air sidewall structure - Google Patents

A kind of integrated approach of the vertical nano-wire device of air sidewall structure Download PDF

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CN106057682B
CN106057682B CN201610648293.3A CN201610648293A CN106057682B CN 106057682 B CN106057682 B CN 106057682B CN 201610648293 A CN201610648293 A CN 201610648293A CN 106057682 B CN106057682 B CN 106057682B
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mask layer
active area
layer
sde
channel
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CN106057682A (en
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黎明
陈珙
杨远程
黄如
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Peking University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors

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Abstract

The present invention provides a kind of integrated approach of the vertical nano-wire device of air sidewall structure, this method combination etching through hole, epi channels material it is integrated, be prepared for active area air sidewall structure.Compared with traditional silica or silicon nitride spacer structure, since the relative dielectric constant of air is 1, it can greatly reduce the parasitic capacitance between grid and upper active area, and using upper active area as the drain terminal of device, the parasitic capacitance for optimizing drain terminal, can significantly improve the frequency characteristic of device；The present invention active extension area heavy doping by under simultaneously, source as device, source side resistance can be reduced, reduce the degeneration of device on-state current, and upper active extension area is that the heavy doping for being transitioned into upper active area side is lightly doped by channel side, it can reduce drain terminal electric field to penetrate channel region, while maintaining lower drain terminal resistance again.The present invention is mutually compatible with traditional integrated circuit manufacturing technology, and simple process, cost price are small.

Description

A kind of integrated approach of the vertical nano-wire device of air sidewall structure
Technical field
The invention belongs to super large-scale integration manufacturing technology fields, are related to a kind of vertical nanowires of air sidewall structure The integrated approach of line device part.
Background technique
It take fin formula field effect transistor (FinFET) as the horizontal ditch of representative after semiconductor devices enters 22nm technology generation Road three-dimensional multi-gate device (Multi-gate MOSFET, MuGFET), with outstanding inhibition short channel effect ability, high density of integration, The advantages that compatible with traditional cmos process, becomes the mainstream of semiconductor devices.But it is strided forward to smaller szie technology node When, and the challenge such as the spacing for facing contact hole is difficult to reduce and (limit the raising of integration density), grid etching in complex topography.
Vertical-channel enclose gate device because its with higher integration density, asymmetric source-drain structure, same technique generation under more The advantages such as loose side wall length of interval, and be concerned.Currently, the Integrated Solution master of the vertical nano-wire device of industry report If the propositions such as B.Yang based on etching formed channel method [B.Yang et al., EDL, 2008,29 (7): 791~ 794]: diameter 20nm being formd by etching on body silicon substrate, depth-width ratio is greater than the vertical-channel of 50:1, and passes through injection shape At the source and drain of device, conventional oxidation silicon medium and polygate electrodes are used.
But the performance and preparation method of vertical-channel nano-wire devices there is a problem in that:
With the size reduction of vertical nano-wire device, the ratio of source and drain dead resistance, parasitic capacitance in all-in resistance is anxious Increase severely and add, the influence in dead resistance especially with source side resistance to on-state current is big, and the parasitic capacitance of drain terminal is imitated due to Miller Several times should can be amplified, the high frequency characteristics of device is greatly influenced；
The vertical-channel of smaller diameter and large ratio of height to width is formed by the method for etching, itself proposes very etching technics Big challenge, and etch the channels cross-section pattern formed and be difficult to control, cause the degeneration of device property consistency, ditch caused by etching Road damage, causes further degenerating for device performance；
Active area is a part for the vertical nano-wire that etching is formed on the device that this method is formed, and sectional area is with device Size reduction and reduce, therefore by inject method be difficult to carry out heavy doping in the region, and between device the region impurity Concentration fluctuation increases with device dimensions shrink；
Therefore, industry is badly in need of a kind of vertical-channel nano-wire transistor for realizing that small size, high-performance, frequency characteristic are excellent Integrated approach.
Summary of the invention
In view of the above problems, the present invention provides a kind of air sidewall structure vertical nano-wire device integrating method, to improve Existing well-known technique.Include the following steps:
A., semi-conductive substrate is provided, realizes device isolation；
B. " the lower active area " of heavy doping is formed；
C. false gate stack is deposited；
The specific implementation steps are as follows:
C1. it deposits one layer of medium and makees " SDE mask layer 1 ", thickness defines the width of the lower active area side wall of device；
C2. it deposits one layer of medium and makees " false grid layer ", thickness defines the channel length Lg of device；
C3. it deposits one layer of medium and makees " SDE mask layer 2 ", thickness defines the width of the upper active area side wall of device；
Wherein, SDE mask layer 1, SDE mask layer 2, false grid layer three's material are different.And it is required that false grid layer material is to SDE The isotropic etching of mask layer 1 and SDE mask layer 2 selection ratio is all larger than 5:1, to guarantee to pass through isotropic etching in F4 SDE mask layer 1 and SDE mask layer 2 are not damaged when removing false grid layer；
D. vertical channel structure is formed by etching through hole, epi channels；
The specific implementation steps are as follows:
D1. pass through the shape of lithographic definition channels cross-section, size；
D2. channel window is formed by anisotropic etching, active area under the heavy doping of bottom of window exposing device is gone Glue；
D3. active extension area under device is formed in window by the graphical epitaxy technology of heavy doping in situ, under have The thickness of source extension area is no more than the thickness of SDE mask layer 1；
D4. the channel of device is formed by graphical epitaxy technology, is filled up in channel window by channel material；
D5. the channel material for exceeding 2 upper surface of SDE mask layer by chemically mechanical polishing removal deposit, realizes planarization；
D6. by carrying out ion implanting to channel upper end, the dopant profiles that concentration is lower by height from top to bottom, ion are formed The junction depth of injection is no more than the thickness of SDE mask layer 2, so far forms the upper active extension area of device；
Wherein, active extension area and channel under the device being graphically epitaxially formed, material can be with lower active area materials Identical (being epitaxially formed active extension area and Si channel under Si on active area such as at the Si of heavy doping), can also be with lower active area material Material difference (is epitaxially formed active extension area and Si channel under Si, in P+ heavy doping such as at the GeSi of N+ heavy doping on active area GeSi under be epitaxially formed active extension area and Ge channel under Ge on active area)；Under active extension area must heavy doping in situ into Row epitaxial growth, and channel can undope when epitaxial growth, can also adulterate；
E. the heavy doping " upper active area " of device is formed by deposit, etching；
The specific implementation steps are as follows:
E1. one layer of active material is deposited；
E2. heavy doping is carried out to active material by ion implantation technique；
E3. upper active area window is defined by photoetching technique；
E4. by anisotropic etching to the upper surface of SDE mask layer 2, active area in formation removes photoresist；
E5. source and drain impurity is activated by annealing process；
F. false grid are removed, HK, MG are deposited and form gate electrode；
The specific implementation steps are as follows:
F1. it deposits one layer of medium and makees top mask layer；
F2. pass through lithographic definition gate electrode；
F3. by anisotropic etching, expose the upper surface of SDE mask layer 1, remove photoresist；
F4. by isotropic etching, entire false grid layer is removed；
F5. high K dielectric (High-K, HK) and metal gate (Metal-Gate, MG) material is successively deposited；
F6. by anisotropic etching, HK, MG material not covered by top mask layer are removed, exposes SDE mask layer 1 Upper surface；
Wherein, top mask material described in F1 is identical as SDE mask layer 2, it is desirable that top mask layer and SDE mask layer The selection of the isotropic etching of 2 pairs of SDE mask layers 1 and HK, MG lamination is than being greater than 5:1, to guarantee to pass through isotropism in G1 SDE mask layer 1 and HK, MG lamination are not damaged when etching removal top mask layer and SDE mask layer 2；Top exposure mask described in F1 Thickness degree answer it is sufficiently thick, to guarantee in F6 to remove HK, MG material not covered by top mask layer by anisotropic etching, Behind the upper surface for exposing SDE mask layer 1, mask layer still has residue at the top of this on the upper active area of device；
G. SDE mask layer 2 and top mask layer, active area air side wall in formation are removed；
The specific implementation steps are as follows:
G1. by isotropic etching, entire SDE mask layer 2 and top mask layer are removed；
G2. it is formed by medium, upper active area air side wall between anisotropy deposit from level to level；
G3. chemical-mechanical planarization is carried out to inter-level dielectric；
H. the metal contact that device is respectively held is formed；
The specific implementation steps are as follows:
H1. the contact hole that device is respectively held is formed by photoetching, anisotropic etching, removed photoresist；
H2. metal Metal 0 is filled in each contact hole；
H3. it by carrying out chemical-mechanical planarization to metal Metal 0, realizes the conductive layers apart between device, reaches Device every
From effect；
I. subsequent integrated by published backend process completion device.
Further, heretofore described structural parameters (as " upper active area ", " upper active expansion area " and " under it is active Area ", the thickness of " under active expansion area " and doping concentration, the thickness of " SDE mask layer 1 ", " SDE mask layer 2 ", " false grid layer ", Material and thickness of HK, MG etc.) all set according to specific device performance requirements；
Further, semiconductor substrate described in A, including body silicon substrate, SOI substrate, body germanium substrate, GOI substrate, chemical combination Object semiconductor substrate etc.；
Further, it is isolated described in A, for body substrate (body silicon, body germanium etc.), trap isolation plus shallow-trench isolation can be used (ShallowTrench Isolation, STI)；For substrates such as SOI, GOI, shallow-trench isolation can be used only；
Further, lower active area described in B can be formed by injection, can also pass through patterned doped epitaxial shape in situ At；
Further, " upper active area " described in B, E should be used as the drain terminal of device, and " lower active area " should be used as the source of device End, the reason is as follows that: first, drain terminal is output end, and drain terminal, which is located at upside, when constructing circuit can reduce the complexity that interconnection is routed； Second, under active extension area be heavy doping, can reduce source side resistance as source, reduce the degeneration of on-state current, and on have Source extension area is transitioned into the heavy doping of upper active area side by the lighter doping in channel side, can reduce leakage as drain terminal Influence of the electric field to channel region is held, while in turn ensuring that drain terminal resistance is smaller；Third, the parasitic capacitance of drain terminal is due to Miller effect It can be amplified, grid can be greatly lowered with greater need for optimization, therefore using air sidewall structure in the parasitic capacitance compared to source Parasitic capacitance between drain electrode improves the frequency characteristic of device；
Further, the isotropism deposition process of nonmetallic materials described in C, E, F, G and H uses low pressure chemical phase Deposit (Low Pressure Chemical Vapor Deposition, LPCVD), atomic layer deposition (Atomic Layer One of Deposition, ALD), anisotropy deposition process using plasma enhances chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), inductively coupled plasma body enhance chemical vapor deposition One in (Inductively Coupled Plasma Enhance Chemical Vapor Deposition, ICPECVD) Kind, do not indicate with deposit be isotropism or anisotropy when, choose any one kind of them；
Further, annealing way uses rapid thermal annealing (Rapid Thermal Annealing), spike annealing in E One in (Spike Annealing), glittering annealing (Flash Annealing) and laser annealing (Laser Annealing) Kind；
Further, HK, GM material described in F, it is desirable that between HK medium and channel, there is good boundary between MG and HK Face characteristic, good thermal stability and chemical stability, the good atomic layer deposition (Atomic of the preferred conformality of deposition process Layer Deposition, ALD)；
Further, anisotropic etching uses such as reactive ion etching (Reactive Ion in D, E, F, G and H Etching, RIE) or inductively coupled plasma body (Inductively Coupled Plasma, ICP) etc.；
Further, as the filling metal Metal 0 of conductive layer described in H, it is desirable that have low resistivity and lead to W, Cu etc. may be selected in hole filling capacity；
Further, metal is filled in H using evaporation, sputtering, plating and chemical vapor deposition (Chemical Vapor One of Deposition, CVD).
The advantages and positive effects of the present invention are as follows:
1) upper active area air sidewall structure proposed by the present invention and traditional silica or silicon nitride spacer structure phase Than, since the relative dielectric constant of air is 1, it can greatly reduce the parasitic capacitance between grid and upper active area, due to The present invention is using upper active area as the drain terminal of device, and the frequency that the parasitic capacitance for optimizing drain terminal can significantly improve device is special Property；
2) present invention active extension area heavy doping by under can reduce source side resistance as the source of device, reduce device and open The degeneration of state electric current, and upper active extension area is that the heavy doping for being transitioned into upper active area side is lightly doped by channel side, by it It can reduce drain terminal electric field as drain terminal to penetrate channel region, while maintaining lower drain terminal resistance again；
3) with it is existing the method for vertical nanowires wire channel is formed by etching compared with, etching through hole proposed by the present invention, The integrated approach of epi channels material can accurately control the length, sectional area size and pattern of device channel, avoid existing Etching injury during channel is formed in method, improves the performance of device；
4) present invention can flexibly realize the hybrid integrated of multiple material channel or source and drain, this is existing by etching shape It is difficult at the method for vertical nanowires wire channel；
5) side wall alternative gate (rear grid technique) scheme proposed by the present invention, solve it is existing by etching form vertical nanowires The problem of being difficult to realize alternative gate in the method for wire channel, improves device property.
Detailed description of the invention
Fig. 1-14 is the signal that each joint technique of air sidewall structure vertical nano-wire NMOSFET is prepared in SOI substrate Figure.In each figure, (a) is top view, is (b) sectional view in (a) along A-A '.
Wherein:
Fig. 1 forms the isolation of device on soi substrates；
Fig. 2 carries out N-type heavy doping to the lower active area of device；
Fig. 3 successively deposits SDE mask layer 1, false grid material, SDE mask layer 2；
Fig. 4 photoetching, etching form the channel window of device；
Fig. 5 extension N-type heavy doping monocrystalline silicon, forms active extension area under device；
Fig. 6 epitaxial light doped p-type monocrystalline silicon, as the channel of device, planarization；
Fig. 7 carries out N-type ion injection to channel upper end, forms Gauss dopant profiles, the upper active extension area as device；
Fig. 8 forms the active area in N-type heavy doping；
Fig. 9 deposit top mask layer, lithographic definition area of grid are etched to 2 upper surface of SDE mask layer；
Figure 10 isotropic etching vacation grid layer；
Figure 11 deposit HK, MG lamination simultaneously forms gate electrode；
Figure 12 isotropic etching SDE mask layer 2 and top mask layer；
Figure 13 anisotropy deposits inter-level dielectric, realizes planarization；
Figure 14 etches contact hole, and fills metal, planarizes；
Figure 15 is the legend of Fig. 1~Figure 14.
Specific embodiment
The present invention is described in detail with specific example with reference to the accompanying drawing.
Air side wall construction vertical nano-wire NMOSFET in SOI substrate may be implemented according to the following steps:
1) 20nm will be thinned to for top silicon surface using HNA solution by being lightly doped in SOI substrate in (100) p-type, pass through light It carves, the lower active area of RIE etching definition device, removes photoresist, as shown in Figure 1；
2) As is carried out+Injection doping forms the lower active area (source for making device) of device, Implantation Energy 10KeV, injection Dosage 5E15cm-2；
3)LPCVD SiO240nm carries out surface planarisation by chemically mechanical polishing, exposes active area under heavy doping Upper surface forms STI, as shown in Figure 2；
4) 10nm SiO is successively deposited by ALD2(make SDE mask layer 1, thickness defines the lower active area side of device The width of wall is 10nm), 14nm Si3N4(grid layer of playing tricks, thickness define the channel length Lg=14nm of device), 10nm SiC (makees SDE mask layer 2, the width that thickness defines the upper active area side wall of device is 10nm), as shown in Figure 3；
5) it etches to form device channel window (cylindrical body of the window for diameter 15nm, bottom of window dew by photoetching, ICP Active area under the heavy doping of device out), it removes photoresist, as shown in Figure 4；
6) in channel window, pass through As in situ+Doped epitaxial 10nm monocrystalline silicon forms active under the device of heavy doping prolong Area is stretched, as shown in Figure 5；
7) in channel window, pass through B in situ+Doped epitaxial 30nm monocrystalline silicon, channel window is interior to be filled up by channel material, The p type single crystal silicon for exceeding 2 upper surface of SDE mask layer by chemically mechanical polishing removal deposit, realizes planarization, as shown in Figure 6；
8) by carrying out As to channel upper end+Ion implanting, Implantation Energy 5KeV, implantation dosage 5E14cm-2, form peak value Gauss dopant profiles positioned at channel upper end, the junction depth of ion implanting are 10nm, so far form the upper active extension area of device, such as Shown in Fig. 7；
9) LPCVD depositing polysilicon 30nm, and carry out As+Injection doping, Implantation Energy 15KeV, implantation dosage 5E15cm-2, by photoetching, RIE etches polycrystalline silicon 30nm, active area (drain terminal as device) on N+ heavily doped polysilicon is formed, is removed photoresist, As shown in Figure 8；
10) it is annealed 1000 DEG C, 10s by RTA, the source of activating appts, leakage；
11) LPCVD deposits 50nm SiC and is used as top mask layer, and by lithographic definition gate electrode, ICP etching is not photo-etched 50nm SiC (top mask layer), the 10nm SiC (SDE mask layer 2), 14nm Si of glue covering3N4(false grid layer) is exposed SDE and is covered The upper surface of film layer 1, removes photoresist, as shown in Figure 9；
12) by isotropic etching, entire Si is removed3N4False grid layer, as shown in Figure 10；
13) high K (HK) medium and metal gate (MG) material are successively deposited by ALD；
14) HK, MG laminated material that the removal of ICP etching is not covered by top mask layer, exposes the upper table of SDE mask layer 1 Face, as shown in figure 11；
15) by isotropic etching, 50nm SiC (top mask layer), 10nm SiC (SDE mask layer 2) are removed, such as Shown in Figure 12；
16) 200nm SiO is deposited by PECVD2As inter-level dielectric, upper active area forms air side wall, passes through chemistry Inter-level dielectric planarization is realized in mechanical polishing, as shown in figure 13；
17) contact hole to form device gate, source, each end of leakage is etched by photoetching, ICP, is removed photoresist；
18) sputter 500nm tungsten, device gate, source, each end of leakage contact hole filled by tungsten；
19) it by being chemically-mechanicapolish polished to tungsten, realizes the conductive layers apart between device, reaches device isolation Effect, as shown in figure 14；
20) subsequent integrated by published backend process completion device.
The embodiment of the present invention is not intended to limit the invention.Anyone skilled in the art is not departing from this hair In the case of bright technical proposal scope, many all is made to technical solution of the present invention using the methods and technical content of the disclosure above Possible changes and modifications or equivalent example modified to equivalent change.Therefore, all without departing from technical solution of the present invention Content, any simple modifications, equivalents, and modifications made to the above embodiment, still belong to according to the technical essence of the invention In the range of technical solution of the present invention protection.

Claims (9)

1. a kind of integrated approach of the vertical nano-wire device of air sidewall structure, includes the following steps:
A., semi-conductive substrate is provided, realizes device isolation；
B. the lower active area of heavy doping is formed；
C. false gate stack is deposited；
The specific implementation steps are as follows:
C1. it deposits one layer of medium and makees the first SDE mask layer, thickness defines the width of the lower active area side wall of device；
C2. it deposits one layer of medium to play tricks grid layer, thickness defines the channel length of device；
C3. it deposits one layer of medium and makees the 2nd SDE mask layer, thickness defines the width of the upper active area side wall of device；
D. vertical channel structure is formed by etching through hole, epi channels；
The specific implementation steps are as follows:
D1. pass through the shape of lithographic definition channels cross-section, size；
D2. channel window is formed by anisotropic etching, active area under the heavy doping of bottom of window exposing device removes photoresist；
D3. active extension area under device is formed in window by the graphical epitaxy technology of heavy doping in situ, under active prolong The thickness for stretching area is no more than the thickness of the first SDE mask layer；
D4. the channel of device is formed by graphical epitaxy technology, is filled up in channel window by channel material；
D5. the channel material for exceeding the 2nd SDE mask layer upper surface by chemically mechanical polishing removal deposit, realizes planarization；
D6. by carrying out ion implanting to channel upper end, the dopant profiles that concentration is lower by height from top to bottom, ion implanting are formed Junction depth be no more than the 2nd SDE mask layer thickness, so far formed device upper active extension area；
E. active area in the heavy doping of device is formed by deposit, etching；
The specific implementation steps are as follows:
E1. one layer of active material is deposited；
E2. heavy doping is carried out to active material by ion implantation technique；
E3. upper active area window is defined by photoetching technique；
E4. by anisotropic etching to the upper surface of the 2nd SDE mask layer, active area in formation removes photoresist；
E5. source and drain impurity is activated by annealing process；
F. false grid are removed, HK, MG are deposited and form gate electrode；
The specific implementation steps are as follows:
F1. it deposits one layer of medium and makees top mask layer；
F2. pass through lithographic definition gate electrode；
F3. by anisotropic etching, expose the upper surface of the first SDE mask layer, remove photoresist；
F4. by isotropic etching, entire false grid layer is removed；
F5. HK, MG material are successively deposited；
F6. by anisotropic etching, HK, MG material not covered by top mask layer are removed, exposes the first SDE mask layer Upper surface；
G. the 2nd SDE mask layer and top mask layer, active area air side wall in formation are removed；
The specific implementation steps are as follows:
G1. by isotropic etching, entire 2nd SDE mask layer and top mask layer are removed；
G2. it is formed by medium, upper active area air side wall between anisotropy deposit from level to level；
G3. chemical-mechanical planarization is carried out to inter-level dielectric；
H. the metal contact that device is respectively held is formed；
The specific implementation steps are as follows:
H1. the contact hole that device is respectively held is formed by photoetching, anisotropic etching, removed photoresist；
H2. metal Metal 0 is filled in each contact hole；
H3. it by carrying out chemical-mechanical planarization to metal Metal 0, realizes the conductive layers apart between device, reaches device The effect of isolation；
I. conventional backend technique is finally entered, it is integrated to complete device.
2. the method as described in claim 1, which is characterized in that the first SDE mask layer, the 2nd SDE mask layer and false grid layer three Person's material is different, and false grid layer material is equal to the isotropic etching selection ratio of the first SDE mask layer and the 2nd SDE mask layer Greater than 5:1.
3. the method as described in claim 1, which is characterized in that top mask material and second described in the step F1 SDE mask material is identical, and top mask layer and the 2nd SDE mask layer to the first SDE mask layer and HK, MG lamination it is each to Same sex etching selection ratio is greater than 5:1.
4. the method as described in claim 1, which is characterized in that semiconductor substrate described in the step A include body silicon substrate, SOI substrate, body germanium substrate, GOI substrate and compound semiconductor substrate use trap isolation plus shallow-trench isolation for body substrate；It is right Shallow-trench isolation is used in SOI, GOI substrate.
5. the method as described in claim 1, which is characterized in that lower active area described in the step B is formed by injection, or It is formed by patterned doped epitaxial in situ.
6. the method as described in claim 1, which is characterized in that nonmetallic materials is each to same in described step C, E, F, G and H Property deposition process use one of low-pressure chemical vapor phase deposition LPCVD, atomic layer deposition ALD, anisotropy deposition process adopts With plasma enhanced CVD PECVD.
7. the method as described in claim 1, which is characterized in that annealing way uses rapid thermal annealing in the step E, described Rapid thermal annealing is one of spike annealing, glittering annealing and laser annealing.
8. the method as described in claim 1, which is characterized in that as the filling metal of conductive layer described in the step H Metal 0 is W or Cu.
9. the method as described in claim 1, which is characterized in that fill metal in the step H using evaporation, sputtering, plating One of with chemical vapor deposition CVD.
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