CN106057236B - A kind of phase transition storage method for writing data - Google Patents
A kind of phase transition storage method for writing data Download PDFInfo
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Abstract
A kind of phase transition storage method for writing data, belongs to the date storage method of memory, solves not utilize energy consumption budget problem existing for existing phase transition storage method for writing data maximumlly, to promote write performance and the service life of phase transition storage (PCM).The present invention includes reading data step, analysis data step, write-in data step.The present invention writes the delay of " 0 " and one writing and the asymmetry of energy consumption for PCM, make full use of the energy consumption budget (power budget) of PCM, by the number for recording each data cell " 0 " and " 1 " to be modified respectively, each data cell write sequence is rescheduled, maximize the utilization to energy consumption budget, the write delay for further shortening PCM, to promote write performance and service life.
Description
Technical field
The invention belongs to the date storage methods of memory, and in particular to a kind of phase transition storage method for writing data is fitted
For building efficient phase transition storage storage system, the enterprise of the Nonvolatile memory system for requiring high-performance, low latency
Industry, individual or research institution have important use value.
Background technology
Phase transition storage (PCM, Phase Change Memory) be it is a kind of by chalcogenide material (GST,
Ge2Sb2Te5) constitute novel nonvolatile storage, the dielectric material for constituting phase transition storage under certain condition can be in amorphous
Changing between state and crystalline state, amorphous state and crystalline state in the process show different resistance characteristics and optical characteristics,
Therefore, " 0 " and " 1 " can be indicated respectively using amorphous state and crystalline state to store data.
Fig. 1 illustrates the storage architecture of PCM, and as an example, phase change memory system arranges (rank) group by 2 storages
At comprising N number of memory bank (bank) in each storage row (rank), each memory bank (bank) is by 4 chip (chips) groups
At each chip includes then multiple memory cell arrays (cell block), and each memory cell array includes that multiple storages are single
Member, each storage unit store a data；The width of data/address bus determines the number of chips of one bank of composition, due to electricity
It is that storage unit persistently provides big transient current, therefore a chip can be written in parallel to that the noise of source line, which can limit charge pump,
Digit be it is restricted, the digit that commonly referred to as a chip can be written in parallel to be chip r/w cell size, claim one deposit
The digit that all chips can be written in parallel in storage body (bank) is the size of a PCM r/w cell, and the size of PCM r/w cells is used
The byte number that a bank can be written indicates.
If PCM r/w cell sizes are N, chip r/w cell size is K, and cache lines (cache line) size is M,
Therefore complete this cache line size write-in need to the same PCM r/w cells write-in [M/N] it is secondary.In general, chip r/w cell is big
Small K is 16, and each chip package is at 16 BITBUS network interfaces, and data/address bus is 64, therefore needs 4 chips to carry out altogether
Data-bus width is aligned.One cache line size is 64 bytes, per byte 8；The data of cache lines once can be with concurrent write
The byte number for entering a memory bank (bank) is the byte of (K × (64/16))=64=8.
Cache lines can be respectively stored in the L (L=2 in memory bank (bank) included first1) chip chip in delay
In depositing, the complete cache lines that a size is M share L chip, data volume Q=M/ (8L) word of each chip
Section, this Q byte data are needed to chip r/w cell write-in Q × 8/K time, every time one data cell (Data unit) of write-in；It waits for
The initial address of write-in cache lines is stored in caching row address register.
For 4 chip r/w cells that PCM r/w cells include, a size is the complete cache lines point of 64 bytes
The data volume Q for carrying on a shoulder pole each chip is 16 bytes, this 16 byte data is needed to chip r/w cell write-in Q/K (16 × 8/16=
8) secondary, a data cell (Data unit) (2 byte) is written every time.
Phase transition storage has the advantage that：Non-volatile, position can change, read latency is short, read low energy consumption, is not necessarily to refreshing etc..
In addition, PCM energy consumptions are more for comparison dynamic random access memory (DRAM, Dynamic Random Access Memory)
It is low, while its non-volatile and relatively high storage density is but also it becomes ideal memory substitute.PCM is also defective,
Especially write performance, write power consumption and life problems, this promote researcher put forward various plans with approach with make up PCM itself
Defect.
The noise of power cord can limit charge pump and persistently provide big transient current for storage unit, therefore can be with concurrent write
The digit for entering chip is limited to PCM r/w cell sizes (constant N).And write a cache lines need it is multiple continuously perform write list
Member, this is greatly lowered whole write performance.In addition, there are one important features for phase transition storage：Write " 0 " and one writing
Asymmetry in terms of being delayed with energy consumption, as shown in Fig. 2, one writing pulse is about writing the clock cycle needed for " 0 " pulse
It is octuple；It writes twice that the current strength needed for " 0 " pulse is about one writing pulse, writes " 0 " pulse and compare one writing pulse delay
Shorter but required electric current bigger, this asymmetry significantly limit the performance of PCM write operations.Traditional PCM system is being write
The case where request scheduling aspect is very conservative, and what is considered is current needs maximum and time demand longest, that is, by write-in
Position be all " 0 " and write-in position be all " 1 " consider.When a data block for being mixed with " 0 " and " 1 " is written, due to writing
Difference of " 0 " one writing in terms of the response time makes unnecessary waiting and causes to write bandwidth and be not fully utilized, and due to right
The underutilization of energy consumption budget (power budget) and waste concurrency.
In the present invention, Data flipping refers to that each binary digit is converted to the binary system opposite with former binary value in former data
Value, i.e., " 1 " is converted to " 0 ", " 0 " is converted to " 1 ".
Invention content
The present invention provides a kind of phase transition storage method for writing data, solves existing phase transition storage method for writing data and deposits
Not maximumlly utilize energy consumption budget problem, to promote write performance and the service life of phase transition storage (PCM).
A kind of phase transition storage method for writing data provided by the present invention, including read data step, analysis data step
Suddenly data step, is written, it is characterised in that：
(1) data step is read, includes following sub-steps to each chip in memory bank to be written (bank)：
(1.1) value for caching row address register is set to the initial address of cache lines to be written；By read-out counter
Value RD be set as 0；
(1.2) legacy data section { F, D that the offset address cached in chip is (K+1) × RD are read0And put it into reading
In caching, legacy data section { F, D0Size be K+1, for the size of chip r/w cell after extension；Wherein flip bit F is 1,
Old data units D0It is K；
(1.3) the new data element D that offset address is K × RD is taken out in cache lines to be written1, by new data element
D1With old data units D0It is compared by turn, judges to have whether differentiated digit is more than K/2, be then rotor step (1.4)；
Otherwise rotor step (1.5)；
(1.4) by new data element D1Overturning is D2, " 1 " is assigned to flip bit F, by D2It is assigned to data sheet to be written
First D constitutes data segment to be written { F, D }, rotor step (1.6)；D1Overturning is D2When, D1In each binary zero position become " 1 "
Position, " 1 " position becomes " 0 " position；
(1.5) new data element D1It remains unchanged, " 0 " is assigned to flip bit F, by D1It is assigned to data cell to be written
D constitutes data segment to be written { F, D }, rotor step (1.6)；
(1.6) it is written into data segment { F, D }, in being saved in offset address to be cached in the corresponding chips of (K+1) × RD,
It is recorded relative to legacy data section { F, D0Modification " 1 " and " 0 " number, be stored in corresponding one writing array and write " 0 " respectively
In array；
The one writing array respectively includes M/ (L × K) item record with " 0 " array is write, every record in one writing array
It is made of serial number and data, serial number is corresponding with the offset address cached in chip, and data are that data segment to be written { F, D } is opposite
In legacy data section { F, D0Modification " 1 " number；It writes every in " 0 " array record to be made of serial number and data, serial number
Corresponding with the offset address cached in chip, data are data segment to be written { F, D } relative to legacy data section { F, D0Modification
The number of " 0 "；M is the digit of cache lines, and K is the size of chip r/w cell, and L is number of chips in a memory bank；The dimension of K
For position；
(1.7) it assigns the value of RD+1 to RD, judges whether RD=M/ (L × K), be to go to step (2), otherwise rotor step
(1.2)；
Before data are written to certain certain chip r/w cell, the legacy data in the chip r/w cell, and profit are first read out
Bit number to be written is minimized with the method for setting flip bit；
(2) data step, including following sub-steps are analyzed：
(2.1) one writing queue is established respectively and writes " 0 " queue, one writing queue and to write " 0 " queue be first in first out team
Row, one writing queue and write every of " 0 " queue and record and constituted by executing number, data cell serial number and data；Execute number
The serial number of corresponding write-in execution sequence, data cell serial number is corresponding with the offset address cached in chip, and data are number to be written
According to location contents, multiple data cells can have it is identical execute number, indicate that these data cells should be in the same execution
It is sequentially written in chip；
Each item record in global energy consumption budget array WU is initialized as 0, the overall situation energy consumption budget array WU includes M/
(L × K) item records, and every record is made of execution number and its corresponding write-in chip energy consumption, is gone to step (2.2)；
(2.2) it to one writing array, is solved by MaxPB algorithms, determines that the data cell to be written of parallel one writing executes
Sequentially, one writing queue, rotor step (2.3) are formed；
(2.3) it to writing " 0 " array, is solved by MaxPB algorithms, determines that the data cell to be written of concurrent write " 0 " executes
Sequentially, it is formed and writes " 0 " queue, gone to step (3)；
Analysis data step will write " 0 " and one writing and separate, and make full use of energy consumption budget to determine by MaxPB algorithms and adjust
Degree scheme；
(3) one writing step, including following sub-steps：
(3.1) the value start of setting write-in initial address register, size are the position (j+m+n), and value is for cache lines
The value q of write sequence counter is set as 1 by the position (j+m+n) after the register of location；J=0,1,2 or 3, m=9~16, n=1~
5；
(3.2) judge whether one writing queue is empty, is to go to step (4)；Otherwise sub-step (3.3) is carried out；
(3.3) each item record for executing that number is q is taken out from one writing queue, according to their corresponding data cell sequences
Number corresponding data cell to be written of selection, carries out sub-step (3.4)；
(3.4) it is written into data cell of the data cell with offset address in read buffer for corresponding data cell serial number
XOR logic operation is carried out, XOR logic operation result is obtained, carries out sub-step (3.5)；
(3.5) judge whether that the XOR logic operation result and the corresponding positions of data cell to be written are " 1 ", be then
It is in the storage unit of (start+ data cell serial numbers+p), otherwise without any behaviour by " 1 " write storage unit address
Make；Sub-step (3.6) is carried out, p is the corresponding positions of data cell to be written；
(3.6) value of q+1 is assigned to the value q of write sequence counter, rotor step (3.2)；
(4) " 0 " step, including following sub-steps are write：
(4.1) judge to write whether " 0 " queue is empty, be that then write operation is completed；Otherwise sub-step (4.2) is carried out；
(4.2) from each item record that taking-up execution number is q in " 0 " queue is write, according to their corresponding data cell sequences
Number corresponding data cell to be written of selection, carries out sub-step (4.3)；
(4.3) it is written into data cell of the data cell with offset address in read buffer for corresponding data cell serial number
XOR logic operation is carried out, XOR logic operation result is obtained, carries out sub-step (4.4)；
(4.4) judge whether that the XOR logic operation result corresponding positions are the corresponding positions of " 1 " and data cell to be written
For " 0 ", in the storage unit of (start+ data cell serial numbers+p), otherwise not it is then by " 0 " write storage unit address to be
Carry out any operation；Carry out sub-step (4.5)；
(4.5) value of q+1 is assigned to the value q of write sequence counter, rotor step (4.1).
In the sub-step (2.2) of the analysis data step, the MaxPB algorithms include following processes：
The maximum energy consumption budget PBmax that chip r/w cell allows is arranged in (2A), and PBmax is determined by Chip scale；It will execute
The value w of sequence counter is set to 1；
(2B) calculates the power consumption values of each data cell to be written, and is put into power consumption values array IN；By data cell
The value i of processing counter is set to 1, carries out process (2C)；
The power consumption values array IN includes M/ (L × K) item record, and every record is made of serial number and data, serial number and
The offset address cached in chip corresponds to, and data are the power consumption values of data cell to be written；
The power consumption values of the data cell to be written are that the data of respective record in one writing array in sub-step (1.6) (are repaiied
The number of " 1 " that changes) it is multiplied by energy consumption needed for one writing；Wherein, energy consumption needed for one writing is determined by Chip scale；
(2C) for the power consumption values array IN, the size of data recorded according to every carries out descending row to all records
Sequence, and each item is recorded according to pending queue is sequentially put into after sequence, turn over journey (2D)；
(2D) judges whether pending queue is empty, is to carry out process (2E)；Otherwise journey (2F) is turned over；
(2E) forms one writing queue, and analysis scheduling is completed；
(2F) takes out a record from pending queue head, carries out process (2G)；
(2G) traverses before WU arrays w, judges whether (IN [i]+WU [w]) ＜ PBmax, is to turn over journey (2H)；Otherwise
Turn over journey (2I)；In above-mentioned judgement formula, IN [i] indicates that the data of i-th record in power consumption values array IN, WU [w] indicate global
The write-in chip energy consumption that number is w is executed in energy consumption budget array WU；
Judge in IN that the serial number of i-th record corresponds to data cell to be written whether can be without prejudice to chip maximum energy
In the case of consumption budget chip is sequentially written in the execution for executing number w；
(2H) using w as execute number, using in IN i-th record serial number as data cell serial number, by i-th in IN
The serial number of record corresponds to data cell to be written as data, constitutes a record, is added to one writing queue tail of the queue；
Meanwhile assigning the value of WU [w]+IN [i] to WU [w], it assigns the value of i+1 to i, turns over journey (2D)；
(2I) assigns the value of w+1 to w, turns over journey (2H).
In the sub-step (2.3) of the analysis data step, the MaxPB algorithms include following processes：
The maximum energy consumption budget PBmax that chip r/w cell allows is arranged in (2A), and PBmax is determined by Chip scale；By w+1's
Value is assigned to the value w for executing sequence counter；
(2B) calculates the power consumption values of each data cell to be written, and is put into power consumption values array IN；By data cell
The value i of processing counter is set to 1, carries out process (2C)；
The power consumption values array IN includes M/ (L × K) item record, and every record is made of serial number and data, serial number and
The offset address cached in chip corresponds to, and data are the power consumption values of data cell to be written；
The power consumption values of the data cell to be written (are repaiied to write the data of respective record in " 0 " array in sub-step (1.6)
The number of " 0 " that changes) it is multiplied by and writes energy consumption needed for " 0 "；Wherein, energy consumption needed for " 0 " is write to be determined by Chip scale；
(2C) for the power consumption values array IN, the size of data recorded according to every carries out descending row to all records
Sequence, and each item is recorded according to pending queue is sequentially put into after sequence, turn over journey (2D)；
(2D) judges whether pending queue is empty, is to carry out process (2E)；Otherwise journey (2F) is turned over；
" 0 " queue is write in (2E) formation, and analysis scheduling is completed；
(2F) takes out a record from pending queue head, carries out process (2G)；
(2G) traverses before WU arrays w, judges whether (IN [i]+WU [w]) ＜ PBmax, is to turn over journey (2H)；Otherwise
Turn over journey (2I)；In above-mentioned judgement formula, IN [i] indicates that the data of i-th record in power consumption values array IN, WU [w] indicate global
The write-in chip energy consumption that number is w is executed in energy consumption budget array WU；
(2H) using w as execute number, using in IN i-th record serial number as data cell serial number, by i-th in IN
The serial number of record corresponds to data cell to be written as data, constitutes a record, is added to and writes " 0 " queue tail of the queue；
Meanwhile assigning the value of WU [w]+IN [i] to WU [w], it assigns the value of i+1 to i, turns over journey (2D)；
(2I) assigns the value of w+1 to w, turns over journey (2H).
On the basis of existing chip data access, the present invention uses a kind of phase change memory chip comprising J storage
It is cell array (Cell Block), J ranks decoder, J write driver, caching in chip, caching row address register, more
Road selector (DMUX) and data output caching (DOUT), J memory cell array are separately connected J ranks decoder, J row
Column decoder is separately connected J write driver, and caching is sequentially connected in series with multiple selector and data output caching in chip, J=
2j, j=0,1,2 or 3；The memory cell matrix that each memory cell array is 2m rows, 2n is arranged, including 2m×2nA storage is single
Member；M=9~16, n=1~5, a PCM chip size are 2j×2m×2nPosition, memory unit address length are the position (j+m+n)；
J ranks decoder is used for the row and column of select storage unit array；
The access of storage unit is carried out according to given memory unit address, gives j+m+n memory unit addresses, root
The memory cell array judged where storage unit according to first j, row number where judging storage unit according to intermediate m, according to
The last positions n judge that column number where storage unit, row number and column number determine a storage unit in storage unit jointly
Position in array；
Caching is M/L in existing chip, and multiple selector and data the output caching of existing chip are respectively K, are read slow
Save as K；In order to support Data flipping to operate, data path is extended：Data output caching and multiple selector expand from K
It opens up K+1 (adding one " flip bit ")；In original chip caching increase (1/K) × M/L, expand to (1+1/K) ×
M/L, the multiple selector, data output caching are expanded into the position (K+1), and increase the read buffer of the position (K+1)；
The present invention is realized according to said chip reads data, analysis data and write-in data,
It reads data and passes through memory cell array, ranks decoder, write driver, caching in chip, more successively from top to bottom
Road selector, read through model are exported up to data in caching；Data are write then to cache by data output successively from the bottom up, is more
Caching, parallel writing module, write driver and ranks decoder in road selector, chip are until memory cell array.It needs to note
Meaning, the level of addition can't influence the path of read operation.
Wherein, read through model executes all operations that the present invention reads data step；Parallel writing module executes present invention analysis
Data step, all operations that data step is written.
It is write compared with scheme with existing PCM, the invention has the advantages that：
(1) present invention can reduce total bit to be written." reading data, analysis data and write-in data " operation is utilized to replace
Original write operation is changed to avoid the write operation (being write on " 0 " " 0 ") of some extra repetitions, and by the way that one " flip bit " is arranged
The maximum number of digits changed will be needed to be reduced in a data cell and be not more than (K-1)/2, and then phase transition storage can be promoted
Service life.
(2) present invention can reduce write delay.The corresponding of " 0 " and one writing is write using a storage unit in phase transition storage
Time and energy consumption asymmetry separately handle write " 0 " and the one writing of write operation, have been carried out to conservative conventional write scheme excellent
Change, writes bandwidth to be promoted, reduce write delay.
(3) present invention can make full use of concurrency, by being carried out to data cell to be written in analysis data step
To writing the sequence of " 0 " and one writing, in the dispatching r/w cell of energy consumption budget limit, the concurrency of write operation is taken full advantage of；And
Energy consumption budget is maximally utilized, write delay is significantly reduced, promotes PCM write performances and service life.
The present invention writes the delay of " 0 " and one writing and the asymmetry of energy consumption for PCM, makes full use of the energy consumption budget of PCM
(power budget), by recording the number of each data cell " 0 " and " 1 " to be modified respectively, to each data
Unit write sequence reschedules, and maximizes the utilization to energy consumption budget, further shortens the write delay of PCM, is write to be promoted
Performance and service life.
Description of the drawings
Fig. 1 is the storage architecture schematic diagram of PCM；
Fig. 2 is asymmetry schematic diagram of the PCM write operations in terms of being delayed with energy consumption；
Fig. 3 is chip schematic diagram of the present invention；
Fig. 4 is flow diagram of the present invention；
Fig. 5 is to read data step flow diagram；
Fig. 6 analyzes data step flow diagram；
Fig. 7 is write-in data step flow diagram；
Fig. 8 is the MaxPB algorithm flow block diagrams to form one writing queue.
Specific implementation mode
Below in conjunction with drawings and examples, the present invention is further described.
As shown in figure 3, chip embodiment of the present invention comprising memory cell array #0~storage unit battle array
Arrange #4,4 ranks decoders, 4 write drivers, caching in chip, caching row address register, multiple selector (DMUX) and
Data output caching (DOUT), 4 memory cell arrays are separately connected 4 ranks decoders, and 4 ranks decoders are separately connected
4 write drivers, the interior caching of chip are sequentially connected in series with multiple selector and data output caching, each memory cell array is
29Row, 24The memory cell matrix of row, including 29×24A storage unit；One PCM chip size is 22×29×24Position, storage
Element address length is the position (2+9+4)；4 ranks decoders are used for the row and column of select storage unit array；
The access of storage unit is carried out according to given memory unit address, gives 2+9+4 memory unit addresses, root
The memory cell array judged where storage unit according to first 2 judges storage unit place row number according to intermediate 9, according to
Last 4 judge that column number where storage unit, row number and column number determine a storage unit in storage unit jointly
Position in array；
Caching is 128 in existing chip, and multiple selector and data the output caching of existing chip are respectively 16, are read slow
Save as 16；In order to support Data flipping to operate, data path is extended：Data output caching and multiple selector are from 16
It expands to 17 (adding one " flip bit ")；Caching increases by 8, expands to 136 in original chip, the multi-path choice
Device, data output caching are expanded into 17, increase by one 17 read buffers.
Fig. 4 is flow diagram of the present invention；
Fig. 5 is to read data step flow diagram；
Fig. 6 analyzes data step flow diagram；
Fig. 7 is write-in data step flow diagram；
Fig. 8 is the MaxPB algorithm flow block diagrams to form one writing queue；The MaxPB algorithm flow frames of " 0 " queue are write in formation
Figure is similar therewith, repeats no more.
Claims (3)
1. a kind of phase transition storage method for writing data, including data step, analysis data step, write-in data step are read,
It is characterized in that：
(1) data step is read, includes following sub-steps to each chip in memory bank to be written：
(1.1) value for caching row address register is set to the initial address of cache lines to be written；By the value of read-out counter
RD is set as 0；
(1.2) legacy data section { F, D that the offset address cached in chip is (K+1) × RD are read0And put it into read buffer
In, legacy data section { F, D0Size be K+1, for the size of chip r/w cell after extension；Wherein flip bit F is 1, old number
According to cells D0It is K；
(1.3) the new data element D that offset address is K × RD is taken out in cache lines to be written1, by new data element D1With
Old data units D0It is compared by turn, judges to have whether differentiated digit is more than K/2, be then rotor step (1.4)；Otherwise
Rotor step (1.5)；
(1.4) by new data element D1Overturning is D2, " 1 " is assigned to flip bit F, by D2It is assigned to data cell D to be written,
Constitute data segment to be written { F, D }, rotor step (1.6)；D1Overturning is D2When, D1In each binary zero position become " 1 " position,
" 1 " position becomes " 0 " position；
(1.5) new data element D1It remains unchanged, " 0 " is assigned to flip bit F, by D1It is assigned to data cell D to be written, structure
At data segment to be written { F, D }, rotor step (1.6)；
(1.6) it is written into data segment { F, D }, it is record in the corresponding chips of (K+1) × RD in caching to be saved in offset address
It is relative to legacy data section { F, D0Modification " 1 " and " 0 " number, be stored in corresponding one writing array and write " 0 " array respectively
In；
The one writing array and write " 0 " array and respectively include M/ (L × K) item record, every record in one writing array by
Serial number and data are constituted, and serial number is corresponding with the offset address cached in chip, and data are data segment to be written { F, D } relative to old
Data segment { F, D0Modification " 1 " number；It writes every in " 0 " array record to be made of serial number and data, serial number and core
The offset address cached in piece corresponds to, and data are data segment to be written { F, D } relative to legacy data section { F, D0Modification " 0 "
Number；M is the digit of cache lines, and K is the size of chip r/w cell, and L is number of chips in a memory bank；The dimension of K is position；
(1.7) it assigns the value of RD+1 to RD, judges whether RD=M/ (L × K), be to go to step (2), otherwise rotor step
(1.2)；
(2) data step, including following sub-steps are analyzed：
(2.1) one writing queue is established respectively and writes " 0 " queue, and one writing queue and to write " 0 " queue be fifo queue is write
It " 1 " queue and writes every of " 0 " queue record and is constituted by executing number, data cell serial number and data；Number is executed to correspond to
The serial number of execution sequence is written, data cell serial number is corresponding with the offset address cached in chip, and data are data sheet to be written
First content, multiple data cells can have it is identical execute number, indicate that these data cells should execute sequence same
Chip is written；
Each item record in global energy consumption budget array WU is initialized as 0, the overall situation energy consumption budget array WU include M/ (L ×
K) item records, and every record is made of execution number and its corresponding write-in chip energy consumption, is gone to step (2.2)；
(2.2) it to one writing array, is solved by MaxPB algorithms, determines that the data cell to be written of parallel one writing executes sequence,
Form one writing queue, rotor step (2.3)；
(2.3) it to writing " 0 " array, is solved by MaxPB algorithms, determines that the data cell to be written of concurrent write " 0 " executes sequence,
" 0 " queue is write in formation, goes to step (3)；
(3) one writing step, including following sub-steps：
(3.1) the value start of setting write-in initial address register, size are the position (j+m+n), and value is that caching row address is posted
The value q of write sequence counter is set as 1 by the position (j+m+n) after storage；J=0,1,2 or 3, m=9~16, n=1~5；
(3.2) judge whether one writing queue is empty, is to go to step (4)；Otherwise sub-step (3.3) is carried out；
(3.3) each item record for executing that number is q is taken out from one writing queue, is selected according to their corresponding data cell serial numbers
Corresponding data cell to be written is selected, sub-step (3.4) is carried out；
(3.4) it is written into data cell and is carried out with the data cell that offset address in read buffer is corresponding data cell serial number
XOR logic operation obtains XOR logic operation result, carries out sub-step (3.5)；
(3.5) judge whether that the XOR logic operation result and the corresponding positions of data cell to be written are " 1 ", then will be
" 1 " write storage unit address is in the storage unit of (start+ data cell serial numbers+p), otherwise without any operation；
Sub-step (3.6) is carried out, p is the corresponding positions of data cell to be written；
(3.6) value of q+1 is assigned to the value q of write sequence counter, rotor step (3.2)；
(4) " 0 " step, including following sub-steps are write：
(4.1) judge to write whether " 0 " queue is empty, be that then write operation is completed；Otherwise sub-step (4.2) is carried out；
(4.2) it from each item record that taking-up execution number is q in " 0 " queue is write, is selected according to their corresponding data cell serial numbers
Corresponding data cell to be written is selected, sub-step (4.3) is carried out；
(4.3) it is written into data cell and is carried out with the data cell that offset address in read buffer is corresponding data cell serial number
XOR logic operation obtains XOR logic operation result, carries out sub-step (4.4)；
(4.4) judge whether that the XOR logic operation result corresponding positions are " 1 " and the corresponding positions of data cell to be written are
" 0 ", be then by " 0 " write storage unit address be (start+ data cell serial numbers+p) storage unit in, otherwise not into
Any operation of row；Carry out sub-step (4.5)；
(4.5) value of q+1 is assigned to the value q of write sequence counter, rotor step (4.1).
2. phase transition storage method for writing data as described in claim 1, it is characterised in that：
In the sub-step (2.2) of the analysis data step, the MaxPB algorithms include following processes：
The maximum energy consumption budget PBmax that chip r/w cell allows is arranged in (2A), and PBmax is determined by Chip scale；By execution sequence
The value w of counter is set to 1；
(2B) calculates the power consumption values of each data cell to be written, and is put into power consumption values array IN；Data cell is handled
The value i of counter is set to 1, carries out process (2C)；
The power consumption values array IN includes M/ (L × K) item record, and every record is made of serial number and data, serial number and chip
The offset address of interior caching corresponds to, and data are the power consumption values of data cell to be written；
The power consumption values of the data cell to be written are multiplied by for the data of respective record in one writing array in sub-step (1.6) to be write
Energy consumption needed for " 1 "；Wherein, energy consumption needed for one writing is determined by Chip scale；
(2C) for the power consumption values array IN, the size of data recorded according to every carries out descending sort to all records, and
Each item is recorded according to pending queue is sequentially put into after sequence, journey (2D) is turned over；
(2D) judges whether pending queue is empty, is to carry out process (2E)；Otherwise journey (2F) is turned over；
(2E) forms one writing queue, and analysis scheduling is completed；
(2F) takes out a record from pending queue head, carries out process (2G)；
(2G) traverses before WU arrays w, judges whether (IN [i]+WU [w]) ＜ PBmax, is to turn over journey (2H)；Otherwise it turns over
Journey (2I)；In above-mentioned judgement formula, IN [i] indicates that the data of i-th record in power consumption values array IN, WU [w] indicate global energy consumption
The write-in chip energy consumption that number is w is executed in budget array WU；
(2H) is recorded using w as number, the serial number for recording i-th in IN is executed as data cell serial number, by i-th in IN
Serial number correspond to data cell to be written as data, constitute a record, be added to one writing queue tail of the queue；
Meanwhile assigning the value of WU [w]+IN [i] to WU [w], it assigns the value of i+1 to i, turns over journey (2D)；
(2I) assigns the value of W+1 to w, turns over journey (2H).
3. phase transition storage method for writing data as described in claim 1, it is characterised in that：
In the sub-step (2.3) of the analysis data step, the MaxPB algorithms include following processes：
The maximum energy consumption budget PBmax that chip r/w cell allows is arranged in (2A), and PBmax is determined by Chip scale；The value of W+1 is assigned
It is worth to the value w for executing sequence counter；
(2B) calculates the power consumption values of each data cell to be written, and is put into power consumption values array IN；Data cell is handled
The value i of counter is set to 1, carries out process (2C)；
The power consumption values array IN includes M/ (L × K) item record, and every record is made of serial number and data, serial number and chip
The offset address of interior caching corresponds to, and data are the power consumption values of data cell to be written；
The power consumption values of the data cell to be written are to write the data of respective record in " 0 " array in sub-step (1.6) to be multiplied by and write
Energy consumption needed for " 0 "；Wherein, energy consumption needed for " 0 " is write to be determined by Chip scale；
(2C) for the power consumption values array IN, the size of data recorded according to every carries out descending sort to all records, and
Each item is recorded according to pending queue is sequentially put into after sequence, journey (2D) is turned over；
(2D) judges whether pending queue is empty, is to carry out process (2E)；Otherwise journey (2F) is turned over；
" 0 " queue is write in (2E) formation, and analysis scheduling is completed；
(2F) takes out a record from pending queue head, carries out process (2G)；
(2G) traverses before WU arrays w, judges whether (IN [i]+WU [w]) ＜ PBmax, is to turn over journey (2H)；Otherwise it turns over
Journey (2I)；In above-mentioned judgement formula, IN [i] indicates that the data of i-th record in power consumption values array IN, WU [w] indicate global energy consumption
The write-in chip energy consumption that number is w is executed in budget array WU；
(2H) is recorded using w as number, the serial number for recording i-th in IN is executed as data cell serial number, by i-th in IN
Serial number correspond to data cell to be written as data, constitute a record, be added to and write " 0 " queue tail of the queue；
Meanwhile assigning the value of WU [w]+IN [i] to WU [w], it assigns the value of i+1 to i, turns over journey (2D)；(2I) assigns the value of w+1
W is given, journey (2H) is turned over.
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