CN106054472B - Low-temperature polysilicon film transistor array substrate and preparation method thereof, liquid crystal display panel - Google Patents
Low-temperature polysilicon film transistor array substrate and preparation method thereof, liquid crystal display panel Download PDFInfo
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- CN106054472B CN106054472B CN201610701193.2A CN201610701193A CN106054472B CN 106054472 B CN106054472 B CN 106054472B CN 201610701193 A CN201610701193 A CN 201610701193A CN 106054472 B CN106054472 B CN 106054472B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
Abstract
The invention discloses a kind of low-temperature polysilicon film transistor array substrates, and the non-display portion of the display unit including substrate, on substrate and the edge extension by display unit, non-display portion includes: the complex metal layer on substrate；Flatness layer on complex metal layer；By the first through hole of part complex metal layer exposure in flatness layer；Common electrode layer on flatness layer；Cover the passivation layer of the complex metal layer of common electrode layer and exposure；Part common electrode layer is exposed the exposure of part complex metal layer, third through-hole by the second through-hole and third through-hole in the passivation layer, the second through-hole；Electric connection layer on the passivation layer, electric connection layer fill the second through-hole and third through-hole respectively, to contact respectively with complex metal layer and common electrode layer.Since in the manufacturing process of passivation layer, the metal oxide that the composition metal layer surface that can contact passivation layer is formed is removed, so as to improve the contact condition of complex metal layer and common electrode layer, and then product quality is promoted.
Description
Technical field
The invention belongs to technical field of liquid crystal display, in particular, being related to a kind of low-temperature polysilicon film transistor array
Substrate and preparation method thereof, liquid crystal display panel.
Background technique
With the evolution of photoelectricity and semiconductor technology, the fluffy of flat-panel monitor (Flat Panel Display) has also been driven
The exhibition of breaking out, and in many flat-panel monitors, liquid crystal display (Liquid Crystal Display, abbreviation LCD) is because having
Many advantageous characteristics such as high spatial utilization efficiency, low consumpting power, radiationless and low EMI, it has also become the master in market
Stream.
Currently, as LCD switch element and that be widely used is amorphous silicon membrane triode (a-Si TFT), but a-Si
TFT LCD is still restricted meeting the requirements such as slim, light weight, high-fineness, high brightness, high reliability, low-power consumption.Low temperature is more
Crystal silicon (Lower Temperature Polycrystal Silicon, LTPS) TFT LCD compared with a-Si TFT LCD,
In terms of meeting above-mentioned requirements, have a clear superiority.
However, public voltage signal is by LTPS array substrate in the manufacturing process of existing LTPS array substrate
Viewing area (i.e. the area AA) periphery flatness layer (PLN) in via hole be sent to public electrode, and below the flatness layer on periphery
Signal wire be formed by composite metal structures (such as Ti/Al/Ti structure), but Ti (titanium) metal in processing environment and
It is easily aoxidized in processing procedure (as toasted) environment afterwards, to form TiOx, and TiOxResistance value is higher and is not easy to remove, and easily causes
Public voltage signal input is abnormal, to cause product display characteristic bad.
Summary of the invention
In order to solve the above technical problems, the purpose of the present invention is to provide a kind of low-temperature polysilicon film transistor battle arrays
Column substrate, comprising: substrate is arranged display unit on the substrate and is extended by the edge of the display unit non-display
Portion, the display unit include multiple low-temperature polysilicon film transistors of array arrangement, and the non-display portion includes: on substrate
Complex metal layer；Flatness layer on the complex metal layer；First through hole in the flatness layer, the first through hole
By the exposure of part complex metal layer；Common electrode layer on the flat laye；Cover the common electrode layer and exposure
The passivation layer of complex metal layer；The second through-hole and third through-hole in the passivation layer, second through-hole are compound by part
Metal layer exposure, the third through-hole expose part common electrode layer；Electric connection layer on the passivation layer, it is described to be electrically connected
It connects layer and fills second through-hole and the third through-hole respectively, with the common electrical respectively with exposed complex metal layer and exposure
Pole layer contact.
Further, the complex metal layer includes: the first metal layer, the second metal set gradually on the substrate
Layer and third metal layer.
Further, the first metal layer and the third metal layer are made of titanium, and the second metal layer uses
Aluminium is made.
Further, the display unit further includes the pixel that the drain electrode with each low-temperature polysilicon film transistor is connected
Electrode, the pixel electrode are formed simultaneously with the electric connection layer, and the pixel electrode and the electric connection layer are independent of one another.
Further, the pixel electrode and the electric connection layer are all made of tin indium oxide and are made.
Another object of the present invention, which also resides in, provides a kind of production method of low-temperature polysilicon film transistor array substrate,
The production method includes: the non-display portion for forming display unit on substrate and being extended by the edge of the display unit；It is described
The specific production method of display unit includes: multiple low-temperature polysilicon film transistors that array arrangement is formed on substrate, described
The specific production method of non-display portion includes: that complex metal layer is formed on substrate；It is formed on the complex metal layer flat
Layer；First through hole is formed in the flatness layer；The first through hole exposes part complex metal layer；On the flat laye
Form common electrode layer；Form the passivation layer for covering the complex metal layer of the common electrode layer and exposure；In the passivation
The second through-hole and third through-hole are formed in layer；Second through-hole is by the exposure of part complex metal layer, and the third through-hole is by portion
Divide common electrode layer exposure；Electric connection layer is formed on the passivation layer；The electric connection layer fills second through-hole respectively
With the third through-hole, to be contacted respectively with the common electrode layer of exposed complex metal layer and exposure.
Further, the specific method that the complex metal layer is formed on substrate includes: to utilize titanium on the substrate
Material forms the first metal layer；Second metal layer is formed using aluminum material on the first metal layer；In second metal
Third metal layer is formed using titanium material on layer.
Further, the specific production method of the display unit further include: formed and each low-temperature polysilicon film crystal
The pixel electrode that the drain electrode of pipe is connected；Wherein, the pixel electrode is formed simultaneously with the electric connection layer, and pixel electricity
Pole and the electric connection layer are independent of one another.
Further, the pixel electrode and the electric connection layer are formed simultaneously using tin indium oxide.
A further object of the present invention is to provide a kind of liquid crystal display panel again, and color membrane substrates and low temperature including box is arranged are more
Polycrystal silicon film transistor (TFT) array substrate, the low-temperature polysilicon film transistor array substrate are above-mentioned low-temperature polysilicon film
Transistor (TFT) array substrate, or the low-temperature polysilicon film transistor array substrate is made using above-mentioned production method.
Beneficial effects of the present invention: due to directly forming passivation layer on the part complex metal layer of first through hole exposure,
And in the manufacturing process of passivation layer, it can be effectively by the top-level metallic oxygen of the part complex metal layer exposed by first through hole
Compound (metal oxide i.e. on the surface of third metal layer) removal, so as to improve connecing for complex metal layer and common electrode layer
Touching situation, and then promote product quality.
Detailed description of the invention
What is carried out in conjunction with the accompanying drawings is described below, above and other aspect, features and advantages of the embodiment of the present invention
It will become clearer, in attached drawing:
Fig. 1 is the top view of the low-temperature polysilicon film transistor array substrate of embodiment according to the present invention；
Fig. 2 is the low-temperature polysilicon film transistor of embodiment according to the present invention and the structural schematic diagram of pixel electrode；
Fig. 3 is A-A in Fig. 1 to sectional view；
Fig. 4 is the flow chart of the production method of the non-display portion of embodiment according to the present invention；
Fig. 5 is the structural schematic diagram of the liquid crystal display panel of embodiment according to the present invention.
Specific embodiment
Hereinafter, with reference to the accompanying drawings to detailed description of the present invention embodiment.However, it is possible to come in many different forms real
The present invention is applied, and the present invention should not be construed as limited to the specific embodiment illustrated here.On the contrary, providing these implementations
Example is in order to explain the principle of the present invention and its practical application, to make others skilled in the art it will be appreciated that the present invention
Various embodiments and be suitable for the various modifications of specific intended application.In the accompanying drawings, identical label will be used for table always
Show identical element.
Fig. 1 is the top view of the low-temperature polysilicon film transistor array substrate of embodiment according to the present invention.Fig. 2 is root
According to the low-temperature polysilicon film transistor of the embodiment of the present invention and the structural schematic diagram of pixel electrode.Fig. 3 is the A-A in Fig. 1
To sectional view.
Referring to figs. 1 to Fig. 3, the low-temperature polysilicon film transistor array substrate of embodiment according to the present invention includes: base
Plate 100 is arranged display unit (or viewing area) 200 on the substrate 100 and is extended by the edge of display unit 200 non-display
Portion's (or non-display area) 300.
Specifically, substrate 100 can be transparent glass substrate or resin substrate.Display unit 200 and non-display portion
300 are arranged on the same surface of substrate 100.During the processing procedure of low-temperature polysilicon film transistor array substrate, display
Portion 200 and non-display portion 300 are formed simultaneously on the same surface of substrate 100.In general, display unit 200 includes array arrangement
Multiple low-temperature polysilicon film transistors 210 and the picture being connect with the drain electrode 211 of each low-temperature polysilicon film transistor 210
Plain electrode 220.Certainly, it should be noted that also may include in display unit 200 data line being staggered and grid line and
Other necessary elements.
Non-display portion 300 will be described in detail below.With continued reference to Fig. 1 to Fig. 3, non-display portion 300 includes: multiple
Metal layer 310, flatness layer 320, common electrode layer 330, passivation layer 340 and electric connection layer 350.
Specifically, complex metal layer 310 is arranged on the substrate 100.It should be noted that complex metal layer 310 and low temperature
The grid (not shown) of polycrystalline SiTFT 210 is formed simultaneously.Further, as a preference, complex metal layer 310
It include: the first metal layer 311, second metal layer 312 and the third metal layer 313 set gradually on the substrate 100, but the present invention
It is not restricted to this, such as complex metal layer 310 may include two metal layers, four layers of metal layer or more layers metal layer.
In this embodiment, it is preferred that the first metal layer 311 and third metal layer 313 are made of titanium (Ti), and second metal layer 312
It is made of aluminium (Al)；But the present invention is not restricted to this, such as this three-layer metal layer also can use other conductive metal materials
Material is made.In this way, the grid of complex metal layer 310 and low-temperature polysilicon film transistor 210 all has Ti/Al/Ti metal knot
Structure.
Flatness layer 320 is arranged on complex metal layer 310, and first through hole 321 is formed in flatness layer 320, this is first logical
Part third metal layer 313 is exposed the exposure of part complex metal layer 310, the i.e. first through hole 321 by hole 321.It needs to illustrate
, also there is flatness layer (not shown), and the flatness layer is formed simultaneously with flatness layer 320 in display unit 200.
Common electrode layer 330 is arranged on flatness layer 320.It should be noted that also having public electrode in display unit 200
Layer (not shown), and the common electrode layer is formed simultaneously and is electrically connected to each other with common electrode layer 330.
Passivation layer 340 is covered on the complex metal layer 310 of common electrode layer 330 and exposure, is formed in passivation layer 340
Second through-hole 341 and third through-hole 342, second through-hole 341 will by the exposure of part complex metal layer 310, the third through-hole 342
The exposure of part common electrode layer 330.It should be noted that also there is passivation layer (not shown), and the passivation layer in display unit 200
It is formed simultaneously with passivation layer 340.
Electric connection layer 350 is arranged on passivation layer 340, and electric connection layer 350 fills the second through-hole 341 and third respectively
Through-hole 342, to be contacted respectively with the common electrode layer 330 of exposed complex metal layer 310 and exposure, to make complex metal layer
310 and common electrode layer 330 be electrically connected so that public voltage signal is transferred to public electrode by complex metal layer 310
Layer 330, and then the common electrode layer being transferred in display unit 200.It should be noted that the electric connection layer 350 and pixel electrode
220 are formed simultaneously, but the two is independent of one another.Preferably, electric connection layer 350 and pixel are formed simultaneously using transparent tin indium oxide
Electrode 220, but the present invention is not restricted to this, both is made using also can use other conductive materials.
Due to directly forming passivation layer 340 on the part complex metal layer 310 exposed by first through hole 321, and blunt
It, can be effectively by the top layer gold of the part complex metal layer 310 exposed by first through hole 321 in the manufacturing process for changing layer 340
Belong to oxide (metal oxide i.e. on the surface of third metal layer 313) removal, so as to improve complex metal layer 310 and public
The contact condition of electrode layer 330, and then promote product quality.
Below by the production method of the low-temperature polysilicon film transistor array substrate to embodiment according to the present invention into
Row explanation.Referring to Fig.1, firstly, providing a substrate 100.Then, display unit 200 is formed on the substrate 100 and by display unit
The non-display portion (or non-display area) 300 that 200 edge extends.
The specific production method of display unit 200 are as follows: form multiple low-temperature polysilicon films of array arrangement on the substrate 100
Transistor 210；Form the pixel electrode 220 being connected with the drain electrode 211 of each low-temperature polysilicon film transistor 210.Each
The production method that the production method of low-temperature polysilicon film transistor 210 uses the low-temperature polysilicon film transistor of the prior art
, details are not described herein.
The production method of the non-display portion 300 to embodiment according to the present invention is described in detail below.Fig. 4 is root
According to the flow chart of the production method of the non-display portion of the embodiment of the present invention.
Referring to figs. 1 to Fig. 4, in step S410, complex metal layer 310 is formed on the substrate 100.It should be noted that
Complex metal layer 310 and the grid 212 of low-temperature polysilicon film transistor 210 are formed simultaneously.
Further, the production method of complex metal layer 310 specifically includes: forming the first gold medal using titanium on the substrate 100
Belong to layer 311；Second metal layer 312 is formed using aluminium on the first metal layer 311；And titanium is utilized in second metal layer 312
Form third metal layer 313.In this way, the grid of complex metal layer 310 and low-temperature polysilicon film transistor 210 all has Ti/
Al/Ti metal structure.
In the step s 420, flatness layer 320 is formed on complex metal layer 310.It should be noted that in display unit 200
Also there is flatness layer (not shown), and the flatness layer is formed simultaneously with flatness layer 320.
In step S430, first through hole 321 is formed in flatness layer 320；The first through hole 321 will be by the compound gold in part
Belong to the exposure of layer 310, i.e. the first through hole 321 exposes part third metal layer 313.
In step S440, common electrode layer 330 is formed on flatness layer 320.It should be noted that in display unit 200
Also there is common electrode layer (not shown), and the common electrode layer is formed simultaneously and is electrically connected to each other with common electrode layer 330.
In step S450, the complex metal layer 310 for covering common electrode layer 330 and being exposed by first through hole 321 is formed
Passivation layer 340.It should be noted that also there is passivation layer (not shown), and the passivation layer and passivation layer in display unit 200
340 are formed simultaneously.
In step S460, the second through-hole 341 and third through-hole 342 are formed in passivation layer 340, second through-hole 341
By the exposure of part complex metal layer 310, which exposes part common electrode layer 330.
In step S470, electric connection layer 350 is formed on passivation layer 340, it is logical which fills second respectively
Hole 341 and third through-hole 342, with sudden and violent with the complex metal layer 310 by the exposure of the second through-hole 341 and by third through-hole 342 respectively
The common electrode layer 330 of dew contacts.In this way, complex metal layer 310 and common electrode layer 330 can be made to be electrically connected, so that
Public voltage signal is transferred to common electrode layer 330 by complex metal layer 310, and then is transferred to public in display unit 200
Electrode layer.It should be noted that the electric connection layer 350 is formed simultaneously with pixel electrode 220, but the two is independent of one another.
Fig. 5 is the structural schematic diagram of the liquid crystal display panel of embodiment according to the present invention.
Referring to Fig. 5, the liquid crystal display panel of embodiment according to the present invention includes: the low-temperature polysilicon film crystal to box setting
Pipe array substrate 1000 and color membrane substrates 2000, and it is located in low-temperature polysilicon film transistor array substrate 1000 and color film
Liquid crystal layer 3000 between substrate 2000.There are several liquid crystal molecules in liquid crystal layer 3000.Here, low-temperature polysilicon film crystal
Pipe array substrate 1000 is Fig. 1 and low-temperature polysilicon film transistor array substrate shown in Fig. 3, alternatively, low temperature polycrystalline silicon is thin
Film transistor array substrate 1000 is the low-temperature polysilicon film transistor array substrate made of above-mentioned production method.This
Outside, color membrane substrates 2000 generally include the colored filter being made of red (R) optical filter, green (G) optical filter, indigo plant (B) optical filter,
Black matrix", alignment film etc..The structure of color membrane substrates please refers to the relevant prior art in further detail, and which is not described herein again.
Although the present invention has shown and described referring to specific embodiment, it should be appreciated by those skilled in the art that:
In the case where not departing from the spirit and scope of the present invention being defined by the claims and their equivalents, can carry out herein form and
Various change in details.
Claims (10)
1. a kind of low-temperature polysilicon film transistor array substrate, comprising: substrate, setting display unit on the substrate and
The non-display portion extended by the edge of the display unit, the display unit include that multiple low-temperature polysilicon films of array arrangement are brilliant
Body pipe, which is characterized in that the non-display portion includes:
Complex metal layer on substrate；
Flatness layer on the complex metal layer；
First through hole in the flatness layer, the first through hole expose part complex metal layer；
Common electrode layer on the flat laye；
Cover the passivation layer of the complex metal layer of the common electrode layer and exposure；
The second through-hole and third through-hole in the passivation layer, second through-hole exposes part complex metal layer, described
Third through-hole exposes part common electrode layer；
Electric connection layer on the passivation layer, the electric connection layer fill second through-hole and the third through-hole respectively,
To be contacted respectively with the common electrode layer of exposed complex metal layer and exposure.
2. low-temperature polysilicon film transistor array substrate according to claim 1, which is characterized in that the composition metal
Layer includes: the first metal layer, second metal layer and the third metal layer set gradually on the substrate.
3. low-temperature polysilicon film transistor array substrate according to claim 2, which is characterized in that first metal
Layer and the third metal layer are made of titanium, and the second metal layer, which is adopted, to be formed from aluminium.
4. low-temperature polysilicon film transistor array substrate according to claim 1, which is characterized in that the display unit is also
Including the pixel electrode that the drain electrode with each low-temperature polysilicon film transistor is connected, the pixel electrode is electrically connected with described
Layer is formed simultaneously, and the pixel electrode and the electric connection layer are independent of one another.
5. low-temperature polysilicon film transistor array substrate according to claim 4, which is characterized in that the pixel electrode
Tin indium oxide is all made of with the electric connection layer to be made.
6. a kind of production method of low-temperature polysilicon film transistor array substrate, the production method include: the shape on substrate
At display unit and the non-display portion extended by the edge of the display unit；
Wherein, the specific production method of the display unit includes: that multiple low temperature polycrystalline silicons of the formation array arrangement on substrate are thin
Film transistor；
It is characterized in that, the specific production method of the non-display portion includes:
Complex metal layer is formed on substrate；
Flatness layer is formed on the complex metal layer；
First through hole is formed in the flatness layer；The first through hole exposes part complex metal layer；
Common electrode layer is formed on the flat laye；
Form the passivation layer for covering the complex metal layer of the common electrode layer and exposure；
The second through-hole and third through-hole are formed in the passivation layer；Second through-hole exposes part complex metal layer, institute
Third through-hole is stated by the exposure of part common electrode layer；
Electric connection layer is formed on the passivation layer；The electric connection layer fills second through-hole respectively and the third is logical
Hole, to be contacted respectively with the common electrode layer of exposed complex metal layer and exposure.
7. the production method of low-temperature polysilicon film transistor array substrate according to claim 6, which is characterized in that
The specific method that the complex metal layer is formed on substrate includes:
The first metal layer is formed using titanium material on the substrate；
Second metal layer is formed using aluminum material on the first metal layer；
Third metal layer is formed using titanium material in the second metal layer.
8. the production method of low-temperature polysilicon film transistor array substrate according to claim 6, which is characterized in that institute
State the specific production method of display unit further include: form the pixel being connected with the drain electrode of each low-temperature polysilicon film transistor
Electrode；Wherein, the pixel electrode is formed simultaneously with the electric connection layer, and the pixel electrode and the electric connection layer are each other
It is independent.
9. the production method of low-temperature polysilicon film transistor array substrate according to claim 8, which is characterized in that benefit
The pixel electrode and the electric connection layer are formed simultaneously with tin indium oxide.
10. a kind of liquid crystal display panel, special including the color membrane substrates that box is arranged and low-temperature polysilicon film transistor array substrate
Sign is that the low-temperature polysilicon film transistor array substrate is that low temperature polycrystalline silicon described in any one of claim 1 to 5 is thin
Film transistor array substrate, or using the described in any item production methods of claim 6 to 9 low temperature polycrystalline silicon to be made thin
Film transistor array substrate.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103913905A (en) * | 2012-12-31 | 2014-07-09 | 三星显示有限公司 | Display device |
| CN105047606A (en) * | 2014-04-29 | 2015-11-11 | 乐金显示有限公司 | Rework method of array substrate for display device and array substrate formed by the method |
| CN105590896A (en) * | 2016-03-01 | 2016-05-18 | 深圳市华星光电技术有限公司 | Manufacturing method of array substrate and manufactured array substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101293130B1 (en) * | 2010-05-28 | 2013-08-12 | 엘지디스플레이 주식회사 | Array substrate and method of fabricating the same |
| CN104965365A (en) * | 2015-07-14 | 2015-10-07 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and array substrate thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103913905A (en) * | 2012-12-31 | 2014-07-09 | 三星显示有限公司 | Display device |
| CN105047606A (en) * | 2014-04-29 | 2015-11-11 | 乐金显示有限公司 | Rework method of array substrate for display device and array substrate formed by the method |
| CN105590896A (en) * | 2016-03-01 | 2016-05-18 | 深圳市华星光电技术有限公司 | Manufacturing method of array substrate and manufactured array substrate |
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