CN1060541A - A kind of random signal generator of digital any probability distribution - Google Patents
A kind of random signal generator of digital any probability distribution Download PDFInfo
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- CN1060541A CN1060541A CN 91108346 CN91108346A CN1060541A CN 1060541 A CN1060541 A CN 1060541A CN 91108346 CN91108346 CN 91108346 CN 91108346 A CN91108346 A CN 91108346A CN 1060541 A CN1060541 A CN 1060541A
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Abstract
The present invention utilizes even distributed random sequence that binary random sequence generator produces to go to choose any given probability distributed random signal sample value in the memory as address signal, produce the digital random signal of given probability distribution, produce the simulation random signals of same probability distribution again by the D/A transducer.Have simple in structurely, be easy to realize that advantages such as frequency band broad can be widely used in signal Processing, radar and communication field.
Description
The invention relates to a kind of random signal generator that can produce any given probability distribution.
As everyone knows, existing digital random signal generator mainly is according to a series of complex calculations by computing machine, produce the digital random signal of any given probability distribution, as being changed to the simulation random signals of any given probability distribution by the D/A transducer.The limitation of this method need to be a computing machine, and the random signal bandwidth that is produced is subjected to the restriction of computer speed, especially when the probability distribution of random parameter was comparatively complicated, computing machine need could produce a signal value through the long period, and the bandwidth of random signal is narrowed down.
The present invention is intended to design a kind of digital random signal generator of broadband, has to be easy to realize that bandwidth and probability distribution be controlled characteristics arbitrarily.
Technical solution of the present invention is the random signal generator of design shown in accompanying drawing one, and wherein 1 is the memory that has solidified the random signal sample value, and 2 is the binary random sequence generator, the 3rd, and the D/A transducer.Basic design concept is to go to choose the random signal sample value of solidifying any given probability distribution of depositing in the random signal sample value memory as the address with the equally distributed random digital signal that the binary random sequence generator produces, produce the digital random signal of any given probability distribution, by the then variable random signal that is changed to simulation of D/A transducer.
It is that the random signal sample value of various probability distribution is deposited (curing) in non-volatile memory medium (PROM, EPROM etc.) that random signal sample value random memory (1) is solidified in the present invention.For the random signal of a certain given probability distribution, on amplitude, it is quantized (by evenly at interval) earlier, suppose to be quantified as N at interval, the signal value after the quantification is D
1, D
2D
N, (these data are the data that will deposit in memory) calculates stochastic variable according to probability density function or distribution function then and is separated out existing probability at each, with P
1, P
2P
NExpression, obviously ∑ P
i=1.If deposit M data in the memory, then M data are changed according to quantity and are divided into N group (every group of data difference, numerical value difference) at interval, i group data value is Di, and the data number is MPi, gets final product after this M data are deposited by this grouping, can deposit in proper order when depositing, also can deposit at random.M is big more, and it is high more that quantized interval is counted N, and then the random signal of Chan Shenging approaches actual simulating signal more.Deposit the random signal sample value of other probability distribution by this method segmentation.
Binary random sequence generator of the present invention (2) is formed (accompanying drawing 2) by shift register and XOR circuit, last two first of sending into register behind XOR of shift register.Under the control of a high frequency clock Ts, shift register constantly is shifted with the result to XOR fortune, and the binary condition sequence of " 0 " and " 1 " that the output equiprobability distributes can prove the shift register for the K position, and the maximum length of sequence is 2
K-1, if K=50, then length is 10
15, under 1000MHz clock Ts control, the curing time of sequence is 300 hours, it can be regarded as the signal of completely random in the case.Take up an official post at shift register and to get L tap output, group is the binary number of a L position, then can obtain one 0 to 2
LEqually distributed random digital signal between-1 goes to choose as address signal with this and solidifies in the random signal sample value memory by the random signal sample value of given probability distribution, can obtain required random signal.Control the frequency of clock Ts, can produce the random signal of different bandwidth.
Advantage of the present invention is that the memory capacity of cycle and the random sample value memory (1) of the random signal that produces has nothing to do, the cycle (deciding) of only depending on binary pseudo random sequence by shift register length, therefore, select long shift register for use, (as the K=50 of precedent, length is 10 can to obtain the random signal of longer cycle
15).And can produce the digital random signal of any given probability distribution, it can be transformed to the simulation random signals of same probability distribution,, then can produce the random signal of broad spectrum if the D/A converter frequency that adopts is enough high by the D/A transducer.This simple in structure, cost is low, be easy to realize, can be widely applied in signal Processing, communication and the radar system research, to simulate the actual working environment of these systems.
The present invention has following accompanying drawing:
Fig. 1 is an electrical schematic diagram of the present invention
Wherein: the 1st, solidify random signal sample value memory, the 2nd, binary random sequence generator, the 3rd, D/A transducer.
Fig. 2 is a binary random sequence generator electrical schematic diagram.
One embodiment of the present of invention are to produce an equally distributed random signal, in EPOM, evenly solidify the number between 0 to 255, the shift register of binary random sequence generator has a parallel set by several altogether, and line output, the register of serial input function is in series, 8 parallel output terminal mouths of optional register are as address signal, equally distributed digital random signal between then can producing 0 to 255, select suitable D/A transducer for use, then can produce 256 equally distributed simulation random signalses in interval.As stated above, in memory, solidify the sample value of other probability distribution, then can produce random signal by given probability distribution.
Claims (4)
1, a kind of random signal generator of digital any probability distribution, the L bit sequence that it is characterized in that being produced by binary random sequence generator (2) is as address signal, to choose any given probability distributed random signal sample value of solidifying in the random signal sample value memory (1), generation requires the digital random signal of probability distribution, becomes the simulation random signals of same probability distribution by D/A transducer (3).
2, by the described curing random signal of claim 1 sample value memory, it is characterized in that the random signal to requiring, uniform quantization is N interval on amplitude, quantizes the matter signal value and is respectively D
1, D
2D
N, probability of occurrence is respectively P
1, P
2P
N,, then deposit D if deposit M data
1Number be P
1M.
3, by claim 1,2 described random signal generators, it is characterized in that the binary random sequence generator is made up of the shift register and an XOR gate of a K position, choose L tap wantonly as address signal.
4, by the described shift register of claim 3, it is characterized in that having parallel set by several, and line output, the register of serial input function is in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 91108346 CN1021379C (en) | 1991-11-16 | 1991-11-16 | Digitized random signal generator with arbitrary probability distribution |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 91108346 CN1021379C (en) | 1991-11-16 | 1991-11-16 | Digitized random signal generator with arbitrary probability distribution |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1060541A true CN1060541A (en) | 1992-04-22 |
| CN1021379C CN1021379C (en) | 1993-06-23 |
Family
ID=4909245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 91108346 Expired - Fee Related CN1021379C (en) | 1991-11-16 | 1991-11-16 | Digitized random signal generator with arbitrary probability distribution |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1021379C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102208210A (en) * | 2010-03-31 | 2011-10-05 | 深圳市朗科科技股份有限公司 | Flash memory device and data storage method thereof |
| CN102999085A (en) * | 2012-11-27 | 2013-03-27 | 中国兵器科学研究院 | Lognormal clutter implementation method and device |
| CN104980185A (en) * | 2015-06-24 | 2015-10-14 | 电子科技大学 | Non-uniform arbitrary probability distribution frequency hopping sequence generation method |
| CN110764733A (en) * | 2019-10-15 | 2020-02-07 | 天津津航计算技术研究所 | FPGA-based multi-distribution random number generation device |
-
1991
- 1991-11-16 CN CN 91108346 patent/CN1021379C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102208210A (en) * | 2010-03-31 | 2011-10-05 | 深圳市朗科科技股份有限公司 | Flash memory device and data storage method thereof |
| CN102999085A (en) * | 2012-11-27 | 2013-03-27 | 中国兵器科学研究院 | Lognormal clutter implementation method and device |
| CN102999085B (en) * | 2012-11-27 | 2015-05-20 | 中国兵器科学研究院 | Lognormal clutter implementation method and device |
| CN104980185A (en) * | 2015-06-24 | 2015-10-14 | 电子科技大学 | Non-uniform arbitrary probability distribution frequency hopping sequence generation method |
| CN110764733A (en) * | 2019-10-15 | 2020-02-07 | 天津津航计算技术研究所 | FPGA-based multi-distribution random number generation device |
| CN110764733B (en) * | 2019-10-15 | 2023-06-30 | 天津津航计算技术研究所 | Multi-distribution random number generation device based on FPGA |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1021379C (en) | 1993-06-23 |
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