CN106033712A - Method for manufacturing 10nm chip in integrated manner - Google Patents
Method for manufacturing 10nm chip in integrated manner Download PDFInfo
- Publication number
- CN106033712A CN106033712A CN201510122300.1A CN201510122300A CN106033712A CN 106033712 A CN106033712 A CN 106033712A CN 201510122300 A CN201510122300 A CN 201510122300A CN 106033712 A CN106033712 A CN 106033712A
- Authority
- CN
- China
- Prior art keywords
- nano
- particle
- workbench
- processing procedure
- passage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method for manufacturing a 10nm chip in an integrated manner. In the technical process, different types of raw materials are prepared into nanometer particles of 1 or 10nm, nanometer particles reaching the standard are screened by a screening device, sent into an arrangement channel, and input to an array workbench after shaping for multiple times by the arrangement channel, a device of the array workbench lays the nanometer particles in one or multiple transistor thin layer according to requirements of a chip design drawing, and the different thin layers are stacked and bonded and then packaged into a finished chip product.
Description
Technical field
Present example relates to a kind of method that integration manufactures 10nm processing procedure chip, belongs to field of semiconductor manufacture.
Background technology
Since Moore's Law is born, semiconductor technology every two years will enter and once update, prevailing technology has been enter into 14nm processing procedure at present, Intel and Taiwan Taiwan Semiconductor Manufacturing Co. have begun to expand keen competition in the process technique of future generation such as 10nm technique, it is anticipated that 10nm technique is a commanding elevation of the chip industry coming years.
Silicon-based semiconductor has approached physics limit after entering 10nm processing procedure rank, and when when being closely sized to electron wavelength of circuit, electronics just overflows device by tunnel-effect, makes device normally to work, and the dimension limit of classical circuit is probably at 0.25 micron.
Existing chip manufacturing process long flow path, be through complicated technologies such as photocopy, photoetching, etching, vapour depositions, it is achieved automated production is more difficult, and the most various high-end devices are all monopolized by some major company.
Summary of the invention
In order to solve to appeal technical problem, various raw materials are prepared as the nano-particle of 1 ~ 10 nanometer by the present invention, after screening nano-particle up to standard by screening installation, send into and arrange passage, through arranging passage repeatedly shaping, then be input to array workbench, the device of array workbench by nano-particle by the requirement of floor layout, array goes out one layer of at most layer transistor thin layer, finally various thin layers is bonded, is packaged into chip finished product.
A kind of method that integration manufactures 10nm processing procedure chip is embodied as step:
Implement step 1: design requirement by chip, various raw materials are made the nano-particle of 1 to 10 nanometer.
Implementing step 2: the nano-particle of various models is inputted screening installation, the nano-particle of different model is separated by screening installation, and sends into arrangement passage.
Implement step 3: in arranging passage, by nano-particle flash ranging, identify nano-particle crystal orientation, and when nano-particle is rotated into uniform orientation, send into array workbench.
Implement step 4: nano-particle arrives array workbench, and nano-particle is operated by mechanical arm and array mold by array workbench, completes the array request of floor layout, i.e. chip thin layer.
Implement step 5: array workbench supercharging heats up, and nano-particle is bonded to an entirety, forms close chip thin layer.
Implementing step 6: move into probe, energising detects each transistor and conductive track, and downstream sent into by qualified products.
Implement step 7: above for two panels thin layer directly being stacked bonding, and links conductive track, after being detected by energising, qualified product becomes a complete bare chip.
The medicine have the advantages that the technology such as the photoetching of traditional handicraft of having skimmed, etching, technique is simple, it is easy to accomplish automatization and Unmanned operation, is conducive to improving production efficiency, improves product yield and reduces production cost.
Detailed description of the invention
For the purposes of the present invention, technical scheme and advantage are clearer, manufacture 10nm processing procedure chip technology below in conjunction with integration and manufacture the specific embodiment of a kind of district system chip, detailed description further to the present invention:
District's system chip design stage；
Implement step: be a kind of district of design system chip on computer special-purpose software, district's system chip is made up of two panels thin layer, wherein the raw material of circuit thin layer is conducting metal nano-particle and the insulator nano-particle of 30 ~ 60 nanometers, and bonding temperature sets 200 ~ 600 degree, bonding time 1 ~ 10 minute；Wherein the pure silicon nano-particle of 10 nanosizeds and n-type silicon nano-particle and p-type silicon nano-particle are bonded to transistor thin layer, and bonding temperature sets 600 ~ 1100 degree, bonding time 1 ~ 12 minute.
District's system chip nano-particle preparatory stage；
Implement step 1: metallic particles is put into nano-level grinder, makes the circuit thin layer nano-particle of 30 ~ 60 nanometers.
Implement step 2: produce 10 nanosized pure silicon nano-particle of transistor thin layer and n-type silicon nano-particle and p-type silicon nano-particle with vapour deposition process.
The machine fabrication stage in district's system chip integration；
Implementing step 1: the nano silicon particles of various models is inputted sound wave screening installation, the nano-particle of different model is separated by screening installation to be sorted out, and sends into arrangement passage.
Implement step 2: passing through nano-particle optical measuring device in arranging passage, identify nano-particle crystal orientation, feeding recovery approach the most up to standard, reach requirement is rotated crystal orientation, is organized into the nano-particle that all nano-particle crystal plane direction are consistent, sends into array workbench.
Implement step 4: nano-particle arrives array workbench, array workbench mechanical arm and array mold are driven by computer and nano-particle carry out arrangement operation, when all nano-grain array formations reach the array request of floor layout, and array mold is immediately fed into bonding workbench.
Implement step 5: bonding workbench supercharging heats up, and nano-particle is bonded to an entirety, forms close chip thin layer.The temperature being wherein bonded is at 300 ~ 1100 degree, and the bonding temperature of metal is at 200 ~ 600 degree.
Implement step 6: the chip thin layer of molding moves into detection workbench, drive feeler arm, energising to detect each transistor and conductive track, determine very yield rate, enter thin layer bonding workbench.
Implement step 7: when manufacturing thin metal layer, repeat to implement step 1 and arrive step 6, thin metal layer can be manufactured.
Implementing step 8: circuit thin layer is directly stacked upon on transistor thin layer by the mechanical arm of thin layer bonding workbench, after aligning key chalaza, heat up bonding, and temperature controls in bonding requires, 5 ~ 20 minutes time.After lowering the temperature, a complete bare chip has been bonded.
Embodiment described above is to complete on automated manufacturing equipment, and yield rate reaches 99.999%, and production efficiency is higher several times than traditional die manufacturing process.
Embodiment described above only have expressed one embodiment of the present invention, therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that, for the person of ordinary skill of the art, without departing from the inventive concept of the premise, it is also possible to make some deformation and improvement, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (11)
1. the method that integration manufactures 10nm processing procedure chip, it is characterised in that comprise the following steps:
A: prepare nano-particle；
B: input screening installation, chooses the nano-particle of various model；
C: arrange nano-particle in arranging passage；
D: nano-particle is input to array workbench by arranging passage, and floor layout pattern array nano-particle pressed by array workbench；
E: energising detection transistor and circuit；
F: in bonding workbench bonding molding；
G: each thin layers, aligning key chalaza are bonded to bare chip at bonding workbench.
The method that integration the most according to claim 1 manufactures 10nm processing procedure chip, it is characterised in that described a: preparing nano-particle is to obtain various nano-particle by mechanical lapping and vapour deposition.
The method that integration the most according to claim 1 manufactures 10nm processing procedure chip, it is characterised in that the screening installation of described b: input, is sound wave screening installation；Or various oscillation source drive choose screening installation, the nano-particle of model of all sizes is sorted, sends into and arrange passage.
The method that integration the most according to claim 1 manufactures 10nm processing procedure chip, it is characterised in that described c: have crystal orientation detecting system in arranging passage, detect various nano-particle crystal plane direction.
The method that integration the most according to claim 1 manufactures 10nm processing procedure chip, it is characterised in that described c: have electromagnetism to cause telescoping switch door in arranging passage, or universal joint controls nano-particle crystal orientation.
The method that integration the most according to claim 1 manufactures 10nm processing procedure chip, it is characterized in that, described c: have a more than passage in arranging passage, two passages are wherein had to synthesize a passage bonding chamber, or multiple passage aggregates into a passage bonding chamber, produce single transistor and geometry nano-particle.
The method that integration the most according to claim 1 manufactures 10nm processing procedure chip, it is characterised in that described d: nano-particle is input to array workbench by arranging passage, and array workbench has mechanical arm by floor layout pattern array nano-particle.
The method that integration the most according to claim 1 manufactures 10nm processing procedure chip, it is characterized in that, described d: nano-particle is input to array workbench by arranging passage, array workbench has more than one substrate die, substrate die is pressed the nanometer of floor layout pattern array and is fallen into, and the nano-particle of passage ejection automatically falls in mould.
The method that integration the most according to claim 1 manufactures 10nm processing procedure chip, it is characterised in that described e: energising detection transistor is that the nanometer probe system consisted of more than one nano-probe checks circuit and transistor.
The method that integration the most according to claim 1 manufactures 10nm processing procedure chip, it is characterised in that described f: at bonding workbench by controlling operating temperature, pressure and time, various nano-particle are bonded molding；Or by the laser fixed fire consistent with nano-particle, allow local heating be bonded nano-particle.
The method that 11. integrations according to claim 1 manufacture 10nm processing procedure chip, it is characterized in that, described g. is in bonding workbench just two panels thin layers, thin layer is reserved with concavo-convex falling into, mobile thin layer makes concavo-convex the falling into of two-layer mutually coincide, i.e. calibrate bonding point, calibrate bonding point intensification bonding thin layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510122300.1A CN106033712A (en) | 2015-03-20 | 2015-03-20 | Method for manufacturing 10nm chip in integrated manner |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510122300.1A CN106033712A (en) | 2015-03-20 | 2015-03-20 | Method for manufacturing 10nm chip in integrated manner |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106033712A true CN106033712A (en) | 2016-10-19 |
Family
ID=57148750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510122300.1A Pending CN106033712A (en) | 2015-03-20 | 2015-03-20 | Method for manufacturing 10nm chip in integrated manner |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106033712A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7544558B2 (en) * | 2006-03-13 | 2009-06-09 | Bcd Semiconductor Manufacturing Limited | Method for integrating DMOS into sub-micron CMOS process |
| CN102923645A (en) * | 2012-11-27 | 2013-02-13 | 北京大学 | High-density nano electrode array and preparation method thereof |
| CN103280435A (en) * | 2013-03-29 | 2013-09-04 | 上海大学 | Micro-electronic chip for realizing interconnection of high-density silicon through holes and manufacturing method of micro-electronic chip |
-
2015
- 2015-03-20 CN CN201510122300.1A patent/CN106033712A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7544558B2 (en) * | 2006-03-13 | 2009-06-09 | Bcd Semiconductor Manufacturing Limited | Method for integrating DMOS into sub-micron CMOS process |
| CN102923645A (en) * | 2012-11-27 | 2013-02-13 | 北京大学 | High-density nano electrode array and preparation method thereof |
| CN103280435A (en) * | 2013-03-29 | 2013-09-04 | 上海大学 | Micro-electronic chip for realizing interconnection of high-density silicon through holes and manufacturing method of micro-electronic chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11018112B2 (en) | Bonding method of semiconductor chip and bonding apparatus of semiconductor chip | |
| KR101523497B1 (en) | Manufacturing Method for Curved Surface Window Glass that Part of Mobile Device | |
| KR20170047282A (en) | Methods of forming shaped glass articles from glass sheets | |
| KR20140045449A (en) | Non-polished glass wafer, thinning system and method for using the non-polished glass wafer to thin a semiconductor wafer | |
| CN1341958A (en) | Chip pickup device and method for manufacturing semiconductor | |
| TW200605195A (en) | Production method of compound semiconductor device wafer | |
| KR20140126247A (en) | Wafer machining method | |
| CN104878663B (en) | Automated pulp molding production line | |
| US20230294364A1 (en) | Method for operating a metal drop ejecting three-dimensional (3d) object printer to form electrical circuits on substrates | |
| CN106033712A (en) | Method for manufacturing 10nm chip in integrated manner | |
| CN106191990A (en) | A kind of air intake installation of boiler tube | |
| CN109887860B (en) | Bonding cavity structure and bonding method | |
| CN102452174A (en) | Air pressure shaping technology of carbon fiber product and glass fiber product and used die | |
| CN107473177A (en) | A kind of preparation method of 3D solids micro-nano structure | |
| KR102397055B1 (en) | Imprint apparatus and method of manufacturing article | |
| CN114334721A (en) | Abnormal reworking method for thinning back of wafer | |
| CN209652151U (en) | A kind of bend glass hot bending shape molding component heating plate | |
| JP7280768B2 (en) | Film forming apparatus and article manufacturing method | |
| CN206953567U (en) | Fused glass pellet heats shower nozzle | |
| CN104762585A (en) | Forming device and method for guiding molten metal coating by using metal wire | |
| TWI660920B (en) | Non-contact forming device and method | |
| TWI747162B (en) | Semiconductor manufacturing device and manufacturing method of semiconductor device | |
| KR101597521B1 (en) | Manufacturing device and method for micro-lens array in glass optical elements | |
| CN112838057B (en) | Scribing method suitable for IGBT semiconductor device | |
| TW202338165A (en) | Semiconductor semi-finished product structure manufacturing equipment, method and structure using silicon dioxide composition and light-curing three-dimensional printing technology to form a semiconductor semi-finished product structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20161019 |