CN106030805A - Yield optimization of processor with graphene-based transistors - Google Patents

Abstract

Techniques described herein generally include methods and systems related to the selection of a combination of graphene an non-graphene transistors in an IC design. In order to reduce the increase in leakage energy caused by graphene transistors, selected non-graphene transistors may be replaced with graphene transistors in the IC design while other non-graphene transistors may be retained in the IC design. In order to limit the number of graphene transistors in the IC design, graphene transistors may replace non-graphene transistors primarily at locations in the IC design where significant delay benefit can be realized.

Description

With transistor based on Graphene, processor is carried out yield optimization

Background

Unless otherwise indicated, the method described in these chapters and sections is not the application claim Prior art and be included in these chapters and sections do not recognize be prior art.

Graphene is the allotrope of carbon, and its structure is single planar sheet sp²The carbon of-combination is former Son, it is closely filled in honeycomb crystal lattice, such as, in regular hexagonal pattern.Graphene is Semimetal zero gap semiconductor and at room temperature there is significantly high electron mobility.Thus, It is interested in be used for Graphene the various application relevant with integrated circuit.Such as, Graphene crystal Pipe be the raceway groove of wherein transistor be use Graphene formed silicon transistor.It is said that in general, In grapheme transistor, the every other component of transistor can be with typical complementary metal oxide The assembly of thing quasiconductor (CMOS) transistor is substantially similar.Therefore, Graphene and CMOS Integrated in single processor of transistor can be relatively easy and cheap.Due to Graphene The numerous characteristics of transistor, including low-down delay and switch energy, therefore at integrated circuit The middle desired possibility of use Graphene.But, Graphene includes some shortcomings the most really.

General introduction

At least some embodiment according to the disclosure, selects heterogeneous in integrated circuit (IC) designs The method of transistor combination includes identifying the multiple ranks relevant to IC design, the most each rank (level) including one or more composition element, described composition element includes by non-graphite alkene quasiconductor Material formed transistor and be configured to from be included in IC design rank immediately before at least One composition element, at least one sequential element, or combination reception signal.The method Including selecting to design one of relevant multiple ranks with IC, with including the crystal that formed by Graphene The composition element of pipe replaces the composition element in one of multiple ranks of selection, to form the first structure Make, determine the energy leakage speed relevant to the first structure, determine and construct relevant prolonging to first Time, compare determined by time delay and IC design target time delay and determined by energy leakage speed With IC design target energy leak rate, and response determined by energy leakage speed be less than Time delay determined by the while of target energy leak rate meets target time delay, selects and IC designs phase The multiple ranks closed another and with including the composition element of transistor that formed by Graphene Replace the described composition element in another in multiple rank, to form the second structure.

At least some embodiment according to the disclosure, selects heterocrystal pipe in IC designs The method of best of breed includes identifying the multiple ranks relevant to IC design, the most each rank bag Including one or more composition element, described composition element includes by non-graphite alkene semi-conducting material shape The transistor that becomes and being configured to from least one group of rank immediately before being included in IC design Close element, at least one sequential element, or combination receives signal.The method is further Including selecting to design one of relevant multiple ranks with IC, with including the crystal that formed by Graphene Composition element in one of multiple ranks selected by composition element replacement of pipe, to form first Structure, determines the energy leakage speed relevant to the first structure, determines relevant to the first structure Time delay, compare determined by time delay and IC design target time delay and determined by energy leakage fast The target energy leak rate of rate and IC design, and in response to determined by time delay more than target Energy leakage speed determined by time delay simultaneously meets target energy leak rate, selects to set with IC Multiple ranks that meter is relevant another and with including the combination of transistor that formed by Graphene The described composition element in another in multiple ranks replaced by element, to form the second structure.

At least some embodiment according to the disclosure, manufacture includes having computer-can perform Non-transient computer-the computer-readable recording medium of instruction, the execution of described instruction answer processor so that place The method that reason device is implemented in selecting the combination of heterocrystal pipe in integrated circuit (IC) design.The method bag Including and identify the multiple ranks relevant to IC design, the most each rank includes one or more combination Element, selects to design one of relevant multiple ranks with IC, with including the crystalline substance that formed by Graphene The composition element of body pipe replace selected by one of multiple ranks in composition element, to form the One structure, determine have the first structure IC design performance parameter, compare determined by performance The target capabilities parameter that parameter designs with IC, and as result of the comparison indicate that target capabilities is joined Number allows the further change of the performance parameter to IC design, selects relevant to IC design Multiple ranks another and with including that the composition element of transistor formed by Graphene is replaced Described composition element in another in multiple ranks, to form the second structure.

Foregoing teachings is only schematically and to be never intended to be restrictive.Show except above-mentioned Meaning property aspect, embodiment and feature, further aspect, embodiment and feature will be passed through Become apparent with reference to accompanying drawing and following detailed description book.

Accompanying drawing explanation

In conjunction with accompanying drawing, the foregoing and other feature of the disclosure will be from following description and appended right Requirement becomes more fully apparent.These accompanying drawings depict several embodiment party only according to the disclosure Formula and so, be not construed as limiting its scope.By using accompanying drawing with other feature with thin Joint describes the disclosure.

Fig. 1 shows the example integrated circuit (IC) of some embodiments that can implement the disclosure The block chart of design；

Fig. 2 A illustrates in IC designs, and selects heterogeneous (such as, Graphene and non-graphite alkene) The flow chart of the illustrative methods of transistor combination；

Fig. 2 B illustrates in IC designs, and selects heterogeneous (such as, Graphene and non-graphite alkene) The flow chart of the illustrative methods of transistor combination；

Fig. 2 C illustrates in IC designs, and selects heterogeneous (such as, Graphene and non-graphite alkene) The flow chart of the illustrative methods of transistor combination；

Fig. 3 is the block chart of the exemplary embodiment of computer program, described computer Program product is implemented to select Graphene and the method for non-graphite alkene transistor combination in IC；With

Fig. 4 is the block chart that illustrated example calculates equipment, and described calculating equipment is for setting at IC Selecting Graphene and the combination of non-graphite alkene transistor in meter, all of content is all according to the disclosure Some embodiments arrange.

Describe in detail

In following detailed description book, with reference to the accompanying drawing forming a description part.In the accompanying drawings, Similar symbol generally represents similar assembly, unless context is pointed out on the contrary.Describing in detail Exemplary embodiment described in book, drawings and claims is not meant to be restrictive. In the case of the spirit and scope without departing substantially from this paper theme, it is possible to use other embodiments, And can be made other change.The aspect of the disclosure, states as described by generally herein go up, and In accompanying drawing, explaination, can arrange with various different structures, replace, combines and design, its institute By being taken explicitly into account and forming a part of this disclosure.

The raceway groove of grapheme transistor wherein transistor be use Graphene formed from It is substantially reduced delay and switch (switching) energy point of view all can be significantly better than traditional CMOS Technology.But, grapheme transistor use in large scale integrated circuit is the most infeasible, former Cause is the high-leakage energy relevant to such transistor, its evaluated ratio outfit silicon raceway groove etc. Allomeric pipe the most thousands of times to millions of times.Therefore, although relevant to grapheme transistor relatively Low switch energy, but the release model of such transistor makes to include grapheme transistor Integrated circuit (IC) overall energy consumption can usually above use silicon transistor equivalent IC. Additionally, the performance of grapheme transistor may be generally to the work generally occurred in a manufacturing process Skill change is more sensitive.This factor can make to predict the performance of grapheme transistor before manufacture more Difficulty.

Embodiment of the present disclosure be included in IC design in select optimal or useful Graphene and The method of the combination of non-graphite alkene transistor.For the high leakage making grapheme transistor cause Energy minimization or reduction, in IC designs, can selectively make non-graphite alkene transistor use Grapheme transistor is replaced.In order to limit the quantity of grapheme transistor, Graphene in IC design Transistor can may realize the notable position postponing benefit in IC designs and replace non-graphite alkene crystal Pipe.

The method can use maximum by restriction, the selection algorithm of least commitment, with at given IC Design select on strategy which kind of transistor can have to produce based on Graphene Good or its improve IC design of design: for the minimum possible of the energy budget specified or fall Low delay, or the minimum or release model of reduction of the delay budget for specifying.Therefore, According to embodiment of the present disclosure, concrete IC design can be configured to the strategy selected in IC Position arranges several grapheme transistor, and this is hereinafter referred to as specific " structure " of IC design. Then, use the yield of the state-variable example prediction of relatively small amount to can be used as quantifiable tolerance, To determine this structure (such as, this concrete selection to transistor based on Graphene) that IC designs Whether it is optimal or whether the improvement relevant to other possible structures is provided.When using, sense is emerging The structure of interest is when carrying out large-scale production, and the predicted yield of this structure can be normally defined IC's Percent, this yield is predicted to meet the energy budget or delay budget specified.That predicts is good Rate can be provided herein power based on transistor-aspect rank and delay model.

The yield of the structure forecast of IC design can be according to one or more measure definitions, including energy Cost (such as, release model and the switch energy estimated) and the delay cost estimated and/or other Tolerance (one or more) or a combination thereof.Release model and the switch energy in lesser degree are permissible It is included as performance metric in the IC design used in a mobile device, because setting for this For Bei, power consumption saves the target being probably design.Postponing, such as, the structure of IC design is implemented Concrete operations or the time of one group of operation, it may be possible to be probably the in data center or its medium-rate One performance objective and energy use and are probably in other application of the second consideration what the IC used designed Tolerance.It addition, it is important for postponing possibly for the application of some mobile devices, because, such as Processing the delay in video and being probably unexpected and for application terminal user is to destroy Property.As discussed more below, to the relevant cost of energy of specific configuration of IC design and prolonging Late cost can be based on using IC and the many of change of the manufacturing process for this structure forecast Different situations and the discreet value that changes.

Fig. 1 shows the block chart of exemplary IC layout 100, and it can implement some disclosure Embodiment.IC design 100 can be as any suitable electronic equipment or small portable The design of the IC that the part of (or mobile) electronic equipment is implemented, such as mobile phone, individual number Word assistant (PDA), personal media player equipment, wireless network monitoring (web-watch) set Headset equipment standby, individual, application specific equipment, include the equipment complex of any of above function, Or personal computer, including portable computer and non-portable computer, or other electronics set Standby.

IC design 100 can include a 101-105, trigger 121-125, source node 131 and converge Poly-node 132.Door 101-105 and trigger 121-125 can couple, at source node 131 such as display And between aggregation node 132, form various path.It should be noted that for clarity and brevity, Fig. 1 eliminates trigger 121-125, and general other assemblies of typical IC design time Clock inputs, arranges and reset input.It is further noted that IC design 100 can include that ratio is in Fig. 1 The greater number of door 101-105 and trigger 121-125 of explaination.Such as, some embodiment party In formula, IC design 100 can be adapted for ultra-large integrated (ULSI) with millions of transistor The design of logic chip, such as processor or processor core.In some embodiments, may be used There is assembly less compared with those described in Fig. 1 and/or other kinds of assembly.

Door 101-105 can be composition element, such as transistor, and in order to determine that IC designs The purpose of the difference " rank " of 100, each door can be considered the circuit of IC design 100 expression " node ", as described by below in conjunction with Fig. 2 A, Fig. 2 B and Fig. 2 C.Trigger 121-125 Can be sequential element, such as depositor and trigger.In some embodiments, when determining When IC designs the rank of 100 circuit represented, such as, include when some structures of IC design 100 One or more being suitable for is replaced by Graphene, with optimization or to improve the performance of IC design 100 During trigger 121-125, trigger 121-125 also can be considered node.Source node 131 can couple To the input 109 of the circuit of IC design 100 expression, and aggregation node 132 can couple described The output 110 of circuit.It is said that in general, in some embodiments, source node 131 and convergence joint The abstract structure for algorithm described herein that point 132 can be introduced into, and may not indicate that Physical node in IC design 100.

Fig. 2 A illustrates the flow chart of the illustrative methods 200 according to embodiment of the present disclosure, To select the combination of heterogeneous (such as, Graphene and non-graphite alkene) transistor at IC in designing.Example As, method 200 can be used for selecting in IC designs optimal or suitably carries out Graphene and non- Combination/the element of grapheme transistor, in order to improve the performance of IC design.Method 200 can include One or more operations, function or action, as by block 201,202,203,204,205,206, One or more explainations of 207 and/or 208.Although explaining block in order, these blocks also can be put down Row is carried out, and/or carries out with the order different from those described herein.And, based on expectation Enforcement, each block is combined into less block, is divided into other block, and/or deletes.Can carry For representing other operations, function or the other block of action.Although the IC in conjunction with Fig. 1 designs 100 Describing method 200, the performance of the method 200 relevant to any suitable IC design is in these public affairs In the range of opening.

Method 200 can begin at block 201 " determining Ai Pu Shillong (ε)-critical path that IC designs ". Block 201 can be followed by block 202 " determining the minimal level of ε-critical path ", and block 202 can be subsequently Being block 203 " determining the most useful rank implementing grapheme transistor ", block 203 can be followed by Block 204 " implementing grapheme transistor with the neotectonics of IC design ", block 204 can be followed by block 205 " calculating the effect implementing grapheme transistor ", block 205 can be followed by block 206 " assessment The yield of neotectonics ", block 206 can be followed by block 207 " determining whether to realize optimal yield ", Block 208 " end " or block 203 can be followed by with block 207.

In some embodiments, before block 201, IC design 100 can be developed to provide spy Fixed function.Therefore, the combination of definable IC design and the concrete physical features of sequential element, Such as, door 101-105 and trigger 121-125.These physical features can include material behavior, Such as capacitive oxide and/or other characteristics, and relevant geometric attribute, such as nominal door length and Gate-width degree and/or other geometric attributes.It addition, the operating parameter of definable IC design 100, than Such as clock frequency rate, supply voltage etc..

In block 201, it may be determined that the ε-critical delays network of IC design 100, it includes IC ε-the critical path of design 100.The ε of circuit-critical delays network can include the door in circuit, Described Men Cong source node is at least one path of aggregation node, and the delay in described path exists Within the predetermined value (ε) of the critical path delay of circuit, wherein ε is can be based on various standards The predetermined value selected.So, being abstracted of importance of each in circuit, such as, quantify, If thus door is in ε-critical delays network, delay can be affected potentially.100 are not designed at IC ε-critical delays network in door can be typically without in the block subsequently of method 200 consider, from And greatly reduced the calculating of block subsequently.

In block 202, it may be determined that " minimum cut " or " rank " of IC design 100, its In each minimum cut and IC construct in all ε-critical paths intersect.For this purpose, IC Design 100 may be configured as weighted digraph, and the most each 101-105 can be node, and If can there is, from node i to node j, the direct output that edge door j is an i.Weighted digraph Minimum cut can be that figure is divided into two parts, the part comprising source node 131 and comprising A part for aggregation node 132 so that from the combination at all edges of source part to assemblying part Weight is minimized or reduces.In other words, removing all doors from specific cutting causes source to be saved Point 131 and aggregation node 132 separate, and such as, do not have remaining path between them.

Find that the minimum cut representing the weighted digraph of IC design 100 can be that uncertainty is many Item formula (NP) complete problem (nondeterministic polynomial complete problem), and Can be approximated by the concept using rank.The circuit other sum of middle rank can be to remittance from source node Poly-node comprises the quantity of door in the path of maximum quantity door.The minimal level of a door in circuit Can be the minimum number of door between this and source node, and this maximum level can be The minimum number of door between this and aggregation node.Therefore, if a door is N's from rank Door receives input, then the rank of this reception door can be at least level n+1.

In FIG, find to represent the minimum cut of the weighted digraph of exemplary IC layout 100 Can relate to/including: door 101 and 102 is in rank 1, because each only slave flipflop receives Input；Door 103 and 104 in rank 2 because door 103 slave flipflop (trigger 124) or Rank be 1 door (door 102) receive input, and door 104 slave flipflop (trigger 121) or level It it is not door (door 102) the reception input of 1；With door 105 in rank 3, because door 105 is from level Be not 1 door (door 101) or rank be 2 (respectively from door 103 and 104) receive input.Therefore, By forming the structure of IC design 100, the wherein other crystal of any one-level of IC design 100 Pipe all replaced by grapheme transistor, IC design 100 time delay and switch energy with wherein own Transistor is that the structure of the IC design 100 of non-grapheme transistor is compared, and can be improved. Additionally, the rank replaced by grapheme transistor by selection, increase in IC design 100 lets out Leakage energy can be minimized or reduce, and described rank is " narrow " rank, such as, has The rank of few door.In FIG, the rank 3 with single door 105 is the example of such rank.

In IC designs 100 more complicated embodiments, such as it is configured to when IC design 100 When there is the ULSI circuit of millions of transistor, identify rank may more complicated, but be non-really Qualitative multinomial (NP) complete problem.So that this problem can solve with the substantial linear time, Effectively cutting can be limited to those doors including having overlapping rank.It addition, at some embodiments In, the weight of node can be used for capturing each node in one or more specific performance parameters (such as, Circuit delay, release model and switch energy) relatedness of aspect.Specifically, the power of node Weight can be directly proportional or directly related to the negative leakage contribution of node, and with the front of node Switch impact be inversely proportional to or be reversely correlated with, the most relatively low weight node be possible Graphene crystalline substance The both candidate nodes that body pipe is replaced.Therefore, being selected for the rank that Graphene door is replaced is tool There is the rank of the weight of minimum or reduction, as mentioned above.This rank can be chosen in block 203.

In block 203, it may be determined that implement grapheme transistor more useful rank.At block 203 In, it may be determined that each rank determined in block 202 when replacing by grapheme transistor to property The effect of energy.Because performance parameter interested in the most each door, such as, circuit prolongs Late, release model and switch energy can substantially be affected by technique change, when selecting to be used for implementing During the most useful rank of grapheme transistor, such technique change typically can in block 203 quilt Consider.

Technique change can directly affect effective channel length (L) and threshold voltage (V_th).At some In embodiment, Cline etc. Quadtree (" the Analysis and modeling of proposed CD variation for statistical static timing, " IEEE/ACM ICCAD, 60-66 page, 2006) can be used for reflecting that the spatial coherence between door close in IC design 100 and IC-arrive The change of-IC.L is scattered in multiple rank and distributes net on each level by Quadtree Lattice, the changing value of each of which allocated followed normal distribution distribution, it captures one of dependency Source.Then, the total value of L can be the door technique change sum in all ranks belonging to door, ΔL_ij.In this model described by equation 1, Δ L_ijIt is the i-th rank belonging to door and jth The change of individual grid, and μ_iAnd σ_iIt it is the parameter of normal distribution at rank i.For with change Measure unrelated door threshold voltage V_th, it may be assumed that Gauss distribution.

Wherein

The most useful rank quantitatively determining enforcement grapheme transistor in block 203 is to have not Determine the design optimization/improvement problem of constraint.In this case, uncertain constraint can be from different works The larger numbers of combination of skill change is correlated with, and these combinations are perhaps to detected specific rank In each generation.For the infinite space of the variable bound that simulation process change causes, permissible Use the sampling that these retrain.Specifically, for detected specific door, interested Performance parameter (such as, circuit delay, release model and switch energy) can be at unlimited or the biggest number May changing in combination of amount, but this door can be assigned to one " storehouse (bin) ", Qi Zhongfen It is fitted on the performance parameter numerical value that door therein has in preset range.Such as an embodiment In, delay, release model and switch energy are respectively classified into five relative to specific door structure Discrete bin value, the sum in the possible storehouse of any in this structure can be 125.Therefore, exist Being suitable for designing each door of considering in 100 ranks with the IC that grapheme transistor is replaced, can exist can The limited distribution of energy form.Each such storehouse of performance parameter is referred to herein as " technique change Example (process variation instance) ".The possibility of each technique change example of particular door Property power and delay model can be used to calculate.In some embodiments, equation 2-5 represents Power and delay model can be used for block 203.

$D=\frac{k_{tp}\·C_L\·V_{dd}}{2\·n\·\mathrm{\μ}\·C_{ox}\·\frac{W}{L}\·{\left(\frac{kT}{q}\right)}^2}\·\frac{k_{fit}}{{\[\ln \left(e^{\frac{(1+\mathrm{\σ})V_{dd}-V_{th}}{2\·n\·(kT/q)}}\right)+1\]}^2}---\left(2\right)$

C_L=C_ox·L·(γ·W+W_fanout) (3)

$P_{leakage}=2\·\mathrm{\μ}\·C_{ox}\·\frac{W}{L}\·{\left(\frac{kT}{q}\right)}^2\·V_{dd}\·e^{\frac{\mathrm{\σ}\·V_{dd}-V_{th}}{n\·(kT/q)}}---\left(4\right)$

$P_{switching}=\mathrm{\α}\·C_L\·V_{dd}^2\·f---\left(5\right)$

Wherein V_dd=supply voltage, n=sub-threshold slope, μ=mobility, C_ox=capacitive oxide, W=gate-width degree, L=door length, thermal voltageσ=DIBL factor, V_th=threshold Threshold voltage, k_tp=delay parameter, and k_f=model fitting parameter.Load capacity C_LAt equation 2 Defined in, wherein γ is logic effect and the W of door_fanoutIt it is the width sum of load door.

In determining the IC design 100 replaced by grapheme transistor, the most useful rank (or is improved Rank) with time, for this rank is not the most Graphene and IC design ε-key network In each door, the object function of each rank considered in block 203, can based on leakage because of Long-pending and the Optimalswitching devices of son and this energy leakage and the ratio amassed of this switch energy. By making the minimization of object function or reduction, it may be determined that the IC design replaced by grapheme transistor Rank (or the rank improved) the most useful in 200.Note, suitably in the case of, according to difference Target, object function can be minimized/reduce.Such as, in some embodiments, target Function can be used for making the latency minimized or reduction of the ceiling capacity budget for specifying, thus logical Cross method 200 and can finally select still to meet IC design 100 construct the soonest of this energy budget. Alternatively, object function can be used for making the energy-delay product for the maximum delay constraint specified Minimize or reduce, thus finally can select still to meet described maximum delay about by method 200 The structure of IC design 100 Energy Efficient of bundle.

In block 204, can be designed by the selected IC replaced with Graphene in block 203 All transistors in the rank of 100 implement grapheme transistor in IC design 100.

In block 205, can calculate and implement Graphene crystal in the selection rank of IC design 100 The effect of pipe.Specifically, the IC implemented in block 204 can be calculated and design prolonging of 100 structures Late, release model and switch energy and/or other parameters.Power and delay model, such as equation Power that formula 2-5 represents and delay model, can be used for quantifying these values.Use grapheme transistor Implement the impact of door in IC design 100, expression grapheme transistor behavior can be used relative to non- The scale factor of the behavior of grapheme transistor is simulated.Such as, for postponing, allusion quotation can be used The scale factor of the 0.05 of type；For leakage power, the typical scale factor of 1000 can be used； And for switch power, the scale factor of typical 0.2 can be used.In other words, stone is used Ink alkene implements door can reduce the delay relevant to door about 20X, increases the leakage power relevant to door About 1000X, and can reduce the switch power relevant to door about 5X.

It is said that in general, all technique change example calculation of the structure of the IC design 100 considered Delay, release model and switch energy and/or other parameters can be calculated.Therefore, at block 205 In, the single value for delay, release model and switch energy etc. can not be produced.But, base In the manufacturing process variations of the IC prediction manufactured with structure, can be by the IC design 100 considered Structure produce these parameters distribution.Thus, some in the distribution determined in block 205, All of or do not have technique change example may meet specific performance parameter, such as time delay or let out Leakage energy.

In block 206, the yield of the structure of the IC design 100 implemented in block 204 can be calculated, Wherein yield can include when manufacturing structure interested, and that estimates meets particular characteristic target The percent of IC chip.Such estimating can be statistically right with it based on manufacturing process variations Impact by the performance of many IC of the structure manufacture of the IC design 100 implemented in block 204. Thus, in block 206, for all technique change examples of structure interested, can calculate Estimated performance (such as, delay, release model, switch energy and/or the energy of the IC chip manufactured Amount-postpone product or other) and compare with the speed specified and/or energy object.

In block 207, it may be determined whether have found IC design 100 that is optimal or that improve Enforcement, such as, it is intended that speed and/or release model target passed through in block 204 implement Structure possible technique change example satisfactory percent (yield) realize.If it is determined that block The structure of the IC design 100 implemented in 204 is optimal or best available enforcement, method 200 Proceed to block 208 and terminate.If it is determined that the structure implemented in block 205 is not optimal or Good available enforcement, method 200 continues back at block 203, and repeatable block 203-207.

In some embodiments, the enforcement of the optimal/improvement of IC design 100 may be included in block 206 The yield of middle prediction designs the structure of 100 more than the yield of minimum expectation or the IC of other threshold values. In other embodiments, the enforcement of the optimal/improvement of IC design 100 can include meeting or exceeding Particular characteristic target substantially uses the IC design 100 of all specified performance parameter budgets simultaneously Structure.Such as, given IC designs 100 energy budgets specified and based on the performance objective postponed (such as, it is thus achieved that possible maximum rate and less than energy budget), optimal/enforcement of improving can To be to use essentially all prescribed energy budget, there is the most maximum allowable delay, and And there is the structure of the IC design 100 of satisfied yield.Because structure uses essentially all finger Fixed energy budget, the other rank of this IC design 100 perhaps can not be replaced by grapheme transistor Change and be less than energy budget.Therefore, such structure can be IC design 100 under particular case Optimal or preferably available enforcement.

Therefore, on the premise of the given IC design and performance target specified, can determine that IC sets Whether some of meter should be can be maybe the enforcement using grapheme transistor.Become according to technique Change model, power module, and delay model and/or other models (one or more), can use The technique change example of limited quantity, is beneficial to the solution of problem when IC design includes a large amount of door. Additionally, the yield of prediction, such as, the percent of the technique change example of IC design prediction, Postpone and can be maximized or increase under power constraint.In some embodiments, technique change The quantity of example may be assumed that into the biggest quantity, millions of ranks, it is sufficiently large sample sets To cover whole technique change (PV) model.

Fig. 2 B illustrates the flow chart of illustrative methods 220 according to embodiment of the present disclosure, with The combination of heterocrystal pipe is selected in integrated circuit (IC) designs.Such as, method 220 can be used for Select optimal in IC designs or suitably Graphene and the combination/unit of non-graphite alkene transistor Part, in order to improve the performance of IC design.Method 220 can include as block 221,222,223, 224, one or more operations, function or the action of one or more explainations of 225 and/or 226. Although illustrating block in order, but these blocks also can parallel be carried out, and/or with described herein Those different orders carry out.And, each block is combined into less based on desired enforcement Block, be divided into other block, and/or delete.Other operations of expression, function or action can be provided Other block.Although designing 100 in conjunction with the IC of Fig. 1 to describe method 220, but with appoint The performance of the method 220 that what suitable IC design is relevant is in the scope of the present disclosure.

Method 220 can begin at block 221 " identifying the multiple ranks relevant to IC design ".Block 221 can be followed by block 222 " selecting one of multiple ranks relevant to IC design ", block 222 Block 223 can be followed by " replace with the composition element including the transistor formed by Graphene and select level Composition element in not, to form the first structure ", block 223 can be followed by block 224 and " determine The energy leakage speed relevant to the first structure ", block 224 can be followed by block 225 and " compare and determine The target energy leak rate of energy leakage speed and IC design ", and block 225 can be subsequently It is that " another of multiple ranks that selection is relevant to IC design is for by Graphene shape for block 226 The transistor become is replaced ".

In block 221, identifying the multiple ranks relevant to IC design, the most each rank includes One or more composition elements, described composition element includes being formed by non-graphite alkene semi-conducting material Transistor.Each rank is configured to from even lower level at least one group other being included in IC design Close element, at least one sequential element, or combination receives signal.

In block 222, select one of multiple ranks relevant to IC design.Some embodiment party In formula, the rank of selection is " narrow " rank with the less door of other ranks in designing than IC.

In blocks 223, the composition element in the rank selected in block 222 is with including by Graphene The composition element of the transistor formed is replaced, to form the first structure.

In block 224, energy leakage speed is determined and the first structure related rate.Such as, In some embodiments, the energy of each composition element replaced with Graphene in the first structure Leak rate can be updated, thus can determine that the gross energy leak rate of whole first structure.

In block 225, compare the target energy leakage of energy leakage speed and the IC design determined Speed.

In block 226, the energy leakage speed determined in response block 225 is let out less than target energy Leakage speed, selection designs another of relevant multiple ranks to IC, for including by graphite The transistor combination element that alkene is formed is replaced, to form the second structure.

Fig. 2 C illustrates the flow chart of illustrative methods 230 according to embodiment of the present disclosure, with The combination of heterocrystal pipe is selected in integrated circuit (IC) designs.Such as, method 230 can be used for Optimal or suitably Graphene and the property of non-graphite alkene transistor/element is selected in IC designs Can combine, in order to improve the performance of IC design.Method 230 can include as block 231,232,233, 234, one or more operations, function or the action of one or more explainations of 235 and/or 236. Although illustrating block in order, but these blocks also can parallel be carried out, and/or with described herein Those different different order carry out.And, each block is combined into based on desired enforcement Less block, is divided into other block, and/or deletes.Can provide expression other operation, function or The other block of action.Although 100 describing method 230 in conjunction with IC design in Fig. 1, and appoint The execution of the method 230 that what suitable IC design is relevant is also in the scope of the present disclosure.

Method 230 can begin at block 231 " identifying the multiple ranks relevant to IC design ".Block 231 can be followed by block 232 " selecting one of multiple ranks relevant to IC design ", block 232 Block 233 can be followed by " replace with the composition element including the transistor formed by Graphene and select level Composition element in not, to form the first structure ", block 233 can be followed by block 234 and " determine To the first relevant time delay of structure ", block 234 can be followed by block 235 " compare the time delay determined and The target time delay of IC design ", block 236 can be followed by with block 235 and " select relevant to IC design Another of multiple ranks for replacing with the transistor that formed by Graphene ".

In method 220, block 231-233 can be similar with block 221-223 the most respectively.

In block 234, determine and the first relevant time delay of structure, wherein this time delay can to correspondence time The persistent period in clock cycle.In some embodiments, by the level selected in computing block 232 In not, the time delay of the composition element that each Graphene is replaced determines the time delay in block 234, with shape Become the first structure.

In block 235, compare the target time delay of time delay and the IC design determined.

In block 236, the time delay determined in response block 235 is less than target time delay, selects and IC Another of multiple ranks that design is relevant, for the transistor including being formed by Graphene Composition element is replaced, to form the second structure.

Fig. 3 is the block chart of the exemplary embodiment of computer program 300, with at IC Design is implemented to select the combined method of heterocrystal pipe.Computer program 300 can include Signal bearing medium 304.Signal bearing medium 304 can include one or more groups executable instruction 302, it is when being performed by the processor such as being calculated equipment, it is possible to provide at least the above with above The function that figure is relevant.

In some implementations, signal bearing medium 304 can include computer-readable Jie of non-momentary Matter 308, be such as but not limited to hard drive, disk (CD), digital disk (DVD), number tape, Bin etc..In some implementations, signal bearing medium 304 can include recordable media 310, It is such as but not limited to bin, read/write (R/W) CD, R/W DVD etc..In some implementations, Signal bearing medium 304 can include communication media 306, is such as but not limited to numeral and/or is similar to Communication media (such as, fiber optic cables, waveguide, wired communication link, radio communication chain circuit etc.). Computer program 300 is recordable in the computer-readable medium of non-momentary 308 or another kind of As on recordable media 310.

Fig. 4 is that at least some embodiment illustrated example according to the disclosure calculates equipment 400 Block chart, described calculating equipment 400 is set to select Graphene and non-graphite in IC designs The combination of alkene transistor.In some embodiments, some component/part of equipment 400 are calculated The combination of Graphene described above and non-graphite alkene element themselves may be used to implement.Non- Often in the structure 402 on basis, calculating equipment 400 generally includes one or more processor 404 With system memory 406.Bin bus 408 can be used for processor 404 and system memory Communication between 406.

Depend on that desired structure, processor 404 can be any kind of, including but do not limit In microprocessor (μ P), microcontroller (μ C), digital signal processor (DSP), or its any group Close.Processor 404 can include the buffering of some ranks, and such as level cache 410 and two grades delay Deposit 412, processor core 414, and depositor 416.The Processor Core heart 414 can wrap Include arithmetic logic unit (ALU), floating point unit (FPU), digital signal processing core (DSP Core), Or its any combination.Processor 404 can include Programmable Logic Device, is such as but not limited to field Programmable gate array (FPGAs), special IC (ASIC), complex programmable logic can be repaired Equipment (CPLD) etc..Example memory device controller 418 also can be used together with processor 404, Or in some implementations, bin controller 418 can be the internal part of processor 404.

Depend on that desired structure, system memory 406 can be any kind of, including but It is not limited to impermanency bin (such as RAM), permanent storage (such as ROM, flash memory Deng) or its any combination.System memory 406 can include operating system 420, one or more Application 422 and routine data 424.Application 422 can include one or more application being divided into block, As described above in conjunction with one or more figures (one or more).Routine data 424 can include can For calculating the data of equipment 400 operation.In some embodiments, application 422 can be arranged For operating in operating system 420 together with routine data 424.This base configuration 402 described Explained in the diagram by those assemblies in inner dotted line.

Calculating equipment 400 can have other feature or function, and additionally interface, is beneficial to base Communication between plinth structure 402 and the equipment of any necessity and interface.Such as, bus/interface control Device 490 processed can be used for beneficially base configuration 402 and one or more Data Holding Equipment 492 it Between through the communication of storage interface bus 494.Data Holding Equipment 492 can be removable storage Deposit equipment 496, non-removable storage facilities 498, or a combination thereof.Removable storage facilities Including disk unit with the example of non-removable storage facilities, such as disk drive and hard disk are driven Dynamic (HDD), disc drives such as Zip disk (CD) drive or digital universal disc (DVD) drives, Solid-state drives (SSD), and band driving etc..Illustrative computer storage medium may be included in any The impermanency implemented in method or technology and permanent, removable and non-removable medium, For storing information, the most computer-readable instruction, data structure, program module or other Data.

System memory 406, removable storage facilities 496 and non-removable storage facilities 498 is the example of computer storage media.Computer storage media include but not limited to RAM, ROM, EEPROM, flash memory or other bin technology, CD-ROM, digital universal disc (DVD) Or other light storages, magnetic holder, tape, disc storage or other magnetic storage devices, or available In storing desired information and any other medium that can be accessed by calculating equipment 400.Any Such computer storage media can be a part for calculating equipment 400.

Calculating equipment 400 may also comprise beneficially from various interface equipments (such as, outut device 442, Periphery interface 444 and communication apparatus 446) to base configuration 402 through bus/interface controller 430 The interface bus 440 of communication.Exemplary output device 442 includes showing methods unit 448 harmony Machining cell 450, it can be configured to set with various outsides through one or more A/V ports 452 Standby communication, such as display or microphone.Exemplary periphery interface 444 includes serial interface control Device 454 or parallel interface controller 456, it can be configured to and external equipment such as input equipment (example As, keyboard/mouse, pen, audio input device, Bluetooth input equipment etc.) or other peripheral devices (such as, printer, scanner etc.) is through the communication of one or more I/O port 458.Exemplary logical News equipment 446 includes network controller 460, and it may be configured as beneficially through one or more communication terminals Mouthfuls 464 do not calculate equipment 462 with one or more other on network communication link, such as but not It is limited to fiber optics, long term evolution (LTE), 3G, WiMax communication.

Network communication link can be the example of communication media.Communication media can be typically embodied as Computer-readable instruction, data structure, program module, or modulation data signal in its His data, such as carrier wave or other conveyer mechanisms, and any information delivery media can be included. " data signal of modulation " can be to have its feature set one or more or in coding signal The signal changed by this way during information.As an example, but it is not limited to this, communication media Can include wire medium such as cable network or direct wired connection, and wireless medium such as sound, Radio frequency (RF), microwave, infrared (IR) and other wireless mediums.Term computer as used herein Readable medium can include storage medium and communication media.

Calculating equipment 400 can be embodied as a following part: small form factor is portable (or to be moved Dynamic) electronic equipment such as mobile phone, personal digital assistant (PDA), personal media player set Standby, wireless network monitors, individual headset equipment, application specific equipment, or includes on any State the equipment complex of function.Calculating equipment 400 also is embodied as personal computer, including portable Formula computer and non-portable computer structure.Embodiment of the present disclosure is included in IC design The method selecting the combination of Graphene and non-graphite alkene transistor.Therefore, concrete IC design can Improve with strategy placing graphite alkene transistor, make the height relevant to grapheme transistor let out simultaneously The unexpected effect of leakage energy minimizes or reduces.

The hardware and software of the embodiment of system has a little difference between implementing；Hardware or software Use the design alternative being typically representative cost and efficiency tradeoff (but the most always, because at some Under background, the selection between hardware and software is probably important).A groove is told in existence can realize this Program described in literary composition and/or various media (such as, hardware, the software of system and/or other technologies And/or firmware), and preferably medium is along with the program disposed and/or system and/or other technologies Ridge and change.Such as, if implementer thinks that speed and accuracy are primary, then Implementer may select main hardware and/or firmware vehicle；If elasticity is primary, implement This may select main software and implement；Or, the most alternatively, implementer can select hardware, Some combinations of software and/or firmware.

Aforementioned detail specifications is by using block chart, flow chart and/or embodiment to illustrate Equipment and/or the various embodiments of program.Comprising this of one or more function and/or operation Under the degree of the block chart of sample, flow chart and/or embodiment, those skilled in the art recognize, Each function and/or operation in such block chart, flow chart or embodiment can be by wide scopes Hardware, software, firmware or actually its combination in any is individually and/or common implementing.In one In embodiment, several parts of theme as herein described can be through application specific integrated circuit (ASICs), field programmable gate array (FPGA), digital signal processor (DSP) or other integration Form is implemented.But, some aspects of embodiments disclosed herein, in whole or in part, can It is equal to enforcement in integrated circuits, as one or more in run on one or more computers Computer program (such as, the one or more programs run in one or more computer systems), As the one or more programs run on the one or more processors (such as, as at one Or the one or more programs run on multi-microprocessor), as firmware, or as actually Its combination in any, and design circuit and/or for software and or firmware write code according to the disclosure In the range of those skilled in the art.It addition, those skilled in the art recognize described herein The mechanism of theme can be as program product with various distributions, and theme as herein described Exemplary embodiment is suitable for being situated between for the actual signaling bearer carrying out being distributed of any particular type Matter.The example of signal bearing medium includes but not limited to following: recordable-type media such as floppy disk, Hard drive, disk (CD), digital disk (DVD), number tape, computer storage etc.；With Such as, digital and/or similar communication media (such as, fiber optic cables, waveguide, has transmission type medium Line communication link, radio communication chain circuit etc.).

Those skilled in the art recognize and describe equipment and/or technique in the way of explaining herein, and Thereafter use through engineering approaches practice that such description equipment and/or technique are integrated to data handling system It is common in this area.That is, at least some of equipment as herein described and/or technique can ECDCs The experiment of reason quantity is integrated to data handling system.It would be recognized by those skilled in the art that typical Data handling system generally comprises one or more system unit cover, video display apparatus, storage Device, such as impermanency and permanent storage, processor, such as microprocessor and numeral letter Number processor, computational entity, such as operating system, driver, graphical user interface, and Application program, one or more interactive devices, such as touch pad or screen, and/or control system Including feedback loop with control motor (such as, by perceived position and/or the feedback of speed；For moving And/or adjust assembly and/or the control motor of quantity).Typical data handling system is available appoints What suitable commercially available assembly is implemented, such as generally at data calculating/communication and/or network Those occurred in calculating/communication system.

Theme described herein sometimes explain the different assemblies being included in other different assemblies or Connect other different components.Should be appreciated that what the structure so described was merely exemplary, And in fact other structures many can be implemented to realize identical function.On conceptual sense, real Any setting of the assembly of existing identical function is effectively " association " so that realize desired merit Energy.Therefore, any two component visual realizing specific function combined herein is for " closing each other Connection " so that realize desired function, no matter construct or intermediate module.Similarly, so close Any two component of connection can be also considered as each other " operatively-coupled " or " combining in operation ", To realize desired function, and any two assembly that can so combine can be also considered as each other " behaviour Couple on work ", to realize desired function.The object lesson coupled in operation includes but does not limits In physically coupling and/or physically interaction assembly and/or wireless interact and/or nothing Line interaction assembly and/or interact in logic and/or in logic can the assembly of dependent interaction.

The most substantially any plural number and/or the use of singular references, those skilled in the art can Plural form is converted into singulative and/or is converted into plural form from singulative, with suitably It is suitable for context and/or application.In order to clear, the most clearly illustrate various singular/plural and arrange.

It will be appreciated by those skilled in the art that it is said that in general, herein, and especially appended claim In term general explanation of using in (such as, appended claimed subject matter) be " open " (such as, term " includes (including) " and should be interpreted that " including but not limited to ", term term " having " and should be interpreted that " at least having ", term " includes (includes) " and should be interpreted that " bag Include but be not limited to " etc.).It is further understood that, if it is desired to specific amount of Quoting claim narration, such expectation will clearly describe in the claims, and not have When having such narration, there is not such expectation.Such as, as the help to understanding, under State appended claim to comprise use and quote phrase " at least one " and " one or more ", To quote claim narration.But, use such phrase to should be not construed as to imply that by not Definite article " one (a) " or " one (an) " quote claim narration and will comprise and so quote power Profit requires that any concrete right of narration requires to be limited to only to comprise the embodiment party of a kind of such narration Formula, even if when identical claim includes quoting phrase " one or more " or " at least Individual " and indefinite article such as " (a) " or " one (an) " (such as, " one (a) " and/ Or " one (an) " should be interpreted that the meaning is " at least one " or " one or more ") time； Definite article for using for quoting claim narration uses same explanation.It addition, i.e. Making clearly to describe specific amount of claim of quoting to describe, those skilled in the art recognize this The narration of sample should be interpreted that the meaning is that at least narration quantity (such as, does not has the nothing modification of modifier Narration " two narrations ", the meaning is at least two narration or two or more narrations).Additionally, Use with the conventional analogous terms of " at least one A, B and C etc. " in the case of, general and Say such structure be intended to those skilled in the art's routine understand the meaning (such as, " have at least one The system of individual A, B and C " include but not limited to that there is independent A, independent B, independent C, A Together with B, together with A with C, together with B with C, and/or the system that A, B are together with C etc.). Use with the conventional analogous terms of " at least one A, B and C etc. " in the case of, general and Say such structure be intended to those skilled in the art's routine understand the meaning (such as, " have at least one The system of individual A, B or C " include but not limited to that there is independent A, independent B, independent C, A Together with B, together with A with C, together with B with C, and/or the system that A, B are together with C etc.). It is further understood that, virtually appear in two or more optional terms it Between any disjunctive and/or phrase, no matter in description, claim or accompanying drawing, It is interpreted as consideration and includes one, the probability of one or two terms of term.Such as, phrase " A or B " is interpreted as including " A " or " B " or the probability of " A and B ".

Although have been disclosed for various aspects and embodiment herein, but other aspects and enforcement Mode will be apparent from for those skilled in the art.Various aspects disclosed herein and reality The mode of executing be the purpose in order to explain and be not intended to restrictive, real scope and spirit Indicated by the claims below.

Claims (22)

1. the method selecting the combination of heterocrystal pipe in integrated circuit (IC) designs, described side Method includes:

Identifying the multiple ranks relevant to described IC design, the most each rank includes one or many Individual composition element, described composition element includes the transistor formed by non-graphite alkene semi-conducting material And it is configured at least one composite unit from the rank immediately before being included in described IC design Part, at least one sequential element, or combination reception signal；

Select one of the plurality of rank relevant to described IC design；

With the composition element of transistor including being formed by Graphene replace selected by the plurality of Composition element in one of rank, to form the first structure；

Determine the energy leakage speed relevant to described first structure；

Determine the time delay relevant to described first structure；

The target time delay of time delay determined by Bi compare and described IC design and determined by energy leakage The target energy leak rate that speed designs with described IC；With

Energy leakage speed determined by response is the most described less than described target energy leak rate The time delay determined meets described target time delay, selects the plurality of level relevant to described IC design Other another and with including that the composition element of transistor formed by Graphene is replaced described many Described composition element in another in individual rank, to form the second structure.

2. the method described in claim 1, wherein determines that described energy leakage speed includes for institute The multiple technique change examples stating IC design determine energy leakage speed.

3. claim 2 method, the multiple techniques farther including to be based upon described IC design become Change described energy leakage speed and the target energy leak rate of described IC design that example determines, Determine the yield of described first structure.

4. claim 3 method, wherein determines that the yield of described first structure is based on described IC The length of effective channel of composition element and the technique change of threshold voltage in design.

5. claim 3 method, wherein determines that the yield of described first structure is based on door-rank At least one of delay model, door-rank leakage power model and door-grade switches power module.

6. the method described in claim 1, wherein replaces one of selected the plurality of rank In composition element include replacing selected with the composition element of transistor including being formed by Graphene Each composition element in one of the plurality of rank selected, to form described first structure.

7. the method described in claim 1, wherein selects to design with described IC relevant described many One of individual rank includes weighting at least one node in described IC design, with bearing of described node The leakage contribution in face is directly proportional and affects with the positive side switch of described node and is inversely proportional to.

8. the method described in claim 1, farther includes, identify the plurality of rank it Before, determining that described IC designs the Ai Pu Shillong-critical path from source node to aggregation node, it prolongs With Ai Pu Shillong (ε) more than or equal to the critical path delay of described IC design long-pending late.

9. the method described in claim 1, wherein selects to design with described IC relevant described many One of individual rank includes relative at least one reduction object function following: design phase with described IC The cost of energy that the time delay cost closed is relevant to described IC design, and design phase with described IC The delay-product closed.

10. the method selecting the combination of heterocrystal pipe in integrated circuit (IC) designs, institute The method of stating includes:

Identifying the multiple ranks relevant to IC design, the most each rank includes one or more groups Close element, described composition element include the transistor that formed by non-graphite alkene semi-conducting material and Be configured to from be included in described IC design rank immediately before at least one composition element, At least one sequential element, or combination reception signal；

Select one of the plurality of rank relevant to described IC design；

With the composition element of transistor including being formed by Graphene replace selected by the plurality of Composition element in one of rank, to form the first structure；

Determine the energy leakage speed relevant to described first structure；

Determine the time delay relevant to described first structure；

The target time delay of time delay determined by Bi compare and described IC design and determined by energy leakage The target energy leak rate that speed designs with described IC；With

Time delay determined by response is more than energy leakage speed determined by described target time delay simultaneously Meet described target energy leak rate, select the plurality of rank relevant to described IC design Another and with including that the composition element of transistor formed by Graphene is replaced the plurality of Described composition element in another in rank, to form the second structure.

Method described in 11. claim 10, wherein determines that described time delay includes for described IC Multiple technique change examples of design determine time delay.

Method described in 12. claim 11, farther includes to be based upon described IC design Time delay that multiple technique change examples determine and the target time delay of described IC design, determine described the The yield of one structure.

Method described in 13. claim 12, wherein determines that the yield of described first structure is The length of effective channel of composition element and the technique change of threshold voltage in designing based on described IC.

Method described in 14. claim 12, wherein determines that the yield of described first structure is Based on door-rank delay model, door-rank leakage power model and door-grade switches power module At least one.

Method described in 15. claim 10, wherein replaces selected the plurality of rank Composition element in one of includes that the composition element with including the transistor formed by Graphene is replaced Each composition element in one of selected the plurality of rank, to form described first structure.

Method described in 16. claim 10, wherein selects the institute relevant to described IC design State one of multiple rank to include weighting at least one node in described IC design, with described node Negative leakage contribution be directly proportional and affect with the positive side switch of described node and be inversely proportional to.

Method described in 17. claim 10, farther includes, and is identifying the plurality of level Before Bie, determine relevant to IC design, there is time delay be more than the Ai Puxi of described target time delay Grand-critical path.

Method described in 18. claim 10, wherein selects the institute relevant to described IC design State one of multiple rank and include at least one reduction object function the most following: design with described IC The cost of energy that relevant time delay cost is relevant to described IC design, and design with described IC Relevant delay-product.

19. 1 kinds of manufactures, including:

Having the non-Transient calculation machine-computer-readable recording medium of computer-executable instruction, described instruction responds The enforcement of processor makes processor perform in integrated circuit (IC) designs and selects heterocrystal pipe The method of combination, method includes:

Identifying the multiple ranks relevant to described IC design, the most each rank includes one or many Individual composition element；

Select one of the plurality of rank relevant to described IC design；

With the composition element of transistor including being formed by Graphene replace selected by the plurality of Composition element in one of rank, to form the first structure；

Determine the performance parameter of the described IC design with described first structure；

The target capabilities parameter that performance parameter determined by Bi compare designs with described IC；With

As result of the comparison indicate that described target capabilities parameter allows the described property of described IC design Can change by the further of parameter, select the another of the plurality of rank relevant to described IC design One and with including that the composition element of transistor formed by Graphene replaces the plurality of rank In described composition element in another, to form the second structure.

Manufacture described in 20. claim 19, wherein determined by performance parameter and described Target capabilities parameter is directed to the energy leakage speed of described IC design.

Manufacture described in 21. claim 19, wherein determined by performance parameter and described Target capabilities parameter is directed to the time delay of described IC design.

Manufacture described in 22. claim 19, wherein replaces described composition element to be formed One or both of described first and described second structure include that the transistor with being formed by Graphene replaces Change some described composition elements and retain other groups with the transistor formed without Graphene simultaneously Close element.