CN106026997A - Differential comparator - Google Patents
Differential comparator Download PDFInfo
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- CN106026997A CN106026997A CN201610453661.9A CN201610453661A CN106026997A CN 106026997 A CN106026997 A CN 106026997A CN 201610453661 A CN201610453661 A CN 201610453661A CN 106026997 A CN106026997 A CN 106026997A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
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Abstract
The invention discloses a differential comparator. The differential comparator comprises a positive-side main circuit, a negative-side main circuit, a common-mode detection circuit, a main bias circuit and a duplicate bias circuit; the positive-side main circuit and the negative-side main circuit are connected with each other; furthermore, both the positive-side main circuit and the negative-side main circuit are connected with the common-mode detection circuit and the duplicate bias circuit; a positive signal and positive reference voltage are input into the positive-side main circuit; a negative signal and negative reference voltage are input into the negative-side main circuit; the common-mode detection circuit is also connected with the duplicate bias circuit; the common-mode detection circuit detects change of common-mode voltage output by the positive-side main circuit and the negative-side main circuit; the duplicate bias circuit is also connected with the main bias circuit; the main bias circuit provides a bias signal for the whole differential comparator; and the duplicate bias circuit performs equal-proportional duplication of the positive-side main circuit and the negative-side main circuit. The common-mode voltage output by the differential comparator disclosed by the invention is stabilized to a certain value; deviation due to jitter of an input differential signal can be avoided; and thus, the output precision of the comparator is effectively ensured.
Description
Technical field
The present invention relates to integrated circuit fields, relate more specifically to a kind of differential comparator.
Background technology
Refer to Fig. 1, Fig. 1 is existing differential comparator circuit.In this differential comparator, four field effect transistor
(M1, M2, M3, M4) is as input pipe；Wherein, external difference signal VIP and VIN is the most defeated
Enter field effect transistor M1 and field effect transistor M4, positive and negative reference voltage V RP, VRN input field effect respectively
Pipe M2 and field effect transistor M3, and, VOP and VON is output differential signal.It addition, IB is biased electrical
Stream, field effect transistor M8 is image current source capsule, and field effect transistor M9, M10, M11 will produce one and IB
Proportional quiescent current, the ratio of this ratio is field effect transistor M9, the breadth length ratio of M10, M11 and M8
The ratio of breadth length ratio.Same, field effect transistor M5 is mirror image pipe, field effect transistor M6, M7 will produce and
The quiescent current that the bias current of field effect transistor M5 is proportional.In existing differential comparator circuit, if
VIP-VIN > VRN-VRP, then VOP > VON；If VIP-VIN < VRN-VRP, then VOP < VON；
And VOP, VON are imported into latched comparator (not shown) and carry out final size judgement.
But in the differential comparator of prior art, if comparator is in the course of the work, input signal VIP,
There is shake in VIN or VRP, VRN, it is likely that cause the current potential of C, D 2 to be all raised and lowered, this
There is difference with the drain terminal current potential of mirror image pipe M8 in sample field effect transistor M10, M11 so that field effect M10,
There is deviation in image current I1, I2 of M11, and then makes comparator output produce imbalance, reduces comparison smart
Degree.
Therefore, it is necessary to provide the differential comparator of a kind of improvement to overcome drawbacks described above.
Summary of the invention
It is an object of the invention to provide a kind of differential comparator, the differential comparator output common mode voltage of the present invention
Stable at certain value, because of input differential signal shake, deviation will not occur, be effectively guaranteed comparator
Output accuracy.
For achieving the above object, the present invention provides a kind of differential comparator, including anode main body circuit, negative terminal
Main body circuit, common mode testing circuit, main biasing circuit and replica bias circuit, described anode main body circuit divides
It is not connected with negative terminal main body circuit, common mode testing circuit, replica bias circuit, positive signal and positive reference voltage
Input described anode main body circuit, the described anode main body circuit voltage to described positive signal Yu positive reference voltage
Value compares, and exports a common mode voltage signal；Described negative terminal main body circuit respectively with anode main body circuit,
Common mode testing circuit, replica bias circuit connect, and negative signal and negative reference voltage input described negative terminal main body electricity
Road, the magnitude of voltage of described negative signal Yu negative reference voltage is compared and exports separately by described negative terminal main body circuit
One common mode voltage signal；Described common mode testing circuit is also connected with described replica bias circuit, and described common mode is examined
Slowdown monitoring circuit detects the change of described anode main body circuit and negative terminal main body circuit output common mode voltage, multiple with regulation
The operating point of biasing circuit processed；Described replica bias circuit is also connected with described main biasing circuit, and described master is inclined
Circuits provides offset signal for whole differential comparator, and described replica bias circuit is described anode main body electricity
Road and the duplicate circuit of negative terminal main body circuit, and the offset signal offer exported by described main biasing circuit is to just
End main body circuit and negative terminal main body circuit.
It is preferred that described anode main body circuit includes the first field effect transistor, the second field effect transistor, the 3rd effect
Should manage and the 4th field effect transistor；The grid of outside positive signal described first field effect transistor of input, described first
The source electrode of effect pipe is connected with the drain electrode of described 4th field effect transistor, and the drain electrode of described first field effect transistor is defeated
Go out a common mode voltage signal, and the drain electrode of described first field effect transistor, the drain electrode of the 3rd field effect transistor, second
The drain electrode of field effect transistor jointly connects and is connected with described common mode testing circuit；Described positive reference voltage inputs institute
Stating the grid of the second field effect transistor, the source electrode of described second field effect transistor is connected with described negative terminal main body circuit；
The grid of described 3rd field effect transistor is connected with described replica bias circuit, the source electrode of described 3rd field effect transistor
It is connected with external power source；The source ground of described 4th field effect transistor, the grid of described 4th field effect transistor with
Common mode testing circuit, replica bias circuit connect.
It is preferred that described negative terminal main body circuit includes the 5th field effect transistor, the 6th field effect transistor, the 7th effect
Should manage and the 8th field effect transistor, the grid of negative reference voltage described 5th field effect transistor of input, described 5th
The source electrode of effect pipe is connected with the drain electrode of described 4th field effect transistor, and the drain electrode of described 5th field effect transistor is defeated
Go out another common mode voltage signal, and the drain electrode of described 5th field effect transistor, the drain electrode of the 6th field effect transistor,
The drain electrode of seven field effect transistor jointly connects and is connected with described common mode testing circuit；Negative signal input the described 6th
The grid of field effect transistor, the source electrode of described 6th field effect transistor is connected also with the drain electrode of described 8th field effect transistor
It is connected with the source electrode of described second field effect transistor；The grid of described 7th field effect transistor and described replica bias electricity
Road connects, and the source electrode of described 7th field effect transistor is connected with external power source；The source electrode of described 8th field effect transistor
Ground connection, the grid of described 8th field effect transistor is connected with common mode testing circuit, replica bias circuit.
It is preferred that described common mode testing circuit include the 9th field effect transistor, the tenth field effect transistor, the 11st
Effect pipe, the 12nd field effect transistor, the 13rd field effect transistor, the first resistance and the second resistance；Described 9th
The grid of field effect transistor is connected with the drain electrode of described first field effect transistor, the drain electrode of described 9th field effect transistor,
The drain electrode of the tenth field effect transistor, the drain electrode of the 13rd field effect transistor connect jointly, described 9th field effect transistor
Source electrode is connected with the drain electrode of described 11st field effect transistor；The grid and the described 5th of described tenth field effect transistor
The drain electrode of field effect transistor connects, the source electrode of described tenth field effect transistor and the drain electrode of described 12nd field effect transistor
Connect；The grid of described 11st field effect transistor, the grid of the 12nd field effect transistor, the 4th field effect transistor
The grid of grid and the 8th field effect transistor connects jointly, the source electrode of the 11st field effect transistor, the 12nd field effect
The source grounding of pipe；The grid of the 13rd field effect transistor, the common connection of drain electrode, the 13rd field effect transistor
Source electrode is connected with external power source；One end of first resistance is connected with the drain electrode of the 11st field effect transistor, the first electricity
The other end of resistance is connected with replica bias circuit；One end of second resistance connects with the drain electrode of the 12nd field effect transistor
Connecing, the other end of the second resistance is connected with replica bias circuit.
It is preferred that described 9th field effect transistor, the tenth field effect transistor have identical parameter attribute.
It is preferred that described replica bias circuit include the 14th field effect transistor, the 15th field effect transistor, the tenth
Six field effect transistor, the 17th field effect transistor and the 18th field effect transistor；The grid of described 14th field effect transistor,
The grid of the 15th field effect transistor jointly connects and is connected with described main biasing circuit, described 14th field effect
The source electrode of pipe, the source grounding of the 15th field effect transistor；The drain electrode and the tenth of described 14th field effect transistor
The source electrode of six field effect transistor connects and is connected with the other end of described first resistance；Described 15th field effect transistor
Drain electrode be connected with the source electrode of the 17th field effect transistor and be connected with the other end of described second resistance；Described
The grid of 16 field effect transistor, the grid of the 17th field effect transistor jointly connect and connect with described main biasing circuit
Connect；The drain electrode of described 16th field effect transistor, the drain electrode of the 17th field effect transistor, the 18th field effect transistor
Drain electrode is common to be connected；The grid of the 18th field effect transistor be jointly connected with drain electrode and with the grid of the 7th field effect transistor
Pole, the grid of the 3rd field effect transistor connect jointly；The source electrode of the 18th field effect transistor is connected with external power source.
It is preferred that described main biasing circuit includes the 19th field effect transistor, the 20th field effect transistor and the 3rd electricity
Resistance, the source electrode of described 19th field effect transistor is connected with external power source, the drain electrode of described 19th field effect transistor
It is connected with the grid of the 17th field effect transistor and is connected with one end of the 3rd resistance, another of described 3rd resistance
End is connected with the drain electrode of the 20th field effect transistor, the grid of the 20th field effect transistor, the common connection of drain electrode, the
The source ground of 20 field effect transistor.
Compared with prior art, the differential comparator of the present invention passes through common mode testing circuit and replica bias circuit
Control make common-mode voltage that comparator exports stable a definite value, without because input signal shake and
Deviation occurs, is effectively guaranteed the precision of comparator output.
By description below and combine accompanying drawing, the present invention will become more fully apparent, and these accompanying drawings are used for explaining
Embodiments of the invention.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of the differential comparator of prior art.
Fig. 2 is the structured flowchart of differential comparator of the present invention.
Fig. 3 is the circuit structure diagram of differential comparator of the present invention.
Detailed description of the invention
With reference now to accompanying drawing, describing embodiments of the invention, element numbers similar in accompanying drawing represents similar unit
Part.As it has been described above, the invention provides a kind of differential comparator, the differential comparator output common mode of the present invention
, at certain value, will not there is deviation because of input differential signal shake, be effectively guaranteed ratio in voltage stabilization
Precision relatively.
Refer to the structured flowchart that Fig. 2, Fig. 2 are differential comparator of the present invention.As it can be seen, the difference of the present invention
Comparator is divided to include anode main body circuit, negative terminal main body circuit, common mode testing circuit, main biasing circuit and answer
Biasing circuit processed；Described anode main body circuit is respectively with negative terminal main body circuit, common mode testing circuit, duplication partially
Circuits connects, and positive signal VIP and positive reference voltage VRP inputs described anode main body circuit, described anode
The magnitude of voltage of described positive signal VIP and positive reference voltage VRP is compared by main body circuit, and after output relatively
A common mode voltage signal；Described negative terminal main body circuit respectively with anode main body circuit, common mode testing circuit,
Replica bias circuit connects, and negative signal VIN inputs described negative terminal main body circuit, institute with negative reference voltage V RN
State negative terminal main body circuit the magnitude of voltage of described negative signal VIN with negative reference voltage V RN is compared, and defeated
Go out another common mode voltage signal after comparison；Described common mode testing circuit is also connected with described replica bias circuit,
Described common mode testing circuit detects the change of described anode main body circuit and the common-mode voltage of negative terminal main body circuit output
Change, produce the voltage signal of respective change, be reconverted into the current signal of change afterwards, make replica bias electricity
The operating point on road changes, and replica bias circuit provides change for anode main body circuit and negative terminal main body circuit
Bias current, form feedback loop, and then make comparator output common mode voltage stabilization；Described duplication is inclined
Circuits is also connected with described main biasing circuit, works accurately so that replica bias circuit is biased in
Point, to ensure the accuracy of its work；Described main biasing circuit provides offset signal for whole differential comparator,
Described replica bias circuit is the duplicate circuit of described anode main body circuit and negative terminal main body circuit, and by described
The offset signal of main biasing circuit output provides to anode main body circuit and negative terminal main body circuit.The present invention's
In differential comparator, described common mode testing circuit can detect anode main body circuit and export with negative terminal main body circuit
The change of common mode voltage signal, and export detect signal accordingly, this detection signal is converted into the change of electric current
Changing, the electric current of this change is used for regulating and controlling the operating point of replica bias circuit, and then realizes comparator output
Dynamic realtime biasing regulation and control.Thus, the differential comparator of the present invention passes through common mode testing circuit and replica bias
The control of circuit make comparator output common mode voltage stabilization at certain value, without because input signal shake and
Deviation occurs, the precision of comparator output can be effectively ensured.
Specifically, please in conjunction with reference to the circuit structure diagram that Fig. 3, Fig. 3 are differential comparator of the present invention.Such as figure
Shown in, described anode main body circuit includes the first field effect transistor M1, the second field effect transistor M2, the 3rd effect
Should pipe M3 and the 4th field effect transistor M4；Outside positive signal VIP inputs the grid of described first field effect transistor M1
Pole, the source electrode of described first field effect transistor M1 is connected with the drain electrode of described 4th field effect transistor M4, and described
The drain electrode of the first field effect transistor M1, the drain electrode of the 3rd field effect transistor M3, the drain electrode of the second field effect transistor M2
Common connection is also connected with described common mode testing circuit；Described positive reference voltage VRP inputs described second effect
Should the grid of pipe M2, the source electrode of described second field effect transistor M2 is connected with described negative terminal main body circuit；Described
The grid of the 3rd field effect transistor M3 is connected with described replica bias circuit, the source of described 3rd field effect transistor M3
Pole is connected with external power source VDD；The source ground of described 4th field effect transistor M4, described 4th field effect
The grid of pipe M4 is connected with common mode testing circuit, replica bias circuit.Thus, described anode main body circuit pair
The magnitude of voltage of described positive signal VIP and the positive reference voltage VRP of input compares, and after output relatively
Common mode voltage signal VON, and described common mode voltage signal VON is defeated from the drain electrode of the first field effect transistor M1
Go out.
Described negative terminal main body circuit includes the 5th field effect transistor M5, the 6th field effect transistor M6, the 7th field effect
Pipe M7 and the 8th field effect transistor M8；Negative reference voltage V RN inputs the grid of described 5th field effect transistor M5,
The source electrode of described 5th field effect transistor M5 is connected with the drain electrode of described 4th field effect transistor M4, and the described 5th
The drain electrode of field effect transistor M5, the drain electrode of the 6th field effect transistor M6, the 7th field effect transistor M7 drain electrode common
Connect and be connected with described common mode testing circuit；Negative signal VIP inputs the grid of described 6th field effect transistor M6
Pole, the source electrode of described 6th field effect transistor M6 is connected and with described with the drain electrode of described 8th field effect transistor M8
The source electrode of the second field effect transistor M2 connects；The grid of described 7th field effect transistor M7 and described replica bias electricity
Road connects, and the source electrode of described 7th field effect transistor M7 is connected with external power source VDD；Described 8th field effect
The source ground of pipe M8, the grid of described 8th field effect transistor M8 and common mode testing circuit, replica bias electricity
Road connects.Thus, the described negative terminal main body circuit described negative signal VIN to inputting and negative reference voltage V RN
Magnitude of voltage compare, and export relatively after another common mode voltage signal VOP, and described common-mode voltage letter
Number VOP exports from the drain electrode of the 5th field effect transistor M5.
Described common mode testing circuit includes the 9th field effect transistor M9, the tenth field effect transistor M10, the 11st effect
Should pipe M11, the 12nd field effect transistor M12, the 13rd field effect transistor M13, the first resistance R1 and second
Resistance R2；The grid of described 9th field effect transistor M9 is connected with the drain electrode of described first field effect transistor M1,
The drain electrode of described 9th field effect transistor M9, the drain electrode of the tenth field effect transistor M10, the 13rd field effect transistor M13
Drain electrode jointly connect, the source electrode of described 9th field effect transistor M9 and described 11st field effect transistor M11
Drain electrode connects；The grid of described tenth field effect transistor M10 is connected with the drain electrode of described 5th field effect transistor M5,
The source electrode of described tenth field effect transistor M10 is connected with the drain electrode of described 12nd field effect transistor M12；Described
The grid of 11 field effect transistor M11, the grid of the 12nd field effect transistor M12, the 4th field effect transistor M4
The grid of grid and the 8th field effect transistor M8 connects jointly, the source electrode of the 11st field effect transistor M11, the tenth
The source grounding of two field effect transistor M12；The grid of the 13rd field effect transistor M13, the common connection of drain electrode,
The source electrode of the 13rd field effect transistor M13 is connected with external power source VDD；One end and the tenth of first resistance R1
The drain electrode of one field effect transistor M11 connects, and the other end of the first resistance R1 is connected with replica bias circuit；The
One end of two resistance R2 is connected with the drain electrode of the 12nd field effect transistor M12, the other end of the second resistance R2 with
Replica bias circuit connects.And, in a preferred embodiment of the invention, described 9th field effect transistor M9,
Ten field effect transistor M10 have identical parameter attribute, namely the architectural feature of two field effect transistor is complete
Identical.
Described replica bias circuit include the 14th field effect transistor M14, the 15th field effect transistor M15, the tenth
Six field effect transistor M16, the 17th field effect transistor M17 and the 18th field effect transistor M18；Described 14th
The grid of effect pipe M14, the grid of the 15th field effect transistor M15 jointly connect and with described main biasing circuit
Connect, the source electrode of described 14th field effect transistor M14, the source grounding of the 15th field effect transistor M15；
The drain electrode of described 14th field effect transistor M14 is connected with the source electrode of the 16th field effect transistor M16 and with described
The other end of one resistance R1 connects；The drain electrode of described 15th field effect transistor M15 and the 17th field effect transistor
The source electrode of M17 connects and is connected with the other end of described second resistance R2；Described 16th field effect transistor M16
Grid, the grid of the 17th field effect transistor M17 jointly connects and is connected with described main biasing circuit；Described
The drain electrode of the 16th field effect transistor M16, the drain electrode of the 17th field effect transistor M17, the 18th field effect transistor
The drain electrode of M18 connects jointly；The grid of the 18th field effect transistor M18 be jointly connected with drain electrode and with the 7th
The grid of effect pipe M7, the grid of the 3rd field effect transistor M3 connect jointly；18th field effect transistor M18
Source electrode be connected with external power source VDD.Concrete as it is shown on figure 3, the present invention replica bias circuit structure with
Anode main body circuit and negative terminal main body circuit structure are consistent, and each device size is the same, thus realize described multiple
The 1:1 of anode main body circuit and negative terminal main body circuit is replicated by biasing circuit processed.
Described main biasing circuit includes the 19th field effect transistor M19, the 20th field effect transistor M20 and the 3rd electricity
Resistance R3, the source electrode of described 19th field effect transistor M19 is connected with external power source VDD, described 19th
The drain electrode of effect pipe M19 be connected with the grid of the 17th field effect transistor M17 and with one end of the 3rd resistance R3
Connect, the grid input external reference voltages vb1 of described 19th field effect transistor M19, thus described ten
Drain electrode output bias voltage vb2, the described bias voltage vb2 input of nine field effect transistor M19 is to the described tenth
Seven field effect transistor M17；The other end of described 3rd resistance R3 and the drain electrode of the 20th field effect transistor M20 are even
Connect, the grid of the 20th field effect transistor M20, the common connection of drain electrode, the source electrode of the 20th field effect transistor M20
Ground connection.
Please in conjunction with reference to Fig. 2 and Fig. 3, the work process of differential comparator of the present invention is described.
3rd field effect transistor M3, the 4th field effect transistor M4, the 7th field effect transistor M7, the 8th field effect transistor
M8 is electric current source capsule.Think that described anode main body circuit and negative terminal main body circuit provide quiescent bias current.
As it has been described above, the differential comparator of the present invention mainly realizes the difference comparsion of VIP-VIN Yu VRN-VRP.
Specifically, when the differential comparator of the present invention is biased on ideal operation point, its output common mode voltage signal
VON, VOP meansigma methods is equal to preset value, and now the first resistance R1, the second resistance R2 two ends no-voltage are poor,
Namely do not have electric current to flow through on the first resistance R1, the second resistance R2.When differential comparator output common mode voltage
(more than design load) time higher, i.e. (VON+VOP)/2 voltage is higher and is more than preset value, that is to say joint
Point A, B current potential meansigma methods raises, owing to the 9th field effect transistor M9, the tenth field effect transistor M10 are all operated in
Saturation region, has:
Wherein, μNIt is the mobility of the 9th field effect transistor M9, COXIt it is the gate oxidation of the 9th field effect transistor M9
Layer thickness, W/L is the breadth length ratio of the 9th field effect transistor M9, VGSIt it is the grid source electricity of the 9th field effect transistor M9
Pressure, VDSIt is the drain-source voltage of the 9th field effect transistor M9, VTHIt is the threshold voltage of the 9th field effect transistor M9,
λ is a constant.9th field effect transistor M9, the tenth field effect transistor M10 are to input pipe, its breadth length ratio phase
Deng.If now A, E point current potential is respectively VA、VE, then the gate source voltage V of the 9th field effect transistor M9GS
Can be expressed as:
VGS=VA-VE (2)
If A, B node current potential meansigma methods raise, it is assumed that VA、VBAll raise Δ V, if now the 9th effect
Should the gate source voltage of pipe M9 be VGS’, have:
VGS'=VA+ΔV-VE (3)
Because the 9th field effect transistor M9, the tenth field effect transistor M10 normally work, drain-source current IDSKeep not
Become, and now VDSThe most constant, so VEAlso Δ V can be raised；In like manner, VF current potential also will raise Δ V.
So make the first resistance R1, the second resistance R2 two ends there is voltage difference, will be formed by node E to G, F
To the electric current of H, this electric current flows into G, H point, and according to Kirchhoff's law, G, H point current potential will raise.
This can make the 16th field effect transistor M16, the gate source voltage V of the 17th field effect transistor M17GSReduce, and this
Time the 16th field effect transistor M16, the drain-source current I of the 17th field effect transistor M17DSConstant, according to formula
(1), the 16th field effect transistor M16, the drain terminal current potential of the 17th field effect transistor M17 will raise, namely K
Point current potential will raise, and so make the grid current potential rising of the 3rd field effect transistor M3, the 7th field effect transistor M7,
Gate source voltage VGSTo reduce, also according to formula (1), now the 3rd field effect transistor M3, the 7th field effect transistor
M7 drain-source current IDSConstant, its drain-source voltage VDSTo increase, so 2 current potentials of A, B will reduce.
In like manner, when 2 current potential meansigma methodss of A, B arrange value less than ideal, and above-mentioned common mode feedback loop can make this 2 point
Voltage is increased to arrange value.So by the control of Commom-mode feedback loop so that 2 current potentials of A, B are able to
Stable, that is to say so that output common mode voltage VON, VOP are stable.
Above in association with most preferred embodiment, invention has been described, but the invention is not limited in disclosed above
Embodiment, and amendment, the equivalent combinations that the various essence according to the present invention is carried out should be contained.
Claims (7)
1. a differential comparator, it is characterised in that include anode main body circuit, negative terminal main body circuit, be total to
Mould testing circuit, main biasing circuit and replica bias circuit, described anode main body circuit respectively with negative terminal main body
Circuit, common mode testing circuit, replica bias circuit connect, and positive signal inputs described anode with positive reference voltage
Main body circuit, the magnitude of voltage of described positive signal with positive reference voltage is compared by described anode main body circuit,
And export a common mode voltage signal；Described negative terminal main body circuit detects electricity with anode main body circuit, common mode respectively
Road, replica bias circuit connect, and negative signal and negative reference voltage input described negative terminal main body circuit, described negative
End main body circuit compares and exports another common-mode voltage to the magnitude of voltage of described negative signal Yu negative reference voltage
Signal；Described common mode testing circuit is also connected with described replica bias circuit, and described common mode testing circuit detects
Described anode main body circuit and the change of negative terminal main body circuit output common mode voltage, to regulate replica bias circuit
Operating point；Described replica bias circuit is also connected with described main biasing circuit, and described main biasing circuit is whole
Individual differential comparator provides offset signal, and described replica bias circuit is described anode main body circuit and negative terminal master
The duplicate circuit of body circuit, and the offset signal offer exported by described main biasing circuit is to anode main body circuit
With negative terminal main body circuit.
2. differential comparator as claimed in claim 1, it is characterised in that described anode main body circuit includes
First field effect transistor, the second field effect transistor, the 3rd field effect transistor and the 4th field effect transistor；Outside positive signal is defeated
Enter the grid of described first field effect transistor, the source electrode of described first field effect transistor and described 4th field effect transistor
Drain electrode connects, and the drain electrode of described first field effect transistor exports a common mode voltage signal, and described first effect
Should the drain electrode of pipe, the drain electrode of the 3rd field effect transistor, the drain electrode of the second field effect transistor jointly connect and common with described
Mould testing circuit connects；The grid of described positive reference voltage described second field effect transistor of input, described second
The source electrode of effect pipe is connected with described negative terminal main body circuit；The grid of described 3rd field effect transistor and described duplication
Biasing circuit connects, and the source electrode of described 3rd field effect transistor is connected with external power source；Described 4th field effect transistor
Source ground, the grid of described 4th field effect transistor is connected with common mode testing circuit, replica bias circuit.
3. differential comparator as claimed in claim 2, it is characterised in that described negative terminal main body circuit includes
5th field effect transistor, the 6th field effect transistor, the 7th field effect transistor and the 8th field effect transistor, negative reference voltage is defeated
Enter the grid of described 5th field effect transistor, the source electrode of described 5th field effect transistor and described 4th field effect transistor
Drain electrode connects, and the drain electrode of described 5th field effect transistor exports another common mode voltage signal, and described 5th
The drain electrode of effect pipe, the drain electrode of the 6th field effect transistor, the drain electrode of the 7th field effect transistor connect and jointly with described
Common mode testing circuit connects；Negative signal inputs the grid of described 6th field effect transistor, described 6th field effect transistor
Source electrode be connected with the drain electrode of described 8th field effect transistor and be connected with the source electrode of described second field effect transistor；Institute
The grid stating the 7th field effect transistor is connected with described replica bias circuit, the source electrode of described 7th field effect transistor with
External power source connects；The source ground of described 8th field effect transistor, the grid of described 8th field effect transistor is together
Mould testing circuit, replica bias circuit connect.
4. differential comparator as claimed in claim 3, it is characterised in that described common mode testing circuit includes
9th field effect transistor, the tenth field effect transistor, the 11st field effect transistor, the 12nd field effect transistor, the 13rd
Effect pipe, the first resistance and the second resistance；The grid of described 9th field effect transistor and described first field effect transistor
Drain electrode connect, the drain electrode of described 9th field effect transistor, the drain electrode of the tenth field effect transistor, the 13rd field effect
The drain electrode of pipe connects jointly, and the source electrode of described 9th field effect transistor connects with the drain electrode of described 11st field effect transistor
Connect；The grid of described tenth field effect transistor is connected with the drain electrode of described 5th field effect transistor, the described ten effect
Should be connected with the drain electrode of described 12nd field effect transistor by the source electrode of pipe；The grid of described 11st field effect transistor,
The grid of the grid of the 12nd field effect transistor, the grid of the 4th field effect transistor and the 8th field effect transistor connects jointly,
The source electrode of the 11st field effect transistor, the source grounding of the 12nd field effect transistor；The grid of the 13rd field effect transistor
Pole, the common connection of drain electrode, the source electrode of the 13rd field effect transistor is connected with external power source；One end of first resistance
Drain electrode with the 11st field effect transistor is connected, and the other end of the first resistance is connected with replica bias circuit；Second
One end of resistance is connected with the drain electrode of the 12nd field effect transistor, the other end of the second resistance and replica bias circuit
Connect.
5. differential comparator as claimed in claim 4, it is characterised in that described 9th field effect transistor, the
Ten field effect transistor have identical parameter attribute.
6. differential comparator as claimed in claim 4, it is characterised in that described replica bias circuit includes
14th field effect transistor, the 15th field effect transistor, the 16th field effect transistor, the 17th field effect transistor and the tenth
Eight field effect transistor；The grid of described 14th field effect transistor, the grid of the 15th field effect transistor connect also jointly
It is connected with described main biasing circuit, the source electrode of described 14th field effect transistor, the source electrode of the 15th field effect transistor
All ground connection；The drain electrode of described 14th field effect transistor is connected with the source electrode of the 16th field effect transistor and with described
The other end of one resistance connects；The drain electrode of described 15th field effect transistor is with the source electrode of the 17th field effect transistor even
Connect and be connected with the other end of described second resistance；The grid of described 16th field effect transistor, the 17th effect
The grid of pipe should jointly connect and be connected with described main biasing circuit；The drain electrode of described 16th field effect transistor,
The drain electrode of the 17th field effect transistor, the drain electrode of the 18th field effect transistor connect jointly；18th field effect transistor
Grid is jointly connected with drain electrode and is jointly connected with grid, the grid of the 3rd field effect transistor of the 7th field effect transistor；
The source electrode of the 18th field effect transistor is connected with external power source.
7. differential comparator as claimed in claim 6, it is characterised in that described main biasing circuit includes the
19 field effect transistor, the 20th field effect transistor and the 3rd resistance, the source electrode of described 19th field effect transistor is with outer
Portion power supply connects, and the drain electrode of described 19th field effect transistor is connected with the grid of the 17th field effect transistor and with the
One end of three resistance connects, and the other end of described 3rd resistance and the drain electrode of the 20th field effect transistor connect, the
The grid of 20 field effect transistor, the common connection of drain electrode, the source ground of the 20th field effect transistor.
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| CN201610453661.9A CN106026997B (en) | 2016-06-21 | 2016-06-21 | Differential comparator |
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| CN106026997B CN106026997B (en) | 2018-09-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107749709A (en) * | 2017-12-06 | 2018-03-02 | 西安智多晶微电子有限公司 | A kind of charge pump for fpga chip |
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| US7375559B1 (en) * | 2005-07-07 | 2008-05-20 | Marvell International Ltd. | Differential comparator with a replica input stage to set the accurate bias current for improved common mode rejection |
| CN102158202A (en) * | 2011-04-15 | 2011-08-17 | 上海大学 | High accuracy digital adjustable RC (Resistance Capacitance) oscillator |
| US20110291758A1 (en) * | 2010-05-28 | 2011-12-01 | Xilinx, Inc. | Differential comparator circuit having a wide common mode input range |
| CN103618522A (en) * | 2013-11-26 | 2014-03-05 | 苏州贝克微电子有限公司 | Self-adaptation threshold value circuit of comparator |
| CN103825565A (en) * | 2012-11-16 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Operational amplifier |
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| US7375559B1 (en) * | 2005-07-07 | 2008-05-20 | Marvell International Ltd. | Differential comparator with a replica input stage to set the accurate bias current for improved common mode rejection |
| US20110291758A1 (en) * | 2010-05-28 | 2011-12-01 | Xilinx, Inc. | Differential comparator circuit having a wide common mode input range |
| CN102158202A (en) * | 2011-04-15 | 2011-08-17 | 上海大学 | High accuracy digital adjustable RC (Resistance Capacitance) oscillator |
| CN103825565A (en) * | 2012-11-16 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Operational amplifier |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107749709A (en) * | 2017-12-06 | 2018-03-02 | 西安智多晶微电子有限公司 | A kind of charge pump for fpga chip |
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| CN106026997B (en) | 2018-09-21 |
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