CN106024851A - Time-saving super-junction fast recovery diode preparation method - Google Patents
Time-saving super-junction fast recovery diode preparation method Download PDFInfo
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- 238000011084 recovery Methods 0.000 title claims abstract description 22
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
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- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
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- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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Abstract
The invention reveals a time-saving super-junction fast recovery diode preparation method, and the method comprises the steps: preparing an N-type doped epitaxial layer on a substrate layer, implanting a P-type doped part on the epitaxial layer, repeatedly carrying out the above steps, and preparing a super-junction structure where a P-type vertical column and the N-type doped epitaxial layer are interlaced; or implanting P-type doped and N-type doped parts on the epitaxial layer, and preparing the super-junction structure where the P-type vertical column and the N-type doped epitaxial layer are interlaced. A P-type doped anode region and a P-type doped liming ring region are formed at the top of the super-junction structure, and the super-junction structure is also provided with an oxidation layer and a polysilicon gate. Pt is doped in the anode region, so as to form a metal anode, and a metal layer of the anode is passivated. A cathode metal layer is prepared through multilayer metallization.
Description
Technical field
The invention belongs to semiconductor components and devices manufacturing technology field, be specifically related to the preparation method of super junction fast recovery diode.
Background technology
Fast recovery diode (Fast Recovery Diode, FRD) is mainly used as switching device, and its reverse recovery time is short, can reduce device loss with faster devices switching speed；And forward voltage drop is low, reverse pressure height, prevent device from burning because of logical super-high-current.And at present switch power module topological structure typically requires high-voltage power part and does switching tube, its exemplary power device is pressure for 600V, and in the performance of the aspects such as pressure performance, reverse recovery time, forward voltage drop, matched fast recovery diode is had higher requirement.And commonly PIN diode device architecture and technique can not meet the performance indications of high tension apparatus.
Super junction (Super Junction) device can obtain low on-state power consumption and high switching speed simultaneously.Identical pressure under the conditions of, the conducting resistance of super junction diode be less than PIN diode conducting resistance.For super junction FRD, in forward voltage drop, the most pressure it is better than traditional F RD with switching speed three aspect overall performance.
By outer layer growth and ion implanting alternately, the growth number of times forming super-junction structures is directly directly proportional to the height of cost in the realization of super-junction structures.And super junction FRD is a kind of charge compensation type device, if charge balance can not be accomplished in inside, breakdown voltage can be made to be remarkably decreased.By the control of super-junction device n district, p district size and doping content ensures the charge balance of super-junction device, this is the highest to the requirement of technique, correspondingly also improves production cost.
Summary of the invention
It is an object of the invention to provide the preparation method of a kind of super junction fast recovery diode that can shorten the time.
For achieving the above object, the present invention provides the preparation method of a kind of super junction fast recovery diode, comprises the steps:
Preparation super-junction structures, super-junction structures includes substrate layer and epitaxial layer, also includes some spaced P doping columns being formed at substrate layer；
The first oxide layer is formed at epitaxial layer top；
Form the first implantation window in the first oxide layer to adulterate limit the position of ring region to define p-type doping anode region and p-type, implant p-type doped region at the first implantation window, remove the first oxide layer；
Knot is to form p-type doping anode region and p-type doping limit ring region；
The second oxide layer is formed at epitaxial layer top；
Polysilicon gate is formed at the second oxide layer top；
Form the second implantation window to define anode metal district in the second oxide layer and polysilicon gate, form anode electrode at the second implantation window Pt that adulterates；
Preparation passivation protection layer；
Metallize bottom substrate layer, grow Ti, Ni, Ag metal level successively, form cathode electrode.
Further as an embodiment of the present invention is improved, and p-type adulterates anode region at least across three P doping columns, each p-type doping limit ring region correspondence one P doping column.
As the further improvement of an embodiment of the present invention, passivation protection layer is Si3N4。
As the further improvement of an embodiment of the present invention, the second oxide layer top uses polysilicon deposition to form polysilicon gate.
As the further improvement of an embodiment of the present invention, the preparation of super junction includes:
S1, prepare substrate layer；
S2, above substrate layer, prepare the first N-type epitaxy layer；
S3, in the first N-type epitaxy layer, form the first hard mask layer, the first hard mask layer is formed at least one the 3rd implantation window, implants the first conduction type doped region at the 3rd implantation window, remove the first hard mask layer；
S4, in the first N-type epitaxy layer, grow the second N-type epitaxy layer；
Repeat S3 to S4, form the first conduction type doping column, constitute the first conduction type column and the staggered super-junction structures of N-type epitaxy layer.
Further improvement as an embodiment of the present invention, between S3 and S4, also include S3 ', first N-type epitaxy layer is formed the second hard mask layer, second hard mask layer is formed at least one the 4th implantation window, implant the second conduction type doped region at the 4th implantation window, remove the second hard mask layer.
It is thusly-formed and there is the first conduction type and the super-junction structures of the second conduction type doping column.
As the further improvement of an embodiment of the present invention, substrate layer is attached most importance to the silicon substrate of arsenic doped or phosphorus.
As the further improvement of an embodiment of the present invention, substrate layer is N-type substrate.
As the further improvement of an embodiment of the present invention, the first conduction type is doped to p-type doping.
As the further improvement of an embodiment of the present invention, the 3rd implantation window and the 4th implantation window position are staggered.
Compared with prior art, the method that the present invention provides can obtain conforming P/N doping column, to ensure charge balance, reaches low grade fever and accumulates, and can shorten the growth time of epitaxial layer thus cost-effective.
Accompanying drawing explanation
Fig. 1 a-1g is the step schematic diagram of super junction preparation method one embodiment of the present invention；
Fig. 2 a-2f is the step schematic diagram of the another embodiment of preparation method of the present invention；
Fig. 3 is the structural representation that the present invention prepares super junction FRD mono-embodiment；
Fig. 4 a-4f is the step schematic diagram of super junction FRD preparation method of the present invention.
Detailed description of the invention
Describe the present invention below with reference to detailed description of the invention shown in the drawings.But these embodiments are not limiting as the present invention, structure, method or conversion functionally that those of ordinary skill in the art is made according to these embodiments are all contained in protection scope of the present invention.
The method of the present invention includes the preparation of super-junction structures and prepares FRD device two parts at super-junction structures top.
First embodiment of super-junction structures preparation method, as shown in Fig. 1 a-g, comprises the steps:
S1, as shown in Figure 1a, prepares substrate layer 101.Substrate layer 101 is attached most importance to the silicon substrate of arsenic doped or phosphorus, for example, N-type substrate.
Further, substrate layer 101 resistivity is 0.001-0.005ohm cm.
S2, as shown in Figure 1 b, prepares the first N-type epitaxy layer 103 above substrate layer 101.
Further, this N-type epitaxy layer 103 thickness is 5-15 μm.
Further, corresponding to the voltage requirements of 600V, n-type doping concentration is 1E15/cm3-3E15/cm3.Corresponding different voltage, changes doping content accordingly.
S3, above the first N-type epitaxy layer 103, form the first hard mask layer (not shown).Utilizing light shield and use photo-etching processes to form at least one implantation window on the first hard mask layer, this window is used for implanting p-type drift region.The position of this window definition P doping column.At implantation window, the first N-type epitaxy layer 103 is exposed out.
Further, window width is 1-10 μm.
Then, as illustrated in figure 1 c, it is ion implanted by carrying out p-type in implantation window, the first N-type epitaxy layer 103 is prepared P doped region 105.
Further, corresponding to the voltage requirements of 600V, p-type doping content is 1E15/cm3-3E15/cm3.Corresponding different voltage, changes doping content accordingly.
After implantation completes, remove hard mask layer, make the first N-type epitaxy layer 103 the most exposed.
S4, above N-type epitaxy layer 103, form the second hard mask layer (not shown).Utilizing light shield and use photo-etching processes to form at least one implantation window on the second hard mask layer, this window is used for implanted with n-type drift region.The position of this window definition N doping column.At implantation window, the first N-type epitaxy layer 103 is exposed out.
This implantation window is staggered with the implantation window position in S3, makes to ultimately form staggered adjacent P doping column and N doping column.
Further, window width is 1-10 μm.
As shown in Figure 1 d, it is ion implanted by N-type in implantation window, the first N-type epitaxy layer 103 is prepared N doped region 107.
Further, corresponding to the voltage requirements of 600V, p-type doping content is 1E15/cm3-3E15/cm3.Corresponding different voltage, changes doping content accordingly.
After implantation completes, remove hard mask layer, make N-type epitaxy layer 103 the most exposed.
S5, as shown in fig. le, grows the second N-type epitaxy layer 109 in the first N-type epitaxy layer 103.
Further, this second N-type epitaxy layer 109 thickness is 3-10um.
Further, corresponding to the voltage requirements of 600V, n-type doping concentration is 1E15/cm3-3E15/cm3.Corresponding different voltage, changes doping content accordingly.
Repeating technique X time shown in S3 to S5, wherein, X is positive integer.
It is situation when 7 layers that Fig. 1 f-1g schematically shows epitaxial layer.P doped region and N doped region can spread by the vertical direction during subsequent thermal, extend in adjacent N-type epitaxy layer, until the homotype doped region of adjacent N-type epitaxy layer is connected.
Above-mentioned steps S3 and S4 also can be inverted, and the most first carry out n-type doping, then carry out p-type doping.
By the super-junction structures that above-mentioned steps, composition P doping column and N doping column are alternately arranged.In each epitaxial layer, the doped region of different conduction-types is arranged alternately.
Second embodiment of super-junction structures preparation method of the present invention, as shown in Fig. 2 a-f, comprises the steps:
S1, as shown in Figure 2 a, prepares substrate layer 101 '.Substrate layer 101 ' is attached most importance to the N-type silicon substrate of arsenic doped or phosphorus.
Further, substrate layer 101 ' resistivity is 0.001-0.005ohm-cm.
S2, as shown in Figure 2 b, in substrate layer 101 ' top preparation the first N-type epitaxy layer 103 '.
Further, this N-type epitaxy layer 103 ' thickness is 5-15 μm.
Further, corresponding to the voltage requirements of 600V, n-type doping concentration is 1E15/cm3-3E15/cm3.Corresponding different voltage, changes doping content accordingly.
S3, first N-type epitaxy layer 103 ' top formed the first hard mask layer (not shown).Utilizing light shield and use photo-etching processes to form at least one implantation window on the first hard mask layer, this window is used for implanting p-type drift region.The position of window definition P doping column.At implantation window, the first N-type epitaxy layer 103 ' is exposed out.
Further, window width is 1-10 μm.
Then, it is ion implanted by p-type in implantation window, in the first N-type epitaxy layer 103 ', forms P doped region 105 ' as shown in Figure 2 c.
Further, corresponding to the voltage requirements of 600V, p-type doping content is 1E15/cm3-3E15/cm3.Corresponding different voltage, changes doping content accordingly.
After implantation completes, remove hard mask layer, make the first N-type epitaxy layer 103 ' the most exposed.
S4, in the first N-type epitaxy layer 103 ' upper growth the second N-type epitaxy layer 109 '.
Further, this second N-type epitaxy layer 109 ' thickness is 3-10um.
Further, corresponding to the voltage requirements of 600V, n-type doping concentration is 1E15/cm3-3E15/cm3.Corresponding different voltage, changes doping content accordingly.
Repeating technique X time shown in S3 to S4, wherein, X is positive integer.
As shown in Fig. 2 e-2f, P doped region 105 ' is in the vertical direction diffusion during subsequent thermal, extends in adjacent N-type epitaxy layer, until being connected with the P doped region 105 ' of adjacent N-type epitaxy layer, constitutes P doping column.
By above-mentioned steps, constitute the super-junction structures that P doping column is alternately arranged with N-type epitaxy layer.P doping column constitutes the p-type drift region of super junction-semiconductor device.
In an embodiment of the present invention, carry out FRD device at the super-junction structures top completed to prepare.Fig. 3 and Fig. 4 is shown respectively the plane FRD device prepared with the first embodiment and the second embodiment.
Fig. 3 illustrates, at the adjacent top surface of epitaxial layer, multiple P doping column 105 and N doping columns 107 alternately collectively constitute a super-junction structures, and carrying is formed at the FRD device 130 at super-junction structures top.Anode metal layer is formed at epitaxial layer top, and cathode metal layer is formed at bottom substrate 101.
Fig. 4 f illustrates, at the adjacent top surface of epitaxial layer, multiple P doping column 105 ' is alternately arranged with N-type epitaxy layer, collectively constitutes a super-junction structures, and carrying is formed at the FRD device 130 ' at super-junction structures top.Remaining structure is identical with Fig. 3.
Specifically, seeing Fig. 4 a-Fig. 4 f, as a example by the super-junction structures of the second embodiment, the preparation process of plane FRD device comprises the steps, as used the super-junction structures of the first embodiment, and the identical (not shown) of preparation method of FRD:
S1, as shown in fig. 4 a, forms the first oxide layer 201 at epitaxial layer top, and oxide layer growth mode can be high-temperature oxydation or SiO2Deposition.
S2, epitaxial layer top formed p-type doping.
Concrete, utilize light shield and use photo-etching processes to form implantation window in the first oxide layer 201, this window is used for implanting p-type doping.Window definition p-type doping anode region 204 and the position of p-type doping limit ring region 205.At implantation window, epitaxial layer top is exposed out.
Wherein, p-type doping anode region is at least across three P doping columns 105 '.The corresponding P doping column 105 ' of each p-type doping limit ring region.
Then, it is ion implanted by p-type in implantation window, forms p-type doped region.
By conventional methods such as such as hf etchings, remove the first oxide layer 201.
S3, employing conventional method knot p-type doped region, make p-type doping diffusion, forms the p-type doping anode region 204 shown in Fig. 4 b at epitaxial layer top and p-type doping limits ring region 205.
S4, as shown in Figure 4 b, uses such as SiO2Sedimentation or high-temperature oxidation, form the second oxide layer 202 at epitaxial layer top.
S5, as shown in Figure 4 b, uses polysilicon deposition to form polysilicon gate 206 at the second oxide layer 202 top.
S6, anode metallization.As illustrated in fig. 4 c, utilizing etching technics to form window in the second oxide layer 202 and polysilicon gate 206, at window, epitaxial layer top is exposed out.Wherein, as shown in figure 4d, doped precious metal, for example, Pt or Au, preferably Pt at window corresponding above p-type doping anode region 204, form anode electrode 207.Precious metal doping can reduce minority carrier life time, shortens FRD reverse recovery time.Heavy metal doping can use evaporation or one layer of Pt of sputtering at the correspondence window of epitaxial layer top, the most at high temperature carries out the mode of Pt diffusion.
S7, as shown in fig 4e, forms Si3N4Passivation protection layer 208.Use such as chemical deposition or other conventional methods, growth of passivation protective layer 208.
S8, cathode metallization.As shown in fig. 4f, carry out bottom substrate 101 thinning and clean after, use physical deposition or the mode of evaporation, below substrate 101, grow Ti, Ni, Ag metal level successively, form cathode electrode.
The present invention, by being ion implanted, can obtain conforming P/N doping column, to ensure charge balance, reaches low grade fever and accumulates.The method utilizes being ion implanted of multiple different-energy, can shorten the growth time of super junction epitaxial layer thus cost-effective, simplifies the processing technology of super junction FRD.
It is to be understood that, although this specification is been described by according to embodiment, but the most each embodiment only comprises an independent technical scheme, this narrating mode of description is only for clarity sake, those skilled in the art should be using description as an entirety, technical scheme in each embodiment can also form, through appropriately combined, other embodiments that it will be appreciated by those skilled in the art that.
The a series of detailed description of those listed above is only for illustrating of the feasibility embodiment of the present invention; they also are not used to limit the scope of the invention, and all equivalent implementations or changes made without departing from skill of the present invention spirit should be included within the scope of the present invention.
Claims (10)
1. the preparation method of a super junction fast recovery diode, it is characterised in that comprise the steps:
Preparation super-junction structures, described super-junction structures includes substrate layer and epitaxial layer, also includes some being formed at
The spaced P doping column of substrate layer；
The first oxide layer is formed at described epitaxial layer top；
Form the first implantation window in the first oxide layer and limit ring region to define p-type doping anode region and p-type doping
Position, implants p-type doped region at described first implantation window, removes described first oxide layer；
Knot is to form described p-type doping anode region and p-type doping limit ring region；
The second oxide layer is formed at described epitaxial layer top；
Polysilicon gate is formed at described second oxide layer top；
The second implantation window is formed to define anode metal district, described in described second oxide layer and polysilicon gate
Second implantation window doping Pt forms anode electrode；
Preparation Si3N4Passivation protection layer；
Metallize bottom described substrate layer, grow Ti, Ni, Ag metal level successively, form negative electrode
Electrode.
The preparation method of super junction fast recovery diode the most according to claim 1, it is characterised in that
Described p-type doping anode region is at least across three P doping columns, and described each p-type doping limit ring region is corresponding
One P doping column.
The preparation method of super junction fast recovery diode the most according to claim 1, it is characterised in that institute
Stating passivation protection layer is Si3N4。
The preparation method of super junction fast recovery diode the most according to claim 1, it is characterised in that
Use polysilicon deposition to form polysilicon gate at described second oxide layer top.
The preparation method of super junction fast recovery diode the most according to claim 1, it is characterised in that
The preparation of described super junction includes:
S1, prepare substrate layer；
S2, above described substrate layer, prepare the first N-type epitaxy layer；
S3, in described first N-type epitaxy layer, form the first hard mask layer, on described first hard mask layer
Form at least one the 3rd implantation window, implant the first conduction type doped region at described 3rd implantation window, go
Except the first hard mask layer；
S4, in described first N-type epitaxy layer, grow the second N-type epitaxy layer；
Repeating S3 to S4X time, described X is positive integer.
The preparation method of super junction fast recovery diode the most according to claim 5, it is characterised in that
Between described S3 and S4, also include:
S3 ', in described first N-type epitaxy layer, form the second hard mask layer, on described second hard mask layer
Form at least one the 4th implantation window, implant the second conduction type doped region at described 4th implantation window, go
Except the second hard mask layer.
The preparation method of super junction fast recovery diode the most according to claim 5, it is characterised in that
Described substrate layer is attached most importance to the silicon substrate of arsenic doped or phosphorus.
The preparation method of super junction fast recovery diode the most according to claim 5, it is characterised in that
Described substrate layer is N-type substrate.
The preparation method of super junction fast recovery diode the most according to claim 5, it is characterised in that
Described first conduction type is doped to p-type doping.
The preparation method of super junction fast recovery diode the most according to claim 6, it is characterised in that
Described 3rd implantation window and the 4th implantation window position are staggered.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112038413A (en) * | 2020-09-10 | 2020-12-04 | 湖南大学 | Super junction type fast recovery diode device |
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| US20080246084A1 (en) * | 2007-04-05 | 2008-10-09 | Kabushiki Kaisha Toshiba | Power semiconductor device and method for producing the same |
| US20120273875A1 (en) * | 2011-04-27 | 2012-11-01 | Yedinak Joseph A | Superjunction Structures for Power Devices and Methods of Manufacture |
| CN102800701A (en) * | 2011-05-25 | 2012-11-28 | 快捷韩国半导体有限公司 | Semiconductor device having a super junction structure and method of manufacturing the same |
| CN103531465A (en) * | 2013-09-13 | 2014-01-22 | 上海集成电路研发中心有限公司 | Preparation method of fast recovery diode |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080246084A1 (en) * | 2007-04-05 | 2008-10-09 | Kabushiki Kaisha Toshiba | Power semiconductor device and method for producing the same |
| US20120273875A1 (en) * | 2011-04-27 | 2012-11-01 | Yedinak Joseph A | Superjunction Structures for Power Devices and Methods of Manufacture |
| CN102800701A (en) * | 2011-05-25 | 2012-11-28 | 快捷韩国半导体有限公司 | Semiconductor device having a super junction structure and method of manufacturing the same |
| CN103531465A (en) * | 2013-09-13 | 2014-01-22 | 上海集成电路研发中心有限公司 | Preparation method of fast recovery diode |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112038413A (en) * | 2020-09-10 | 2020-12-04 | 湖南大学 | Super junction type fast recovery diode device |
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Application publication date: 20161012 |