CN106024639A - Manufacturing method of LTPS TFT based on metal induced crystallization process - Google Patents

Manufacturing method of LTPS TFT based on metal induced crystallization process Download PDF

Info

Publication number
CN106024639A
CN106024639A CN201610584469.3A CN201610584469A CN106024639A CN 106024639 A CN106024639 A CN 106024639A CN 201610584469 A CN201610584469 A CN 201610584469A CN 106024639 A CN106024639 A CN 106024639A
Authority
CN
China
Prior art keywords
layer
metal
ltps tft
crystallization inducing
contact portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610584469.3A
Other languages
Chinese (zh)
Inventor
李松杉
刘兆松
徐源竣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201610584469.3A priority Critical patent/CN106024639A/en
Publication of CN106024639A publication Critical patent/CN106024639A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention provides a manufacturing method of an LTPS TFT based on a metal induced crystallization process. The manufacturing method comprises the steps of: forming a polycrystalline silicon thin film by adopting the metal induced crystallization process, wherein the top part of the polycrystalline silicon thin film is a metal silicide layer comprising a large number of metal ions and having an conductive property; adopting a halftone mask plate for carrying out patterning treatment on the polycrystalline silicon thin film to form an active layer, so that the metal silicide layer on a channel portion is etched away, and the purpose of reducing leakage current when the LTPS TFT is in an off state; and reserving the metal silicide layer on a source contact portion and a drain contact portion, thereby achieving the purposes of reducing contact resistance between the active layer and the source as well as the drain in the LTPS TFT.

Description

The manufacture method of LTPS TFT based on crystallization inducing metal technique
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of LTPS based on crystallization inducing metal technique The manufacture method of TFT.
Background technology
In Display Technique field, flat panel display the most progressively replaces cathode ray tube (Cathode Ray Tube, is called for short CRT) display.Panel display apparatus is thin and should because having high image quality, power saving, fuselage By advantages such as scope are wide, and it is widely used in mobile phone, TV, personal digital assistant, numeral phase The various consumption electronic products such as machine, notebook computer, desk computer, become the master in display device Stream.
Thin film transistor (TFT) (Thin Film Transistor is called for short TFT) is current liquid crystal indicator (Liquid Crystal Display is called for short LCD) and active matrix drive type ORGANIC ELECTROLUMINESCENCE DISPLAYS dress Put mainly driving in (Active Matrix Organic Light-Emitting Diode is called for short AMOLED) Dynamic element, is directly connected to the developing direction of high performance flat display device.
Thin film transistor (TFT) has various structures, prepares the material of thin film transistor active layer of corresponding construction also Have multiple, wherein, low temperature polycrystalline silicon (Low Temperature Poly-silicon is called for short LTPS) material Material is a kind of, owing to the atomic rule of low temperature polycrystalline silicon arranges, and carrier mobility Height, for the liquid crystal indicator of voltage driven type, low-temperature polysilicon film transistor has due to it Higher mobility, it is possible to use the thin film transistor (TFT) of small volume realizes driving the deflection of liquid crystal molecule Dynamic, reduce the volume shared by thin film transistor (TFT) to a great extent, increase glazed area, obtain higher Brightness and resolution；Active matrix drive type organic electroluminescence display device and method of manufacturing same for current-driven For, low-temperature polysilicon film transistor can better meet driving current requirements.
At present, in the making of LTPS, the method for low temperature crystallization is divided into the method for laser and non-of utilizing The method of laser.Wherein, crystallization inducing metal (the Metal Induced of non-laser crystallization Crystallization, MIC) as a kind of low cost, crystallization homogeneity is preferable, the letter of Making programme technique Single method is paid attention to by people in the industry；During but traditional MIC makes, due in active layer raceway groove The residual of metal ion causes TFT device leakage current when OFF state relatively big, and additionally active layer connects with source-drain electrode The area contact resistance touching district (S/D contact) is the biggest.
Summary of the invention
It is an object of the invention to provide the making side of a kind of LTPS TFT based on crystallization inducing metal technique Method, it is possible to reduce the LTPS TFT device leakage current when OFF state, and LTPS TFT device can be reduced Middle active layer and the contact impedance of source-drain electrode.
For achieving the above object, the present invention provides a kind of LTPS TFT based on crystallization inducing metal technique Manufacture method, comprise the following steps:
Step 1, offer underlay substrate, buffer layer on underlay substrate, deposit gold on the buffer layer Belong to inducing layer；
Step 2, in metal induction layer deposition of amorphous silicon films, utilize metal induction layer thin to non-crystalline silicon Film carries out crystallization inducing metal, and during crystallization inducing metal, the induction of described metal induction layer is non- The bottom-up crystallization of polycrystal silicon film forms polysilicon membrane, and metal induction layer migrates upwardly to polysilicon membrane Top and formation metal silicide layer in connection；
Step 3, provide a halftoning mask plate, use this intermediate tone mask plate to described polysilicon membrane Carrying out patterned process, obtain active layer, described active layer includes source contact portion and the leakage being positioned at two ends Pole contact site and the groove between described source contact portion and drain contact, wherein, described Source contact portion is retained with the metal silicide layer on drain contact, the metallic silicon on described groove Compound layer is etched；
Step 4, on described active layer and cushion deposit gate insulator, at described gate insulator The first metal layer is deposited and patterned on Ceng, obtains the grid above corresponding to described groove；
Step 5, on described grid and gate insulator deposit interlayer insulating film, exhausted at described interlayer Second metal level is deposited and patterned in edge layer, obtains source electrode and drain electrode.
Alternatively, described step 4 also includes: with grid as shielding layer, connects the source electrode of described active layer Contact portion and drain contact carry out p-type heavy doping；
In described step 5, described active layer, grid, source electrode and drain electrode collectively form PMOS device Part.
When described step 4 carries out p-type heavy doping, mix in described source contact portion with drain contact The ion entered is boron ion or gallium ion.
Alternatively, described step 4 also includes: with grid as shielding layer, connects the source electrode of described active layer Contact portion and drain contact carry out N-type heavy doping；
In described step 5, described active layer, grid, source electrode and drain electrode collectively form NMOS device Part.
When described step 4 carries out N-type heavy doping, mix in described source contact portion with drain contact The ion entered is phosphonium ion or arsenic ion.
The thickness depositing metal induction layer in described step 1 is 5nm-10nm, and described metallized metal is induced The material of layer is nickel or aluminum.
In described step 2, the thickness of deposition of amorphous silicon films is 50nm-100nm, at 350 DEG C-400 DEG C At a temperature of amorphous silicon membrane is carried out crystallization inducing metal.
Described step 3 use intermediate tone mask plate described polysilicon membrane carries out the tool of patterned process Body step is: is coated with one layer of photoresist on described polysilicon membrane, utilizes described intermediate tone mask plate After this layer of photoresist is exposed and is developed, obtain including the first photoresistance pattern and the second photoresistance The photoresist layer of pattern, wherein the thickness of the second photoresistance pattern is less than the thickness of described first photoresistance pattern, with Photoresist layer is shielding layer, is etched described polysilicon membrane, obtains active layer, wherein said active The source contact portion of layer is formed corresponding to described first photoresistance pattern with drain contact, described groove pair Described in Ying Yu, the second photoresistance pattern is formed.
Described step 5 also includes, before depositing second metal layer, described interlayer insulating film is carried out figure Caseization processes, obtain corresponding respectively to the first via above described source contact portion, drain contact, Second via, described source electrode, drain electrode are respectively by the first via of described interlayer insulating film, the second via It is connected with described source contact portion, drain contact.
The material of described the first metal layer and the second metal level be the one in molybdenum, titanium, aluminum and copper or Multiple heap stack combination；Described cushion, gate insulator and interlayer insulating film are silicon oxide layer, nitrogen SiClx layer or superposed the composite bed constituted with silicon nitride layer by silicon oxide layer.
Beneficial effects of the present invention: a kind of based on crystallization inducing metal technique the LTPS that the present invention provides The manufacture method of TFT, first deposition layer of metal inducing layer, in metal induction layer, deposited amorphous silicon is thin Film, utilizes metal induction layer amorphous silicon membrane to be carried out crystallization inducing metal, at crystallization inducing metal During, metal induction layer induction amorphous silicon membrane bottom-up crystallization formation polysilicon membrane, and metal Inducing layer migrate upwardly to polysilicon membrane top and the top of polysilicon membrane formed one layer the thinnest The metal silicide layer with conduction property containing a large amount of metal ions；Then intermediate tone mask plate is used Described polysilicon membrane is carried out patterned process and is formed with active layer, make the metal silicide layer on groove Etched, thus reach to reduce the purpose of the LTPS TFT device leakage current when OFF state, and source electrode connects Contact portion is retained with the metal silicide layer on drain contact, thus reaches to reduce in LTPS TFT device The purpose of the contact impedance of active layer and source-drain electrode.
Accompanying drawing explanation
Below in conjunction with the accompanying drawings, by the detailed description of the invention of the present invention is described in detail, will make the present invention's Technical scheme and other beneficial effects are apparent.
In accompanying drawing,
Fig. 1 is the flow process of the manufacture method of the LTPS TFT based on crystallization inducing metal technique of the present invention Schematic diagram；
Fig. 2 is the step 1 of the manufacture method of the LTPS TFT based on crystallization inducing metal technique of the present invention Schematic diagram；
Fig. 3-4 is the step of the manufacture method of the LTPS TFT based on crystallization inducing metal technique of the present invention The schematic diagram of 2；
Fig. 5-6 is the step of the manufacture method of the LTPS TFT based on crystallization inducing metal technique of the present invention The schematic diagram of 3；
Fig. 7 is the step 4 of the manufacture method of the LTPS TFT based on crystallization inducing metal technique of the present invention The schematic diagram of middle formation grid；
Fig. 8 is the step 4 of the manufacture method of the LTPS TFT based on crystallization inducing metal technique of the present invention In active layer carried out the heavily doped schematic diagram of p-type；
Fig. 9 is the step 4 of the manufacture method of the LTPS TFT based on crystallization inducing metal technique of the present invention In active layer carried out the heavily doped schematic diagram of N-type；
Figure 10-11 is the step of the manufacture method of the LTPS TFT based on crystallization inducing metal technique of the present invention The schematic diagram forming PMOS device is made in rapid 5；
Figure 12-13 is the step of the manufacture method of the LTPS TFT based on crystallization inducing metal technique of the present invention The schematic diagram forming nmos device is made in rapid 5.
Detailed description of the invention
By further illustrating the technological means and effect thereof that the present invention taked, below in conjunction with the present invention's Preferred embodiment and accompanying drawing thereof are described in detail.
Referring to Fig. 1, the present invention provides the making of a kind of LTPS TFT based on crystallization inducing metal technique Method, comprises the following steps:
Step 1, as shown in Figure 2, it is provided that underlay substrate 10, buffer layer 20 on underlay substrate 10, Cushion 20 deposits metal induction layer 35.
Specifically, the thickness depositing metal induction layer 35 in described step 1 is 5nm-10nm, described metal The material of metal induction layer 35 is nickel (Ni) or aluminum (Al).
Step 2, as shown in Figure 3-4, deposited amorphous silicon (amorphous in metal induction layer 35 Silicon, a-Si) thin film 36, utilize metal induction layer 35 that amorphous silicon membrane 36 is carried out crystallization inducing metal Changing, during crystallization inducing metal, metal induction layer 35 induces the bottom-up knot of amorphous silicon membrane 36 Brilliant formation polysilicon (poly-Si) thin film 30, final metal induction layer 35 migrates upwardly to polysilicon membrane The top of 30 formation metal silicide layer 31 in connection.
Specifically, in described step 2, the thickness of deposition of amorphous silicon films 36 is 50nm-100nm.
Specifically, in described step 2, at a temperature of 350 DEG C-400 DEG C, amorphous silicon membrane 36 is carried out gold Belong to induced crystallization.
Specifically, during crystallization inducing metal, the metal ion in metal induction layer 35 is as luring Stem can the most upwards replace the Si atom in the Si-Si covalent bond in amorphous silicon membrane 36 thus induce Crystallization, crystallization direction is carried out from bottom to top, and the superiors obtaining polysilicon membrane 30 after crystallization completely are gold Belong to silicide (such as Si-Ni compound etc.), and containing substantial amounts of metal ion (such as Ni from Son), thus form the metal silicide layer 31 with conduction property.
Step 3, as seen in figs. 5-6, it is provided that a halftoning mask plate 90, uses this intermediate tone mask plate 90 Described polysilicon membrane 30 being carried out patterned process, obtains active layer 33, described active layer 33 includes position Source contact portion 331 in two ends and drain contact 332 and be positioned at described source contact portion 331 and drain electrode Groove 333 between contact site 332, wherein, on described source contact portion 331 and drain contact 332 Metal silicide layer 31 be retained, the metal silicide layer 31 on described groove 333 is etched.
Specifically, described step 3 use intermediate tone mask plate 90 described polysilicon membrane 30 is carried out pattern What change processed concretely comprises the following steps: be coated with one layer of photoresist 80 on described polysilicon membrane 30, and utilizing should After this layer of photoresist 80 is exposed and develops by intermediate tone mask plate 90, obtain photoresist layer, described Photoresist layer include the first photoresistance pattern at two ends and between described first photoresistance pattern second Photoresistance pattern, wherein the thickness of the second photoresistance pattern is less than the thickness of described first photoresistance pattern, then with Described photoresist layer is shielding layer, is etched described polysilicon membrane 30, obtains active layer 35, wherein The source contact portion 331 of described active layer 35 and drain contact 332 are corresponding to described first photoresistance pattern shape Becoming, described groove 333 is formed corresponding to described second photoresistance pattern.
Specifically, in described step 3, described source contact portion 331 and the metallic silicon on drain contact 332 Compound layer 31 is retained, due in the source contact portion 331 metal silicide layer 31 with drain contact 332 There is substantial amounts of metal ion, there is electric conductivity, can reach to reduce the purpose of contact impedance, and described Metal silicide layer 31 on groove 333 is etched, the polysilicon membrane 30 of i.e. corresponding groove 333 Interior metal ion major part is etched, such that it is able to reach to reduce the purpose of leakage current.
Step 4 is as it is shown in fig. 7, deposit gate insulator on described active layer 35 and cushion 20 40, on described gate insulator 40, the first metal layer is deposited and patterned, obtains corresponding to described raceway groove Grid 45 above portion 333.
Specifically, described step 4 also includes, after forming grid 45, then with grid 45 for shielding layer pair The source contact portion 331 of described active layer 30 is carried out p-type heavy doping or N-type weight with drain contact 332 Doping, for forming p channel metal oxide semiconductor (P-channel metal oxide respectively Semiconductor, PMOS) device or n channel metal oxide semiconductor (N-channel metal Oxide semiconductor, NMOS) device.
Specifically, if being used for forming PMOS device, the most as shown in Figure 8, with grid 45 as shielding layer, The source contact portion 331 of described active layer 30 and drain contact 332 are carried out p-type heavy doping, wherein, The ion mixed in described source contact portion 331 with drain contact 332 is boron ion (B+) or gallium from Son.
Specifically, if being used for forming nmos device, then as it is shown in figure 9, with grid 45 as shielding layer, The source contact portion 331 of described active layer 30 and drain contact 332 are carried out N-type heavy doping, wherein, The ion mixed in described source contact portion 331 with drain contact 332 is phosphonium ion (P-) or arsenic from Son.
Step 5, as shown in Figure 10 and Figure 12, on described grid 45 and gate insulator 40 deposit interlayer Insulating barrier 50, carries out patterned process to described interlayer insulating film 50, obtains corresponding respectively to described source electrode The first via above contact site 331, drain contact 332, the second via, such as Figure 11 and Figure 13 institute Show, on described interlayer insulating film 50, second metal level be deposited and patterned, obtain respectively with described source electrode The source electrode 61 that contact site 331 and drain contact 332 are connected and drain electrode 62, described source electrode 61, drain electrode 62 respectively by the first via of described interlayer insulating film 50, the second via and described source contact portion 331, Drain contact 332 is connected.
Specifically, if the source contact portion 331 to described active layer 30 enters with drain contact 332 in step 4 Gone p-type heavy doping, then in described step 5, described active layer 35, grid 45, source electrode 61 and leakage Pole 62 collectively forms PMOS device as shown in figure 11.
Specifically, if the source contact portion 331 to described active layer 30 enters with drain contact 332 in step 4 Gone p-type heavy doping, then in described step 5, described active layer 35, grid 45, source electrode 61 and leakage Pole 62 collectively forms nmos device as shown in fig. 13 that.
Specifically, during the material of described the first metal layer and the second metal level is molybdenum, titanium, aluminum and copper The heap stack combination of one or more；Described cushion 20, gate insulator 40 and interlayer insulating film 50 For silicon oxide layer, silicon nitride layer or superposed, by silicon oxide layer, the composite bed constituted with silicon nitride layer.
In sum, the system of a kind of based on crystallization inducing metal technique the LTPS TFT that the present invention provides Making method, first deposition layer of metal inducing layer, deposition of amorphous silicon films in metal induction layer, utilize Metal induction layer carries out crystallization inducing metal to amorphous silicon membrane, during crystallization inducing metal, Metal induction layer induction amorphous silicon membrane bottom-up crystallization formed polysilicon membrane, and metal induction layer to On migrate to the top of polysilicon membrane and formed at the top of polysilicon membrane one layer the thinnest containing a large amount of The metal silicide layer with conduction property of metal ion；Then use intermediate tone mask plate to described many Polycrystal silicon film carries out patterned process and is formed with active layer, makes the metal silicide layer on groove be etched Fall, thus reach to reduce the purpose of the LTPS TFT device leakage current when OFF state, and source contact portion It is retained with the metal silicide layer on drain contact, thus reaches to reduce in LTPS TFT device and have The purpose of the contact impedance of active layer and source-drain electrode.
The above, for the person of ordinary skill of the art, can be according to the technical side of the present invention Other various corresponding changes and deformation are made in case and technology design, and all these change and deformation are all answered Belong to the protection domain of appended claims of the present invention.

Claims (10)

1. the manufacture method of a LTPS TFT based on crystallization inducing metal technique, it is characterised in that Comprise the following steps:
Step 1, offer underlay substrate (10), at the upper buffer layer (20) of underlay substrate (10), Cushion (20) deposits metal induction layer (35)；
Step 2, at the upper deposition of amorphous silicon films (36) of metal induction layer (35), utilize metal induction layer (35) amorphous silicon membrane (36) is carried out crystallization inducing metal, during crystallization inducing metal, The bottom-up crystallization of metal induction layer (35) induction amorphous silicon membrane (36) forms polysilicon membrane (30), metal induction layer (35) migrates upwardly to the top of polysilicon membrane (30) shape in connection Become metal silicide layer (31)；
Step 3, provide a halftoning mask plate (90), use this intermediate tone mask plate (90) to described Polysilicon membrane (30) carries out patterned process, obtains active layer (33), described active layer (33) Including being positioned at source contact portion (331) and the drain contact (332) at two ends and being positioned at described source electrode Groove (333) between contact site (331) and drain contact (332), wherein, described source electrode Contact site (331) is retained with the metal silicide layer (31) on drain contact (332), described Metal silicide layer (31) on groove (333) is etched；
Step 4, on described active layer (35) and cushion (20), deposit gate insulator (40), on described gate insulator (40), the first metal layer is deposited and patterned, obtains corresponding to institute State the grid (45) of groove (333) top；
Step 5, on described grid (45) and gate insulator (40), deposit interlayer insulating film (50), on described interlayer insulating film (50), second metal level is deposited and patterned, obtains source electrode (61) with drain electrode (62).
2. the making side of LTPS TFT based on crystallization inducing metal technique as claimed in claim 1 Method, it is characterised in that described step 4 also includes: with grid (45) as shielding layer, to described active layer (30) source contact portion (331) and drain contact (332) carry out p-type heavy doping；
In described step 5, described active layer (35), grid (45), source electrode (61) and drain electrode (62) PMOS device is collectively formed.
3. the making side of LTPS TFT based on crystallization inducing metal technique as claimed in claim 2 Method, it is characterised in that when carrying out p-type heavy doping in described step 4, to described source contact portion (331) ion that mix middle with drain contact (332) is boron ion or gallium ion.
4. the making side of LTPS TFT based on crystallization inducing metal technique as claimed in claim 1 Method, it is characterised in that described step 4 also includes: with grid (45) as shielding layer, to described active layer (30) source contact portion (331) and drain contact (332) carry out N-type heavy doping；
In described step 5, described active layer (35), grid (45), source electrode (61) and drain electrode (62) nmos device is collectively formed.
5. the making side of LTPS TFT based on crystallization inducing metal technique as claimed in claim 4 Method, it is characterised in that when carrying out N-type heavy doping in described step 4, to described source contact portion (331) ion that mix middle with drain contact (332) is phosphonium ion or arsenic ion.
6. the making side of LTPS TFT based on crystallization inducing metal technique as claimed in claim 1 Method, it is characterised in that the thickness depositing metal induction layer (35) in described step 1 is 5nm-10nm, The material of described metallized metal inducing layer (35) is nickel or aluminum.
7. the making side of LTPS TFT based on crystallization inducing metal technique as claimed in claim 1 Method, it is characterised in that in described step 2, the thickness of deposition of amorphous silicon films (36) is 50nm- 100nm, carries out crystallization inducing metal to amorphous silicon membrane (36) at a temperature of 350 DEG C-400 DEG C.
8. the making side of LTPS TFT based on crystallization inducing metal technique as claimed in claim 1 Method, it is characterised in that use intermediate tone mask plate (90) to described polysilicon membrane in described step 3 (30) concretely comprising the following steps of patterned process is carried out: at described polysilicon membrane (30) one layer of light of upper coating Resistance material (80), utilizes described intermediate tone mask plate (90) to expose this layer of photoresist (80) After light and development, obtain including the first photoresistance pattern and the photoresist layer of the second photoresistance pattern, Qi Zhong The thickness of two photoresistance patterns is less than the thickness of described first photoresistance pattern, with photoresist layer as shielding layer, to institute State polysilicon membrane (30) to be etched, obtain active layer (35), wherein said active layer (35) Source contact portion (331) and drain contact (332) formed corresponding to described first photoresistance pattern, Described groove (333) is formed corresponding to described second photoresistance pattern.
9. the making side of LTPS TFT based on crystallization inducing metal technique as claimed in claim 1 Method, it is characterised in that described step 5 also includes, before depositing second metal layer, exhausted to described interlayer Edge layer (50) carries out patterned process, obtains corresponding respectively to described source contact portion (331), drain electrode First via of contact site (332) top, the second via, described source electrode (61), drain electrode (62) point Tong Guo the first via of described interlayer insulating film (50), the second via and described source contact portion (331), drain contact (332) is connected.
10. the making side of LTPS TFT based on crystallization inducing metal technique as claimed in claim 1 Method, it is characterised in that the material of described the first metal layer and the second metal level be molybdenum, titanium, aluminum and The heap stack combination of one or more in copper；Described cushion (20), gate insulator (40) and Interlayer insulating film (50) is silicon oxide layer, silicon nitride layer or is superposed with silicon nitride layer by silicon oxide layer The composite bed constituted.
CN201610584469.3A 2016-07-21 2016-07-21 Manufacturing method of LTPS TFT based on metal induced crystallization process Pending CN106024639A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610584469.3A CN106024639A (en) 2016-07-21 2016-07-21 Manufacturing method of LTPS TFT based on metal induced crystallization process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610584469.3A CN106024639A (en) 2016-07-21 2016-07-21 Manufacturing method of LTPS TFT based on metal induced crystallization process

Publications (1)

Publication Number Publication Date
CN106024639A true CN106024639A (en) 2016-10-12

Family

ID=57117414

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610584469.3A Pending CN106024639A (en) 2016-07-21 2016-07-21 Manufacturing method of LTPS TFT based on metal induced crystallization process

Country Status (1)

Country Link
CN (1) CN106024639A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107706243A (en) * 2017-09-20 2018-02-16 武汉华星光电半导体显示技术有限公司 Low-temperature polysilicon film transistor and preparation method thereof and array base palte
CN108550583A (en) * 2018-05-09 2018-09-18 京东方科技集团股份有限公司 A kind of production method of display base plate, display device and display base plate
CN108598145A (en) * 2018-06-29 2018-09-28 上海天马微电子有限公司 Organic light-emitting display panel and organic light-emitting display device
CN110036458A (en) * 2019-03-05 2019-07-19 京东方科技集团股份有限公司 Form the method for crystalline semiconductor layer, the method for manufacturing thin film transistor (TFT), thin film transistor (TFT) and display equipment
US10424668B2 (en) 2017-09-20 2019-09-24 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Low temperature polysilicon thin film transistor and fabricating method thereof and array substrate
CN112420520A (en) * 2020-11-23 2021-02-26 山东华芯半导体有限公司 Method for inducing semiconductor oxide crystallization by using metal
CN112563196A (en) * 2020-11-24 2021-03-26 惠科股份有限公司 Manufacturing method of active switch and display panel

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100669499B1 (en) * 2005-12-29 2007-01-16 요업기술원 Crystallization method of amorphous silicon thin film by metal induced lateral crystallization
CN104299891A (en) * 2014-10-20 2015-01-21 京东方科技集团股份有限公司 Preparation method of low-temperature polycrystalline silicon thin film, TFT, array substrate and display device
CN104576753A (en) * 2014-12-29 2015-04-29 昆山国显光电有限公司 Low temperature polycrystalline silicon film transistor and manufacturing method thereof
CN105118777A (en) * 2015-07-01 2015-12-02 深圳市华星光电技术有限公司 Manufacturing method for TFT back board and structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100669499B1 (en) * 2005-12-29 2007-01-16 요업기술원 Crystallization method of amorphous silicon thin film by metal induced lateral crystallization
CN104299891A (en) * 2014-10-20 2015-01-21 京东方科技集团股份有限公司 Preparation method of low-temperature polycrystalline silicon thin film, TFT, array substrate and display device
CN104576753A (en) * 2014-12-29 2015-04-29 昆山国显光电有限公司 Low temperature polycrystalline silicon film transistor and manufacturing method thereof
CN105118777A (en) * 2015-07-01 2015-12-02 深圳市华星光电技术有限公司 Manufacturing method for TFT back board and structure

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107706243B (en) * 2017-09-20 2020-05-05 武汉华星光电半导体显示技术有限公司 Preparation method of low-temperature polycrystalline silicon thin film transistor
WO2019056657A1 (en) * 2017-09-20 2019-03-28 武汉华星光电半导体显示技术有限公司 Low-temperature polycrystalline silicon thin film transistor, preparation method therefor, and array substrate
US10424668B2 (en) 2017-09-20 2019-09-24 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Low temperature polysilicon thin film transistor and fabricating method thereof and array substrate
CN107706243A (en) * 2017-09-20 2018-02-16 武汉华星光电半导体显示技术有限公司 Low-temperature polysilicon film transistor and preparation method thereof and array base palte
CN108550583B (en) * 2018-05-09 2021-03-23 京东方科技集团股份有限公司 Display substrate, display device and manufacturing method of display substrate
US11521989B2 (en) 2018-05-09 2022-12-06 Beijing Boe Technology Development Co., Ltd. Display substrate, display apparatus and manufacturing method of display substrate
CN108550583A (en) * 2018-05-09 2018-09-18 京东方科技集团股份有限公司 A kind of production method of display base plate, display device and display base plate
CN108598145A (en) * 2018-06-29 2018-09-28 上海天马微电子有限公司 Organic light-emitting display panel and organic light-emitting display device
CN108598145B (en) * 2018-06-29 2021-08-31 上海天马微电子有限公司 Organic light-emitting display panel and organic light-emitting display device
CN110036458A (en) * 2019-03-05 2019-07-19 京东方科技集团股份有限公司 Form the method for crystalline semiconductor layer, the method for manufacturing thin film transistor (TFT), thin film transistor (TFT) and display equipment
WO2020177080A1 (en) * 2019-03-05 2020-09-10 Boe Technology Group Co., Ltd. Method of forming crystallized semiconductor layer, method of fabricating thin film transistor, thin film transistor, and display apparatus
CN110036458B (en) * 2019-03-05 2023-05-30 京东方科技集团股份有限公司 Method of forming crystalline semiconductor layer, method of manufacturing thin film transistor, and display device
CN112420520A (en) * 2020-11-23 2021-02-26 山东华芯半导体有限公司 Method for inducing semiconductor oxide crystallization by using metal
CN112563196A (en) * 2020-11-24 2021-03-26 惠科股份有限公司 Manufacturing method of active switch and display panel

Similar Documents

Publication Publication Date Title
CN105097675B (en) Array base palte and preparation method thereof
CN106024639A (en) Manufacturing method of LTPS TFT based on metal induced crystallization process
CN107424957B (en) Manufacturing method of flexible TFT substrate
CN107507841B (en) Array substrate, manufacturing method thereof and display device
CN104332477B (en) Thin film transistor component, array substrate, method for manufacturing array substrate and display device comprising array substrate
CN104538429B (en) The production method and its structure of AMOLED backboard
CN105489552B (en) The production method of LTPS array substrates
US20180197895A1 (en) Tft array substrate, method for manufacturing the same, and display device
CN105702623B (en) The production method of tft array substrate
CN106098628B (en) The production method and TFT backplate of TFT backplate
US20170184892A1 (en) Array substrate, method for manufacturing the same, and display device
CN106531692A (en) Array substrate and preparation method therefor, and display apparatus
CN105097841B (en) The production method and TFT substrate of TFT substrate
CN104681628A (en) Polycrystalline silicon thin film transistor, array substrate, manufacturing methods and display device
CN106910748A (en) A kind of array base palte, display device and preparation method thereof
CN106128944A (en) The manufacture method of metal oxide thin-film transistor array base palte
CN106024633A (en) Preparation methods of thin film transistor and array substrate, array substrate and display device
CN108538860A (en) The production method of top gate type amorphous-silicon TFT substrate
CN106449655A (en) Thin film transistor array substrate and manufacturing method thereof
CN104576399B (en) A kind of thin film transistor (TFT) and its manufacture method
CN106057735A (en) Manufacturing method of TFT backboard and TFT backboard
CN105789117A (en) Manufacturing method of TFT substrate and manufactured TFT substrate
CN106356306A (en) Top gate type thin film transistor and production method thereof
US8975124B2 (en) Thin film transistor, array substrate and preparation method thereof
CN108269856A (en) A kind of oxide semiconductor thin-film transistor and preparation method thereof, array substrate

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20161012