CN106024065A - Shifting register, grid driving circuit, array substrate and display device - Google Patents
Shifting register, grid driving circuit, array substrate and display device Download PDFInfo
- Publication number
- CN106024065A CN106024065A CN201610333143.3A CN201610333143A CN106024065A CN 106024065 A CN106024065 A CN 106024065A CN 201610333143 A CN201610333143 A CN 201610333143A CN 106024065 A CN106024065 A CN 106024065A
- Authority
- CN
- China
- Prior art keywords
- shift register
- switch
- signal
- nodal point
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title abstract description 6
- 238000006073 displacement reaction Methods 0.000 claims description 8
- 230000008054 signal transmission Effects 0.000 claims description 8
- 238000013499 data model Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 5
- 230000005611 electricity Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 244000045947 parasite Species 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Shift Register Type Memory (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The embodiment of the application provides a shift register, a gate driving circuit comprising the shift register, an array substrate comprising the gate driving circuit and a display panel comprising the array substrate, wherein the shift register comprises: the first switch, the second switch, the third switch, the fourth switch, the seventh switch, the first node, the second node and the output signal end, wherein the fourth switch is controlled by the first control signal, and is used for transmitting the second level signal to the second node, and is no longer controlled by the first node, thereby avoiding the mutual control and influence of the first node and the second node, causing poor stability of the shift register, and leading to the problem that the circuit can not work normally, and when the stability of the shift register is improved, the display effect of the display panel is improved.
Description
Technical field
The present invention relates to Display Technique field, more particularly, it relates to a kind of shift register, grid drive
Galvanic electricity road, array base palte and display device.
Background technology
Along with the development of Display Technique, kinds of displays application and give birth to, such as liquid crystal display, organic
Active displays etc., are increasingly becoming the main product showing industry at present.In the display, usually,
Be that pixel cell in display provides and drives signal, such as gate drive signal by drive circuit, be by
Being positioned at the gate driver circuit on display side, the grid for display picture element unit provides driving signal,
To drive corresponding pixel cell to present required display state.
Drive circuit in display is typically made up of shift register, and shift registers at different levels mutually cascade
So that pulse signal to be transferred to pixel cell step by step line by line, shift register is typically by several switch element phases
Electrical connection is formed mutually, during real work, is typically due to the less stable of shift register
And there is the phenomenons such as distortion and the disorder of output waveform, mutually doing between different nodes in shift register
The effect of disturbing and the circuit oscillation that causes are the one of the main reasons of shift register poor stability, therefore, as
What promotes the stability of shift register and is an up the major issue that display display quality is urgently to be resolved hurrily.
Summary of the invention
In view of this, the invention provides a kind of shift register, gate driver circuit, array base palte and
Display device, to improve shift register and to include the gate driver circuit of this shift register, array
The stability of substrate and display device etc..
For achieving the above object, the present invention provides following technical scheme:
A kind of shift register, including the first switch to the 7th switch, primary nodal point and secondary nodal point, with
And output signal end；
Described first switch is controlled by the first input signal, for by the first level signal transmission to the most described the
One node；
Described second switch is controlled by the second input signal, for by second electrical level signal transmission to the most described the
One node；
Described 3rd switch is by the Automatic level control of described secondary nodal point, for being passed by described second electrical level signal
Transport to described primary nodal point；
Described 4th switch is controlled by the first control signal, for transmitting described second electrical level signal to institute
State secondary nodal point；
Described 5th switch is by the Automatic level control of described primary nodal point, for by the first clock signal transmission extremely
Described output signal end；
Described 6th switch is by the Automatic level control of described secondary nodal point, for being passed by described second electrical level signal
Transport to described output signal end；
Described 7th switch is controlled by second clock signal, for transmitting described second electrical level signal to institute
State output signal end；
Wherein, described shift register also includes the first control signal end, described first control signal end to
The control end of described 4th switch provides described first control signal.
A kind of gate driver circuit, described gate driver circuit includes n level shift register, described n level
Shift register includes m shift register group, the shift register in each described shift register group
Electrically connecting in cascaded fashion, described shift register is above-mentioned shift register, and m, n are positive integer, and
M ＞ 1, n ＞ 1.
A kind of array base palte, insulate with described gate line including a plurality of gate line intersect a plurality of data lines,
Enclosed by described gate line and described data wire and form the pel array being arranged in array and be arranged on described battle array
The above-mentioned gate driver circuit of row substrate at least side, the outfan of each described shift register and one
Described gate line is connected.
A kind of display device, including above-mentioned array base palte.
Compared with prior art, technical scheme provided by the present invention has the advantage that
Shift register provided by the present invention, including: first switch to the 7th switch, primary nodal point and
Secondary nodal point, output signal end and the first control signal end, wherein, described 4th switch is controlled by first
The first control signal that signal end provides controls, for by described second electrical level signal transmission extremely described second
Node, and described first control signal end is not by the voltage influence of described primary nodal point, so that described
Secondary nodal point is no longer controlled by described primary nodal point, thus avoids primary nodal point and the mutual phase control of secondary nodal point
And impact, it is to avoid the distortion of shift register output waveform or disorderly phenomenon, improve shift register
Stability.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to reality
Execute the required accompanying drawing used in example or description of the prior art to be briefly described, it should be apparent that below,
Accompanying drawing in description is only embodiments of the invention, for those of ordinary skill in the art, not
On the premise of paying creative work, it is also possible to obtain other accompanying drawing according to the accompanying drawing provided.
The structural representation of the shift register that Fig. 1 is provided by one embodiment of the invention；
The structural representation of the shift register that Fig. 2 is provided by another embodiment of the present invention；
The structural representation of the gate driver circuit that Fig. 3 is provided by one embodiment of the invention；
Fig. 4 is the structural representation of the i-stage shift register of gate driver circuit in Fig. 3；
The structural representation of the array base palte that Fig. 5 is provided by one embodiment of the invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the present invention, and
It is not all, of embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art are not doing
Go out the every other embodiment obtained under creative work premise, broadly fall into the scope of protection of the invention.
The most as described in the background section, the less stable of shift register in prior art, thus lead
Cause to include that the stability of the gate driver circuit of this shift register and display device is the most relatively poor.
Usually, shift register comprise so that the important node of shift register institute output waveform change,
As when output waveform is a high level pulse, shift register having so that output waveform presents height
The pull-up node of level and make it reply low level pull-down node, when pull-up node is mutual with pull-down node
When controlling and interfere, being easily generated circuit oscillation problem, the waveform that shift register is exported easily is sent out
The raw phenomenon such as distortion or disorder, so that the less stable of shift register, have impact on display
Display effect.
Embodiments provide a kind of shift register, as it is shown in figure 1, Fig. 1 is one reality of the present invention
Executing the structural representation of the shift register that example is provided, wherein, this shift register includes: first opens
Close to the 7th switch T0-T6, primary nodal point PU and secondary nodal point PD, and output signal end Gn；First
Switch T0 is controlled by the first input signal SET, for transmitting the first level signal VGH to primary nodal point
PU；Second switch T1 is controlled by the second input signal Gn+1, for second electrical level being believed No. VGL transmission extremely
Primary nodal point PU；3rd switch T2 is by the Automatic level control of secondary nodal point PD, for by second electrical level signal
VGL transmits to primary nodal point PU；4th switch T3 is controlled by the first control signal, for by second electrical level
Signal VGL transmits to secondary nodal point PD；5th switch T4 is by the Automatic level control of primary nodal point PU, and being used for will
First clock signal CKB is transmitted to output signal end Gn；6th switch T5 is by the level control of secondary nodal point PD
System, for by second electrical level signal VGL transmission to output signal end Gn；7th switch T6 is by second clock
Signal CK controls, for by second electrical level signal VGL transmission to output signal end Gn；Wherein, displacement is posted
Storage also includes the first control signal end 10, and the first control signal end 10 carries to the control end of the 4th switch T3
For the first control signal.
In the shift register that the embodiment of the present invention is provided, the 4th switch is provided by the first control signal end
First control signal control, for by second electrical level signal transmit to secondary nodal point, and first control letter
Number end is not by the voltage influence of primary nodal point, so that secondary nodal point is no longer by primary nodal point control, from
And avoid when primary nodal point goes wrong, and the problem that secondary nodal point also cannot normally work, improve
The stability of shift register.
In one embodiment of the invention, as in figure 2 it is shown, Fig. 2 is carried by another embodiment of the present invention
The structural representation of the shift register of confession, wherein, shift register also includes control signal source 20, control
Signal source 20 processed electrically connects with the first control signal end 10, provides the first control for the first control signal end 10
Signal, is transferred to the 4th switch T3 by the first control signal end 10 by the first control signal, controls the 4th
The conducting of switch T3 and cut-off.But this is not limited by the present invention, in other embodiments of the invention,
When shift register is applied to gate driver circuit by the way of cascade, the first control signal end is all right
Electrically connect with the outfan of other shift registers, the output signal of other shift registers be controlled,
The circuit structure of the gate driver circuit to simplify shift register and include this shift register, it is concrete
Electrical connection is described below, repeats no more here.
In an alternate embodiment of the present invention where, the first level signal VGH is high level signal, second
Level signal VGL is low level signal, and primary nodal point PU is pull-up node, and secondary nodal point PD is drop-down joint
Point, second clock signal CK is the reverse signal of the first clock signal CKB.But this is not done by the present invention
Limit, specifically depend on the circumstances.
In one embodiment of the invention, shift register also includes: the first input signal end, second
Input signal end, the first clock signal terminal, second clock signal end, the first level signal end and the second electricity
Flat signal end；Wherein, the first input signal end is for receiving the first input signal SET, the second input signal
End is for receiving the second input signal Gn+1, and the first clock signal terminal is used for receiving the first clock signal CKB,
Second clock signal end is used for receiving second clock signal CK, and the first level signal end is for receiving the first electricity
Ordinary mail VGH, second electrical level signal end is used for receiving second electrical level signal VGL, and, the first switch T0
Control end and the first input signal end connect, the first end and the first level signal end company of the first switch T0
Connecing, second end of the first switch T0 is connected with primary nodal point PU；The control end of second switch T1 and second defeated
Entering signal end to connect, first end of second switch T1 is connected with second electrical level signal end, second switch T1's
Second end is connected with primary nodal point PU；The control end of the 3rd switch T2 is connected with secondary nodal point PD, and the 3rd opens
The first end closing T2 is connected with second electrical level signal end, and second end of the 3rd switch T2 is with primary nodal point PU even
Connect；Control end and the first control signal end of the 4th switch T3 connect, and the 4th switchs first end and the of T3
Two level signal ends connect, and second end of the 4th switch T3 is connected with secondary nodal point PD；5th switch T4's
Controlling end to be connected with primary nodal point PU, the first end and first clock signal input terminal of the 5th switch T4 connect,
Second end of the 5th switch T4 is connected with output signal end；The control end of the 6th switch T5 and secondary nodal point PD
Connect, the 6th switch T5 the first end is connected with second electrical level signal end, the 6th switch T5 the second end and
Output signal end connects；The control end of the 7th switch T6 is connected with second clock signal end, the 7th switch T6
The first end be connected with second electrical level signal end, the 7th switch T6 the second end be connected with output signal end.
It should be noted that in the above-described embodiments, the signal source of the first input signal end can be to touch
The triggering signal STP of signalling source output, it is also possible to for being positioned at the upper level of same group with this shift register
Or the output signal of next stage shift register, in like manner, the signal source of the second input signal end can also
For being positioned at next stage or the output signal of upper level shift register of same group with this shift register, this
This is not limited by invention, specifically depending on including the scan mode of the drive circuit of this shift register and being somebody's turn to do
Depending on shift register electrically connecting position in this drive circuit.
In one embodiment of the invention, shift register also includes: the first electric capacity C1 and the second electric capacity
C2, wherein, first end of the first electric capacity C1 and the first clock signal terminal connect, the of the first electric capacity C1
Two ends are connected with secondary nodal point PD；First end of the second electric capacity C2 is connected with primary nodal point PU, and second
Second end of electric capacity C2 is connected with output signal end.In the present embodiment, the first electric capacity C1 is for the
During four switch T3 cut-offs, the first clock signal is coupled to secondary nodal point PD so that secondary nodal point PD
Change along with the change of the first clock signal；Second electric capacity C2 is used for when the 5th switch T4 cut-off,
By output signal end export signal coupled to primary nodal point PU so that the signal of primary nodal point PU along with
The change of signal of output signal end output and change.
In one embodiment of the invention, shift register also includes: the 8th switch T7 and the 9th switch
T8, wherein, the 8th switch T7 is controlled by reset signal Reset, for by second electrical level signal VGL
Transmit to primary nodal point PU；9th switch T8 is controlled by reset signal Reset, for being believed by second electrical level
Number VGL transmits to outfan.
Optionally, in one particular embodiment of the present invention, shift register also includes: reset signal
End, is used for receiving reset signal Reset；The control end of the 8th switch T7 is connected with reset signal end, the
First end of eight switch T7 is connected with second electrical level signal end, second end of the 8th switch T7 and first segment
Point PU connects；The control end of the 9th switch T8 is connected with reset signal end, the first of the 9th switch T8
End is connected with second electrical level signal end, and second end of the 9th switch T8 is connected with output signal end.Need
Bright, in embodiments of the present invention, the input signal of reset signal end can derive from reset signal source,
Can also derive from and be positioned at the upper level of same group or the defeated of next stage shift register with this shift register
Going out the signal of signal end output, this is not limited by the present invention, specifically depends on the circumstances.
In an alternate embodiment of the present invention where, the first switch T0 to the 9th switch T8 is PMOS crystal
Pipe or nmos pass transistor, the first switch is the grid of transistor to the end that controls of the 9th switch T0-T8, the
One end and the second end are respectively source electrode and the drain electrode of transistor.
Understanding from the above mentioned, in the shift register that the embodiment of the present invention is provided, the 4th switch is by first
The first control signal that control signal end provides controls, for second electrical level signal is transmitted to secondary nodal point,
And the first control signal end is not by the voltage influence of primary nodal point, so that secondary nodal point is no longer by first
Node control, thus avoid when primary nodal point goes wrong, secondary nodal point also cannot normally work
Problem, improves the stability of shift register.
Accordingly, the embodiment of the present invention additionally provides a kind of gate driver circuit, as it is shown on figure 3, Fig. 3
By the electrical block diagram of the gate driver circuit that one embodiment of the invention is provided, wherein, grid
Drive circuit includes: n level shift register, and n level shift register includes m shift register group, often
Shift register in one shift register group electrically connects in cascaded fashion, and shift register is any of the above-described
The shift register that embodiment is provided, m, n are positive integer, and m ＞ 1, n ＞ 1.Concrete,
In the embodiment of the present invention, when gate driver circuit forward scan, it is positioned in same shift register group
First input signal of one-level shift register controls end and electrically connects with the extraneous signal STP that triggers, and remaining is each
The signal output part of shift register is electrically connected with the first input signal end of the shift register of its next stage
Connect；When gate driver circuit reverse scan, it is positioned at afterbody displacement in same shift register group and posts
First input signal end of storage electrically connects with the extraneous signal STP that triggers, the letter of remaining each shift register
Number outfan electrically connects with the first input signal end of the shift register of its upper level.
In one embodiment of the invention, the first control signal end L3 in each shift register is electrically connected
Connect a control signal source, control signal source provide the first control signal；Another reality in the present invention
Execute in example, all shift registers or each shifting of being positioned in same shift register group in n level shift register
First control signal end L3 of bit register electrically connects same control signal source, control signal source be respectively
It provides the first corresponding control signal end to provide the first control signal, to simplify the knot of gate driver circuit
Structure；In yet another embodiment of the present invention, gate driver circuit is not provided with control signal source, each
The first control signal end in shift register is electrically connected to other shift registers, by other shift LDs
Device provides the first control signal.
In the gate driver circuit that the embodiment of the present invention is provided, the 4th switch of each shift register is by the
The first control signal that one control signal end provides controls, for transmitting second electrical level signal to second section
Point, and the first control signal end is not by the voltage influence of primary nodal point so that secondary nodal point no longer by
Primary nodal point controls, thus avoids when primary nodal point goes wrong, and secondary nodal point also cannot normal work
The problem made, improves the stability of shift register, and then improves the stability of gate driver circuit.
Below with the first control when being not provided with control signal source in gate driver circuit, in each shift register
Signal end is electrically connected to other shift registers, other shift registers as a example by providing the first control signal,
The gate driver circuit being provided the embodiment of the present invention illustrates.
In one embodiment of the invention, when the scan mode of gate driver circuit is forward scan,
As it is shown on figure 3, the first control signal end of i-stage shift register receives the i-th-1 grade shift register
Output signal, i-stage shift register and the i-th-1 grade shift register are belonging respectively to two shift registers
Group, it addition, reference Fig. 4, Fig. 4 are the structures of the i-stage shift register of gate driver circuit in Fig. 3
Schematic diagram, wherein, the first control signal end of i-stage shift register receives the i-th-1 grade shift register
Output signal Gn-1, for pull-down node PD is controlled；In an alternative embodiment of the invention
In, when the scan mode of gate driver circuit is reverse scan, the first control of i-stage shift register
Signal end receives the output signal of i+1 level shift register, and i-stage shift register moves with i+1 level
Bit register is belonging respectively to two shift register group.Although it should be noted that the embodiment of the present invention
With n level shift register, accompanying drawing includes that 2 shift register group are illustrated, but the present invention is to this
Do not limit, when 3,4 or more level shift register group, above-mentioned shift registers at different levels
Electrical connection equally applicable.
In yet another embodiment of the present invention, 3 shift register group are included when n level shift register
Time, when the scan mode of gate driver circuit is forward scan, the first control of i-stage shift register
Signal end receives i-th-1 or the output signal of the i-th-2 grades shift registers, i-stage shift register and the
I-1 level shift register, the i-th-2 grades shift registers are belonging respectively to different shift register group；At this
In another embodiment of invention, when the scan mode of gate driver circuit is reverse scan, i-stage is moved
First control signal end of bit register receives i+1 or the output signal of the i-th+2 grades shift registers, the
I level shift register is belonging respectively to different shifting from i+1 level shift register, the i-th+2 grades shift registers
Bit register group.
In like manner, when n level shift register includes m shift register group, when gate driver circuit
When scan mode is forward scan, the first control signal end of i-stage shift register receives the i-th-p level and moves
The output signal of bit register, i-stage shift register and the i-th-p level shift register are belonging respectively to different
Shift register group；In another embodiment of the present invention, when the scan mode of gate driver circuit
During for reverse scan, the first control signal end of i-stage shift register receives the i-th+p level shift register
Output signal, i-stage shift register and the i-th+p level shift register are belonging respectively to different shift LD
Device group.Wherein, p can be [1, m) in arbitrary positive integer, including endpoint value 1, but do not include end
Point value m.
It should be noted that in any of the above-described embodiment, be positioned at the different group shift register with a line
Trigger the signal delay having Preset Time between signal, wherein, Preset Time is more than zero, less than one
The width of pulse.
In one embodiment of the invention, gate driver circuit also includes: input signal cable, clock are believed
Number line and reseting signal line, wherein, the first order displacement of each shift register group of input signal alignment
Depositor provides and triggers signal STP, the of remaining shift register at different levels in each shift register group
One input signal is the output signal of previous stage shift register, and/or, each displacement of input signal alignment
The afterbody shift register of Parasites Fauna provides and triggers signal STP, in each shift register group
The output signal that second input signal is rear stage shift register of remaining shift register at different levels；Time each
Shift register in each shift register group of clock signal alignment provides the first clock signal CKB and when second
Clock signal CK；Shift register in each shift register group of reset signal alignment provides reset signal
Reset, makes shift register be in reset state.Optionally, in one embodiment of the invention, when
The first order shift register of each each shift register group of input signal alignment provides the first input signal,
First input signal of remaining shift register at different levels in each shift register group is that previous stage displacement is posted
During the output signal of storage, the signal of the reseting signal line that each shift register is corresponding derives from and is positioned at it
The signal of the output signal end output of the next stage shift register of same shift register group；When each input
The afterbody shift register of each shift register group of signal alignment provides the second input signal, each
Second input signal of the shift register at different levels of remaining in shift register group is rear stage shift register
Output signal time, the signal of the reseting signal line that each shift register is corresponding derive from be positioned at it same
The signal of the output signal end output of the upper level shift register of shift register group, drives simplifying grid
The circuit structure on galvanic electricity road, but this is not limited by the present invention, specifically depends on the circumstances.
Additionally, the embodiment of the present invention additionally provides a kind of array base palte and includes the display surface of this array base palte
Plate.As it is shown in figure 5, the structural representation of array base palte that Fig. 5 is provided by one embodiment of the invention,
This array base palte includes: a plurality of gate lines G ate and gate lines G ate insulate intersect a plurality of data lines S,
Enclosed by gate lines G ate and data wire S and form the pel array 100 being arranged in array and be arranged on array
The gate driver circuit 200 that any of the above-described embodiment of substrate at least side is provided, each shift register
The outfan of (not shown) and a gate line are connected, and the quantity of gate line shown in figure is only shown
Example, particular number, depending on particular situation, does not repeats them here.
In sum, the embodiment of the present invention is provided shift register, the grid of this shift register are included
Pole drive circuit, include the array base palte of this gate driver circuit and include the display surface of this array base palte
Plate, including: the first switch is to the 7th switch, primary nodal point and secondary nodal point, and output signal end,
Wherein, the 4th switch is controlled by the first control signal, for second electrical level signal is transmitted to secondary nodal point,
And no longer by primary nodal point control, thus avoid when primary nodal point goes wrong, secondary nodal point also without
The problem that method normally works, improves the stability of shift register, and then improves and include that this displacement is posted
The gate driver circuit of storage and include the array base palte of this gate driver circuit, include this array base palte
The stability of display device.
In this specification, each embodiment uses the mode gone forward one by one to describe, and each embodiment stresses
Being the difference with other embodiments, between each embodiment, identical similar portion sees mutually.
For device disclosed in embodiment, owing to it corresponds to the method disclosed in Example, so describing
Fairly simple, relevant part sees method part and illustrates.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses
The present invention.Multiple amendment to these embodiments will be aobvious and easy for those skilled in the art
See, generic principles defined herein can without departing from the spirit or scope of the present invention,
Realize in other embodiments.Therefore, the present invention is not intended to be limited to the embodiments shown herein,
And it is to fit to the widest scope consistent with principles disclosed herein and features of novelty.
Claims (13)
1. a shift register, it is characterised in that include that the first switch is to the 7th switch, primary nodal point
And secondary nodal point, and output signal end；
Described first switch is controlled by the first input signal, for by the first level signal transmission to the most described the
One node；
Described second switch is controlled by the second input signal, for by second electrical level signal transmission to the most described the
One node；
Described 3rd switch is by the Automatic level control of described secondary nodal point, for being passed by described second electrical level signal
Transport to described primary nodal point；
Described 4th switch is controlled by the first control signal, for transmitting described second electrical level signal to institute
State secondary nodal point；
Described 5th switch is by the Automatic level control of described primary nodal point, for by the first clock signal transmission extremely
Described output signal end；
Described 6th switch is by the Automatic level control of described secondary nodal point, for being passed by described second electrical level signal
Transport to described output signal end；
Described 7th switch is controlled by second clock signal, for transmitting described second electrical level signal to institute
State output signal end；
Wherein, described shift register also includes the first control signal end, described first control signal end to
The control end of described 4th switch provides described first control signal.
Shift register the most according to claim 1, it is characterised in that described first level signal
For high level signal, described second electrical level signal is low level signal, and described primary nodal point is pull-up node,
Described secondary nodal point is pull-down node, and described second clock signal is the reverse letter of described first clock signal
Number.
Shift register the most according to claim 1, it is characterised in that also include the first input letter
Number end, the second input signal end, the first clock signal terminal, second clock signal end, the first level signal
End and second electrical level signal end；
The control end of described first switch is connected with described first input signal end, described first switch the
One end is connected with described first level signal end, and the second end of described first switch is with described primary nodal point even
Connect；
The control end of described second switch is connected with described second input signal end, the of described second switch
One end is connected with described second electrical level signal end, and the second end of described second switch is with described primary nodal point even
Connect；
Described 3rd switch control end is connected with described secondary nodal point, described 3rd switch the first end and
Described second electrical level signal end connects, and the second end of described 3rd switch is connected with described primary nodal point；
The control end of described 4th switch is connected with described first control signal end, the described 4th switch the
One end is connected with described second electrical level signal end, and the second end of described 4th switch is with described secondary nodal point even
Connect；
Described 5th switch control end is connected with described primary nodal point, described 5th switch the first end and
Described first clock signal terminal connects, and the second end of described 5th switch is connected with described output signal end；
Described 6th switch control end is connected with described secondary nodal point, described 6th switch the first end and
Described second electrical level signal end connects, and the second end of described 6th switch is connected with described output signal end；
The control end of described 7th switch is connected with described second clock signal end, the described 7th switch the
One end is connected with described second electrical level signal end, the second end of described 7th switch and described output signal end
Connect.
Shift register the most according to claim 3, it is characterised in that also include the first electric capacity and
Second electric capacity；
First end of described first electric capacity is connected with described first clock signal terminal, the of described first electric capacity
Two ends are connected with described secondary nodal point；
First end of described second electric capacity is connected with described primary nodal point, the second end of described second electric capacity with
Described output signal end connects.
5. according to the shift register described in any one of Claims 1 to 4, it is characterised in that also include
Eight switches and the 9th switch；
Described 8th switch is by reset signal control, for by described second electrical level signal transmission to the most described the
One node；
Described 9th switch is controlled by described reset signal, for transmitting described second electrical level signal to institute
State outfan.
Shift register the most according to claim 5, it is characterised in that also include reset signal end；
The control end of described 8th switch is connected with described reset signal end, the first end of described 8th switch
Being connected with described second electrical level signal end, the second end of described 8th switch is connected with described primary nodal point；
The control end of described 9th switch is connected with described reset signal end, the first end of described 9th switch
Being connected with described second electrical level signal end, the second end of described 9th switch is connected with described output signal end.
Shift register the most according to claim 6, it is characterised in that described first switch is to the
Nine switches are PMOS transistor or nmos pass transistor, the described control of described first switch to the 9th switch
End processed is the grid of transistor, and described first end and described second end are respectively source electrode and the drain electrode of transistor.
8. a gate driver circuit, it is characterised in that described gate driver circuit includes that the displacement of n level is posted
Storage, described n level shift register includes m shift register group, each described shift register group
In shift register electrically connect in cascaded fashion, described shift register is claim 1-7 any one
Described shift register, m, n are positive integer, and m ＞ 1, n ＞ 1.
Gate driver circuit the most according to claim 8, it is characterised in that described i-stage shifts
The output signal of the described first control signal end reception i-th-p level shift register of depositor, described i-th
Level shift register is belonging respectively to different shift register group from described i-th-p level shift register；
Or, the described first control signal end of described i-stage shift register receives the i-th+p level displacement and posts
The output signal of storage, described i-stage shift register is belonging respectively to described i-th+p level shift register
Different shift register group；Wherein, p can be [1, m) in arbitrary positive integer, including endpoint value 1,
But do not include endpoint value m.
Gate driver circuit the most according to claim 9, it is characterised in that i-stage shift LD
The described first control signal end of device receives the output signal of the i-th-1 grade shift register, and described i-stage is moved
Bit register is belonging respectively to two different shift register group from described the i-th-1 grade shift register；
Or, the described first control signal end of i-stage shift register receives i+1 level shift register
Output signal, shift register described in described i-stage is belonging respectively to described i+1 level shift register
Two different shift register group.
11. gate driver circuits according to claim 8, it is characterised in that described raster data model
Circuit also includes input signal cable, clock cable and reseting signal line, wherein,
The first order shift register of each each described shift register group of described input signal alignment provides the
One input signal, the first input letter of remaining shift register at different levels in each described shift register group
Number it is the output signal of previous stage shift register, and/or, each each described shifting of described input signal alignment
The afterbody shift register of bit register group provides the second input signal, each described shift register
The output that second input signal the is rear stage shift register letter of the shift register at different levels of remaining in group
Number；
Shift register in each each described shift register group of described clock signal alignment provides clock letter
Number；
Shift register in each described shift register group of described reset signal alignment provides reset signal,
Described shift register is made to be in reset state.
12. 1 kinds of array base paltes, it is characterised in that include a plurality of gate line and the insulation of described gate line
The a plurality of data lines that intersects, described gate line and described data wire enclose and form the pixel being arranged in array
Array and the grid as described in any one of claim 8 to 11 being arranged on described array base palte at least side
Drive circuit, outfan and a described gate line of each described shift register are connected.
13. 1 kinds of display devices, it is characterised in that include the array base palte described in claim 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610333143.3A CN106024065B (en) | 2016-05-18 | 2016-05-18 | Shifting register, grid driving circuit, array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610333143.3A CN106024065B (en) | 2016-05-18 | 2016-05-18 | Shifting register, grid driving circuit, array substrate and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106024065A true CN106024065A (en) | 2016-10-12 |
| CN106024065B CN106024065B (en) | 2019-12-17 |
Family
ID=57098608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610333143.3A Active CN106024065B (en) | 2016-05-18 | 2016-05-18 | Shifting register, grid driving circuit, array substrate and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106024065B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107403609A (en) * | 2017-09-04 | 2017-11-28 | 上海天马微电子有限公司 | Shift register and control method thereof, grid drive circuit and display device |
| WO2020097816A1 (en) * | 2018-11-14 | 2020-05-22 | 京东方科技集团股份有限公司 | Shift register unit, drive method, gate drive circuit, and display device |
| CN111599301A (en) * | 2020-06-30 | 2020-08-28 | 厦门天马微电子有限公司 | Shift register and display device |
| CN112951146A (en) * | 2021-04-25 | 2021-06-11 | 厦门天马微电子有限公司 | Shift register, driving method, scanning driving circuit, display panel and device |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187037A (en) * | 2011-12-29 | 2013-07-03 | 上海天马微电子有限公司 | Amorphous silicon grid electrode driving circuit |
| CN103985363A (en) * | 2013-12-05 | 2014-08-13 | 上海中航光电子有限公司 | Grid driving circuit, TTF array substrate, display panel and display apparatus |
| CN104361852A (en) * | 2014-11-28 | 2015-02-18 | 上海中航光电子有限公司 | Shifting register, gate drive circuit and display device |
| CN104575419A (en) * | 2014-12-04 | 2015-04-29 | 上海天马微电子有限公司 | Shift register and driving method thereof |
| CN104575430A (en) * | 2015-02-02 | 2015-04-29 | 京东方科技集团股份有限公司 | Shifting register unit, drive method thereof, gate drive circuit and display device |
| CN104867439A (en) * | 2015-06-24 | 2015-08-26 | 合肥京东方光电科技有限公司 | Shift register unit and driving method thereof, gate drive circuit and display device |
| CN105185339A (en) * | 2015-10-08 | 2015-12-23 | 京东方科技集团股份有限公司 | Shift register unit, grid line drive unit and drive method |
| CN105280134A (en) * | 2015-07-02 | 2016-01-27 | 友达光电股份有限公司 | Shift register circuit and operation method thereof |
| CN105336300A (en) * | 2015-12-04 | 2016-02-17 | 昆山龙腾光电有限公司 | Shift register, grid drive circuit and display device |
| CN106935168A (en) * | 2015-12-31 | 2017-07-07 | 瀚宇彩晶股份有限公司 | Shift register and display device |
-
2016
- 2016-05-18 CN CN201610333143.3A patent/CN106024065B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187037A (en) * | 2011-12-29 | 2013-07-03 | 上海天马微电子有限公司 | Amorphous silicon grid electrode driving circuit |
| CN103985363A (en) * | 2013-12-05 | 2014-08-13 | 上海中航光电子有限公司 | Grid driving circuit, TTF array substrate, display panel and display apparatus |
| CN104361852A (en) * | 2014-11-28 | 2015-02-18 | 上海中航光电子有限公司 | Shifting register, gate drive circuit and display device |
| CN104575419A (en) * | 2014-12-04 | 2015-04-29 | 上海天马微电子有限公司 | Shift register and driving method thereof |
| CN104575430A (en) * | 2015-02-02 | 2015-04-29 | 京东方科技集团股份有限公司 | Shifting register unit, drive method thereof, gate drive circuit and display device |
| CN104867439A (en) * | 2015-06-24 | 2015-08-26 | 合肥京东方光电科技有限公司 | Shift register unit and driving method thereof, gate drive circuit and display device |
| CN105280134A (en) * | 2015-07-02 | 2016-01-27 | 友达光电股份有限公司 | Shift register circuit and operation method thereof |
| CN105185339A (en) * | 2015-10-08 | 2015-12-23 | 京东方科技集团股份有限公司 | Shift register unit, grid line drive unit and drive method |
| CN105336300A (en) * | 2015-12-04 | 2016-02-17 | 昆山龙腾光电有限公司 | Shift register, grid drive circuit and display device |
| CN106935168A (en) * | 2015-12-31 | 2017-07-07 | 瀚宇彩晶股份有限公司 | Shift register and display device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107403609A (en) * | 2017-09-04 | 2017-11-28 | 上海天马微电子有限公司 | Shift register and control method thereof, grid drive circuit and display device |
| WO2020097816A1 (en) * | 2018-11-14 | 2020-05-22 | 京东方科技集团股份有限公司 | Shift register unit, drive method, gate drive circuit, and display device |
| US10971102B2 (en) | 2018-11-14 | 2021-04-06 | Hefei Boe Optoelectronics Technology Co., Ltd. | Shift register unit and driving method, gate driving circuit, and display device |
| CN111599301A (en) * | 2020-06-30 | 2020-08-28 | 厦门天马微电子有限公司 | Shift register and display device |
| CN112951146A (en) * | 2021-04-25 | 2021-06-11 | 厦门天马微电子有限公司 | Shift register, driving method, scanning driving circuit, display panel and device |
| CN112951146B (en) * | 2021-04-25 | 2024-03-15 | 厦门天马微电子有限公司 | Shift register, driving method, scanning driving circuit, display panel and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106024065B (en) | 2019-12-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104795041B (en) | A kind of driving method of array base palte, array base palte, display panel and display device | |
| US9576678B2 (en) | Shift register group and method for driving the same | |
| CN103943054A (en) | Grid driving circuit, TFT array substrate, display panel and display device | |
| CN106024065A (en) | Shifting register, grid driving circuit, array substrate and display device | |
| CN104485065A (en) | Shifting register, driving method and gate driving circuit | |
| CN104575353A (en) | Drive circuit, array substrate and display device | |
| CN101025906B (en) | Display device and method of driving the same | |
| CN104808862A (en) | Array substrate, touch display panel and driving method for array substrate | |
| CN104808406A (en) | Substrate and liquid crystal display device thereof | |
| CN109473069A (en) | Gate driving circuit and display panel | |
| US20180158395A1 (en) | Display panel | |
| CN105185325A (en) | Liquid crystal display driving system and driving method | |
| CN105243995A (en) | Shifting register and driving method thereof, gate drive circuit and relevant devices of shifting register | |
| CN104916249A (en) | Drive circuit used for display panel, and display device | |
| CN108877634A (en) | Synchronous controller, display device and control method thereof | |
| CN106898292A (en) | Scan drive circuit and its driving method, array base palte and display device | |
| CN104464597A (en) | Multi-path selection circuit and display device | |
| CN106782663A (en) | A kind of shift register and gate driving circuit | |
| CN104517556A (en) | Shift register circuit and gate driving circuit comprising same | |
| CN106373538B (en) | Shifting register and driving method thereof, grid driving circuit and array substrate | |
| KR20160004480A (en) | Display panel | |
| CN106448532A (en) | Shift register, drive circuit and display panel | |
| CN103592800A (en) | Liquid crystal display panel and liquid crystal display device | |
| CN104880875A (en) | Array substrate and liquid-crystal display panel | |
| CN105654886A (en) | Grid drive circuit, repairing method thereof and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |