CN106023867B - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN106023867B CN106023867B CN201610617410.XA CN201610617410A CN106023867B CN 106023867 B CN106023867 B CN 106023867B CN 201610617410 A CN201610617410 A CN 201610617410A CN 106023867 B CN106023867 B CN 106023867B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The invention provides an array substrate and a display panel, which comprise a display area and a non-display area, wherein the display area comprises a plurality of gate lines, a plurality of data lines and a plurality of color resistors, the plurality of gate lines and the plurality of data lines are insulated and crossed to define a plurality of sub-pixel areas, and the color resistors are arranged corresponding to the sub-pixel areas; the non-display area comprises a gate driving circuit, the gate driving circuit comprises sub-gate driving circuits, each sub-gate driving circuit is connected with a gate line, and at least one gate line is connected with one sub-gate driving circuit; the length of the sub-gate driving circuit in the extending direction of the data line is greater than or equal to 1.5 times of the length of the sub-pixel area in the extending direction of the data line. The number of the sub-gate driving circuits is small, the length of the sub-gate driving circuit in the extending direction of the data line can be larger than or equal to 1.5 times of the length of the sub-pixel region in the extending direction of the data line, and the AOI detection efficiency of the gate driving circuit can be improved.
Description
Technical Field
The invention relates to the technical field of display equipment, in particular to an array substrate and a display panel.
Background
As shown in fig. 1, fig. 1 is a schematic top view of a conventional array substrate, which includes a plurality of gate lines 10 in a display area, a plurality of data lines 11, a plurality of sub-pixel regions 12 defined by the gate lines 10 and the data lines 11 crossing each other in an insulating manner, and a gate driving circuit 13 and a data driving circuit 14 in a non-display area. The array substrate further comprises a plurality of color resistors 15 located in the display area, and each color resistor 15 is arranged corresponding to at least one sub-pixel area 12. The gate driving circuit 13 includes a plurality of sub-gate driving circuits 130, each gate line 10 is connected to two sub-gate driving circuits 130, the two sub-gate driving circuits 130 are respectively located at two opposite sides of the array substrate, and the length L of each sub-gate driving circuit 130 in the extending direction (X direction shown by arrow in fig. 1) of the data line 11 is longer than the length L of each sub-gate driving circuit 1301Is equal to the length L of one sub-pixel region 12 in the extending direction of the data line 112。
In the manufacturing process of the array substrate, because the antistatic level in the production line is poor, after the gate driving circuit 13 is manufactured, the gate driving circuit 13 needs to be subjected to AOI (Automatic optical Inspection) detection to detect whether there are common defects such as short circuit or open circuit in the gate driving circuit 13. However, the AOI detection efficiency of the gate driving circuit 13 of the array substrate having the color resists 15 is lower than that of the array substrate having no color resists.
Disclosure of Invention
In view of the above, the present invention provides an array substrate and a display panel to solve the problem of low AOI detection efficiency of a gate driving circuit of the array substrate in the prior art.
In order to achieve the purpose, the invention provides the following technical scheme:
an array substrate comprises a display area and a non-display area, wherein the display area comprises a plurality of gate lines, a plurality of data lines and a plurality of color resistors, the plurality of gate lines and the plurality of data lines are insulated and crossed to define a plurality of sub-pixel areas, and the color resistors are arranged corresponding to the sub-pixel areas;
the non-display area comprises a gate driving circuit, the gate driving circuit comprises a plurality of sub-gate driving circuits, each sub-gate driving circuit is connected with the gate line, and at least one gate line is connected with one sub-gate driving circuit;
wherein the length of the sub-gate driving circuit in the data line extending direction is greater than or equal to 1.5 times the length of the sub-pixel region in the data line extending direction.
A display panel comprises an array substrate and an opposite substrate arranged opposite to the array substrate, wherein the array substrate is the array substrate.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
according to the array substrate and the display panel provided by the invention, at least one gate line is connected with one sub-gate drive circuit, so that compared with the scheme that each gate line is connected with two sub-gate drive circuits in the prior art, the number of the sub-gate drive circuits is less, and the AOI detection efficiency of the gate drive circuit on the array substrate with color resistance can be relatively improved; moreover, on the basis of reducing the number of the sub-gate driving circuits, the length of the sub-gate driving circuit in the extending direction of the data line can be more than or equal to 1.5 times of the length of the sub-pixel area in the extending direction of the data line, so that the distribution density of devices in the sub-gate driving circuit can be reduced, and the AOI detection efficiency of the gate driving circuit is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic top view of an array substrate in the prior art;
fig. 2 is a schematic top view of an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of the array substrate shown in fig. 2;
fig. 4 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the invention;
fig. 5 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;
fig. 6 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;
fig. 7 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;
fig. 8 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;
fig. 9 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the invention.
Detailed Description
As described in the background, the AOI detection efficiency of the gate driving circuit of the array substrate having the color resistance is low compared to the array substrate having no color resistance. This is because, on the array substrate without color resistors, the gate driving circuit is not covered by the color resistors, and the AOI detection can be performed by using visible light imaging; on the basis of the fact that, on the array substrate with the color resistors, in order to reduce the step difference between the display area and the non-display area, the non-display area is also provided with the color resistors, namely the gate driving circuit is covered by the color resistors, most of visible light is filtered by the color resistors, and therefore the gate driving circuit covered by the color resistors cannot be subjected to AOI (automated optical inspection) by adopting the visible light.
The inventors have found that the AOI detection efficiency of the gate driver circuit can be improved by reducing the number of sub-gate driver circuits and the distribution density of devices such as TFTs. Accordingly, the present invention is directed to an array substrate to overcome the above problems of the prior art, the array substrate including a display area and a non-display area;
the display area comprises a plurality of gate lines, a plurality of data lines and a plurality of color resistors, the gate lines and the data lines are crossed in an insulating mode to define a plurality of sub-pixel areas, and the color resistors are arranged corresponding to the sub-pixel areas; the non-display area comprises a gate driving circuit, the gate driving circuit comprises a plurality of sub-gate driving circuits, each sub-gate driving circuit is connected with the gate line, and at least one gate line is connected with one sub-gate driving circuit; wherein the length of the sub-gate driving circuit in the data line extending direction is greater than or equal to 1.5 times the length of the sub-pixel region in the data line extending direction.
In the array substrate provided by the invention, the number of the sub-gate drive circuits is small, so that the AOI detection efficiency of the gate drive circuit on the array substrate with color resistance can be relatively improved; in addition, the length of the sub-gate driving circuit in the extending direction of the data line is greater than or equal to 1.5 times of the length of the sub-pixel area in the extending direction of the data line, so that the distribution density of devices in the sub-gate driving circuit can be reduced, and the AOI detection efficiency of the gate driving circuit is further improved.
The foregoing is a core idea of the present invention, and in order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, fig. 2 is a schematic top view of an array substrate according to an embodiment of the present invention, where the array substrate includes a display area and a non-display area located around the display area. The display area includes a plurality of gate lines 20, a plurality of data lines 21, and a plurality of sub-pixel regions 22 defined by the insulated crossings of the plurality of gate lines 20 and the plurality of data lines 21, and the non-display area includes a data driving circuit 30 and a gate driving circuit 31.
Each sub-pixel region 22 is provided with a corresponding sub-pixel, and each sub-pixel includes a thin film transistor 23 and a pixel electrode 24 provided in the sub-pixel region 22. Referring to fig. 3, fig. 3 is a schematic cross-sectional view of the array substrate shown in fig. 2, the thin film transistor 23 includes a gate electrode 230, a source electrode 231, and a drain electrode 232 on the substrate 1, wherein the gate electrode 230 is connected to the corresponding gate line 20, the source electrode 231 is connected to the corresponding data line 21, and the drain electrode 232 is connected to the pixel electrode 24 through a via 240. In addition, the array substrate further includes a common electrode 25 disposed on the substrate 1, wherein the common electrode 25 is disposed corresponding to the plurality of sub-pixel regions 22, so as to drive the corresponding sub-pixels to display images by the voltage difference between the common electrode 25 and the pixel electrodes 24.
The array substrate in this embodiment further includes a color resist layer 26, where the color resist layer 26 includes a black matrix 260 and a plurality of color resists 261, the black matrix 260 defines a plurality of color resist regions in a display region of the array substrate, each color resist region is provided with one color resist 261, and the color resist 261 is provided corresponding to the sub-pixel region 22. Optionally, each color resistor 261 is disposed corresponding to one sub-pixel region 22, or each color resistor 261 is disposed corresponding to a plurality of sub-pixel regions 22.
In order to reduce the step difference between the display area and the non-display area, the color resistor 261 in this embodiment at least partially covers the sub-gate driving circuit 310. As shown in fig. 2, the color resistors 261 on the left and right sides of the array substrate at least partially cover the sub-gate driving circuit 310 adjacent thereto, and optionally, the color resistors 261 at least cover 80% of the area of the sub-gate driving circuit 310.
In the structure shown in fig. 3, the color resistance layer 26 is located between the thin film transistor layer and the pixel electrode layer, where the thin film transistor layer refers to the film layer where the thin film transistor 23 is located, and the pixel electrode layer refers to the film layer where the pixel electrode 24 is located, although the invention is not limited thereto, the color resistance layer 26 may be located between any two layers of the thin film transistor layer, the pixel electrode layer and the common electrode layer, that is, the color resistance layer 26 may be located between any two layers of the film layer where the thin film transistor 23 is located, the film layer where the pixel electrode 24 is located and the film layer where the common electrode 25 is located.
In the structure shown in fig. 3, the film layer where the common electrode 25 is located on the surface of the film layer where the pixel electrode 24 is located, but the invention is not limited thereto, and in other embodiments, as shown in fig. 4, fig. 4 is a schematic cross-sectional structure diagram of another array substrate provided in the embodiment of the invention, the film layer where the common electrode 25 is located between the film layer where the pixel electrode 24 is located and the color resistance layer 26, and at this time, the drain electrode 232 of the thin film transistor 23 is connected to the pixel electrode 24 on the color resistance surface through the via 241 penetrating through the corresponding color resistance and the corresponding common electrode 25.
In the present embodiment, referring to fig. 2, the data driving circuit 30 is connected to all the data lines 21 for supplying data signals to the data lines 21. The gate driving circuit 31 includes a plurality of sub-gate driving circuits 310, and each sub-gate driving circuit 310 is connected to the gate line 20 and is configured to provide a scanning signal to the gate line 20 to control the thin film transistor 23 connected to the gate line 20 to be turned on, so that the data signal in the data line 21 is transmitted to the pixel electrode 24 through the turned-on thin film transistor 23, and the sub-pixel corresponding to the pixel electrode 24 displays an image.
The sub-gate driving circuit 310 in this embodiment is a shift register, and the structure of the sub-gate driving circuit is the same as that of a shift register in an existing array substrate, and is not described herein again. In addition, in this embodiment, the connection relationship between the sub-gate driving circuits 310 is only one cascade connection manner of the shift register, and the present invention is not limited thereto, and in other embodiments, other cascade connection manners may be adopted between the sub-gate driving circuits 310.
In this embodiment, at least one gate line 20 is connected to one sub-gate driving circuit 310, so that the number of sub-gate driving circuits 310 on the array substrate can be reduced, and the AOI detection efficiency of the gate driving circuit 31 can be improved. On this basis, in the present embodiment, the sub-gate driving circuit 310 has a length L in the extending direction of the data line 21 (X direction shown by arrow in fig. 2)3Is greater than or equal to the length L of the sub-pixel region 22 in the extending direction of the data line 2141.5 times of the total number of the sub-gate driving circuits, so as to reduce the distribution density of devices such as TFTs in the sub-gate driving circuits, and further improve the AOI detection efficiency of the gate driving circuit 31 by improving the imaging definition. Optionally, in this embodiment, the length L of the sub-gate driving circuit 310 in the extending direction of the data line 21 is3Is equal to the length L of the sub-pixel region 22 in the extending direction of the data line 2141.7 times, so that the AOI detection efficiency of the gate driving circuit 31 on the array substrate with the color resistor 261 in the embodiment of the present invention is the same as or slightly higher than that of the gate driving circuit on the array substrate without the color resistor.
The length L of the sub-gate driving circuit 310 in the extending direction of the data line 21 is defined as follows3Is equal to the length L of the sub-pixel region 22 in the extending direction of the data line 214The structure of the array substrate will be described with reference to the specific embodiments by taking the 1.7 times as an example.
In a specific implementation manner, as shown in fig. 5, fig. 5 is a schematic top view structure diagram of another array substrate according to an embodiment of the present invention, each gate line 20 is connected to a sub-gate driving circuit 310, and the sub-gate driving circuits 310 are distributed on two opposite sides of the array substrate. In the structure shown in fig. 5, the plurality of gate lines 20 are sequentially arranged along the extending direction of the data line 21, and optionally, the sub-gate driving circuits 310 of the gate lines 20 that are ordered as odd numbers along the direction X shown by the arrow in fig. 5 are located on one side of the array substrate, and the sub-gate driving circuits 310 of the gate lines 20 that are ordered as even numbers along the direction X shown by the arrow in fig. 5 are located on the other side of the array substrate opposite to each other, so as to improve the uniformity of the distribution of the sub-gate driving circuits 310, and further improve the AOI detection efficiency of the gate driving circuit 31.
In another specific implementation, as shown in fig. 6, fig. 6 is a schematic top view structure of another array substrate according to an embodiment of the present invention, in which the plurality of gate lines 20 includes at least one first gate line 201 and at least one second gate line 202, each first gate line 201 is connected to one sub-gate driving circuit 310, and optionally, the sub-gate driving circuits 310 connected to two adjacent first gate lines 201 are respectively located at two opposite sides of the array substrate; each second gate line 202 is connected to two sub-gate driving circuits 310, the two sub-gate driving circuits 310 are respectively located at two opposite sides of the array substrate, and the two sub-gate driving circuits 310 are respectively connected to two ends of the second gate line 202.
In the structure shown in fig. 6, at least one first gate line 201 and at least one second gate line 202 are sequentially arranged along the extending direction of the data line 21 (X direction as indicated by arrow in fig. 6), i.e., all the first gate lines 201 are sequentially arranged at the upper portion of the array substrate, and all the second gate lines 202 are sequentially arranged at the lower portion of the array substrate.
However, in another embodiment, as shown in fig. 7, fig. 7 is a schematic top view structure diagram of another array substrate according to an embodiment of the present invention, in which at least one second gate line 202 and at least one first gate line 201 are sequentially arranged along the extending direction of the data line 21, that is, all the second gate lines 202 are sequentially arranged on the upper portion of the array substrate, and all the first gate lines 201 are sequentially arranged on the lower portion of the array substrate.
Alternatively, in other embodiments, as shown in fig. 8, fig. 8 is a schematic top view structure diagram of another array substrate according to an embodiment of the present invention, the first gate lines 201 and the second gate lines 202 may be arranged at intervals, and optionally, the sub-gate driving circuits 310 connected to two adjacent first gate lines 201 are respectively located at two opposite sides of the array substrate, which is not limited in the present invention.
In addition, it should be noted that the color resistors 261 in this embodiment include a red color resistor, a green color resistor, and a blue color resistor, and of course, in other embodiments, the color resistors 261 may also include a red color resistor, a green color resistor, a blue color resistor, and a white color resistor, and the invention is not limited thereto. In this embodiment, the color of the sub-pixel is determined by the color of the color resistor corresponding to the sub-pixel, that is, if the color of the color resistor is red, the display color of the corresponding sub-pixel is also red, if the color of the color resistor is green, the display color of the corresponding sub-pixel is also green, and if the color of the color resistor is blue, the display color of the corresponding sub-pixel is also blue. Therefore, the image can be displayed by mixing the colors of the sub-pixels with different colors.
According to the array substrate provided by the embodiment of the invention, because at least one gate line is connected with one sub-gate driving circuit, compared with the scheme that each gate line is connected with two sub-gate driving circuits in the prior art, the number of the sub-gate driving circuits is less, so that the AOI detection efficiency of the gate driving circuits on the array substrate with color resistance can be relatively improved; moreover, on the basis of reducing the number of the sub-gate driving circuits, the length of the sub-gate driving circuit in the extending direction of the data line can be more than or equal to 1.5 times of the length of the sub-pixel area in the extending direction of the data line, so that the distribution density of devices in the sub-gate driving circuit can be reduced, and the AOI detection efficiency of the gate driving circuit is further improved.
As shown in fig. 9, the display panel further includes an array substrate 90 provided in any of the above embodiments and an opposite substrate 91 disposed opposite to the array substrate 90, and in a specific embodiment of the present invention, the display panel further includes a liquid crystal layer 92 disposed between the array substrate 90 and the opposite substrate 91, which is not described herein again. Based on the array substrate structure, the manufacturing time of the display panel in the embodiment is short, and the cost is low.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. An array substrate comprises a display area and a non-display area, and is characterized in that:
the display area comprises a plurality of gate lines, a plurality of data lines and a plurality of color resistors, the gate lines and the data lines are crossed in an insulating mode to define a plurality of sub-pixel areas, and the color resistors are arranged corresponding to the sub-pixel areas;
the non-display area comprises a gate driving circuit, the gate driving circuit comprises a plurality of sub-gate driving circuits, each sub-gate driving circuit is connected with the gate line, and at least one gate line is connected with one sub-gate driving circuit;
wherein the color resistors at least partially cover the sub-gate driving circuits; the length of the sub-gate driving circuit in the extending direction of the data line is greater than or equal to 1.5 times of the length of the sub-pixel area in the extending direction of the data line, so that when AOI detection is carried out on the sub-gate driving circuit, the distribution density of devices in the sub-gate driving circuit is reduced by increasing the area of the sub-gate driving circuit.
2. The array substrate of claim 1, wherein each of the gate lines is connected to one of the sub-gate driving circuits, and the plurality of sub-gate driving circuits are disposed on opposite sides of the array substrate.
3. The array substrate of claim 1, wherein the plurality of gate lines comprises at least one first gate line and at least one second gate line;
each first gate line is connected with one sub-gate driving circuit;
each second gate line is connected with two sub-gate driving circuits, the two sub-gate driving circuits are respectively located on two opposite sides of the array substrate, and the two sub-gate driving circuits are respectively connected with two ends of the second gate line.
4. The array substrate of claim 3, wherein the at least one first gate line and the at least one second gate line are sequentially arranged along an extending direction of the data line;
or, the at least one second gate line and the at least one first gate line are sequentially arranged along an extending direction of the data line;
alternatively, the first gate line and the second gate line are arranged at an interval in the extending direction of the data line.
5. The array substrate of claim 1, wherein the length of the sub-gate driving circuit in the data line extending direction is equal to 1.7 times the length of the sub-pixel in the data line extending direction.
6. The array substrate of claim 1, wherein the array substrate further comprises a thin film transistor layer, a pixel electrode layer, a common electrode layer and a color resistance layer;
the color resistance layer comprises a plurality of color resistances, and is positioned between any two layers of the thin film transistor layer, the pixel electrode layer and the common electrode layer.
7. The array substrate of claim 6, wherein the color resistance layer is located between the thin-film transistor layer and the pixel electrode layer.
8. The array substrate of claim 1, wherein the color resistors cover at least 80% of the area of the sub-gate driving circuit.
9. A display panel comprising an array substrate and a counter substrate disposed opposite to the array substrate, wherein the array substrate is the array substrate according to any one of claims 1 to 8.
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| CN201610617410.XA CN106023867B (en) | 2016-07-29 | 2016-07-29 | Array substrate and display panel |
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| CN201610617410.XA CN106023867B (en) | 2016-07-29 | 2016-07-29 | Array substrate and display panel |
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| CN106782250B (en) * | 2017-01-16 | 2020-11-27 | 京东方科技集团股份有限公司 | Display panel, detection method thereof and display device |
| CN107492363A (en) * | 2017-09-28 | 2017-12-19 | 惠科股份有限公司 | Driving device and driving method of display panel |
| CN107643617A (en) * | 2017-10-25 | 2018-01-30 | 惠科股份有限公司 | Driving device and display device |
| CN109188804B (en) * | 2018-09-03 | 2021-06-22 | Tcl华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display |
| CN109036237B (en) * | 2018-09-30 | 2021-07-09 | 厦门天马微电子有限公司 | Display device |
| CN109545115A (en) * | 2018-12-04 | 2019-03-29 | 深圳市华星光电半导体显示技术有限公司 | Device of testing electrical properties and device of testing electrical properties cross hairs precise defect location method |
| CN111986607B (en) * | 2020-08-19 | 2021-12-03 | 武汉华星光电技术有限公司 | Display panel and display device |
| CN112130389B (en) * | 2020-09-30 | 2022-04-29 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
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| CN101290409B (en) * | 2007-04-17 | 2010-05-19 | 北京京东方光电科技有限公司 | Gate drive circuit and LCD device |
| KR101374084B1 (en) * | 2007-11-01 | 2014-03-13 | 삼성디스플레이 주식회사 | Gate driving circuit and display substrate having the same |
| CN101673017B (en) * | 2009-10-28 | 2012-02-29 | 友达光电股份有限公司 | Active component array substrate and manufacturing method thereof |
| CN104485085B (en) * | 2015-01-04 | 2017-07-21 | 京东方科技集团股份有限公司 | A kind of array base palte and display device |
| CN104656333A (en) * | 2015-03-18 | 2015-05-27 | 深圳市华星光电技术有限公司 | COA (Color filter On Array) type liquid crystal panel and manufacturing method thereof |
| CN108445687B (en) * | 2015-06-30 | 2021-04-13 | 上海天马微电子有限公司 | Array substrate, display panel and liquid crystal display device |
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Effective date of registration: 20201202 Address after: Room A-430, 4th Floor, Block A, Phase II, Guangxi Huike Science and Technology Co., Ltd., 336 East Extension Line of Beihai Avenue, Beihai Industrial Park, Guangxi Zhuang Autonomous Region Patentee after: BEIHAI HKC PHOTOELECTRIC TECHNOLOGY Co.,Ltd. Address before: 5-6 / F, building D, huilongda Industrial Park, Shuitian Private Industrial Park, Shiyan street, Bao'an District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Haiyun Communication Co.,Ltd. Effective date of registration: 20201202 Address after: 5-6 / F, building D, huilongda Industrial Park, Shuitian Private Industrial Park, Shiyan street, Bao'an District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Haiyun Communication Co.,Ltd. Address before: 201108 Shanghai city Minhang District Huaning Road No. 3388 Patentee before: Shanghai AVIC Optoelectronics Co.,Ltd. Patentee before: Tianma Micro-Electronics Co.,Ltd. |