CN105990248A - Semiconductor device and manufacture method thereof - Google Patents
Semiconductor device and manufacture method thereof Download PDFInfo
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- CN105990248A CN105990248A CN201510087815.2A CN201510087815A CN105990248A CN 105990248 A CN105990248 A CN 105990248A CN 201510087815 A CN201510087815 A CN 201510087815A CN 105990248 A CN105990248 A CN 105990248A
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000009413 insulation Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000003475 lamination Methods 0.000 claims abstract description 4
- 239000012212 insulator Substances 0.000 claims description 29
- 238000010276 construction Methods 0.000 claims description 25
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims 1
- 239000000463 material Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005304 joining Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42352—Gate electrodes for transistors with charge trapping gate insulator with the gate at least partly formed in a trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a semiconductor device and a manufacture method thereof. The manufacture method of the semiconductor device comprises the following steps that a bottom insulation layer is formed on a substrate; two lamination structures are formed on the bottom insulation layer; and each lamination structure comprises a grid layers, grid insulation layers, a top insulation layer and a conductive mask layer; each charge capturing structure comprises first dielectric layers and second dielectric layers; part of the first dielectric layers is etched to expose part of the second dielectric layers; part of the second dielectric layers is etched to expose part of channel layers; and a landing pad layer is formed on the conductive mask layer and the first and second conductive layers to connect the conductive mask layers with the channel layers.
Description
Technical field
The invention relates to a kind of semiconductor device and manufacture method thereof, and in particular to one
Vertical channel semiconductor device and manufacture method thereof.
Background technology
In recent years, the constantly evolution of the structure of semiconductor device, and the storage volume of device increases constantly
Add.Storage arrangement is used for storing many electronic products, e.g. MP3 archives, digitized video,
Computer documents etc..Along with range of application is constantly increasing, the demand of storage arrangement focuses on corpusculum
Amass and Large Copacity.In order to meet its requirement, need the memory device with high component density and small size
Put and manufacture method.
Therefore, one can be reached big storage volume, small size and have good performance and stability
Vertical channel storage arrangement, it has also become the important directions of research and development.
Summary of the invention
The invention relates to a kind of semiconductor device and manufacture method, its etched portions charge-trapping
Structure and form a cushion layer, to form a thick connection pad, firmly connect a bit line.
According to the first aspect of the invention, the manufacture method of a kind of semiconductor device is proposed.Manufacture method
Comprise the following steps.Form a bottom insulation layer on a substrate.Form two laminated construction exhausted in bottom
In edge layer.Each laminated construction includes multiple grid layer, multiple gate insulator, a top layer
And a conductive mask layer.Grid layer and gate insulator are alternately arranged in bottom insulation layer.Top
Insulating barrier is arranged on grid layer and gate insulator.Conductive mask layer is arranged in top layer.
Form a charge trapping structure and a channel layer in a side surface of each laminated construction and bottom insulation
One upper surface of layer.Each charge trapping structure includes multiple first dielectric layer and multiple second dielectric layer.
Each first dielectric layer of etched portions, with each second dielectric layer of expose portion.Etched portions
Each second dielectric layer, with the channel layer of expose portion.Formed a cushion layer in conductive mask layer,
On one dielectric layer and the second dielectric layer, to connect conductive mask layer and channel layer.
According to the second aspect of the invention, it is provided that semiconductor device.Quasiconductor include a substrate, one
Bottom insulation layer, two laminated construction, a charge trapping structure and a cushion layer.Bottom insulation layer is arranged
On substrate.Laminated construction is arranged in bottom insulation layer.Each laminated construction include multiple grid layer,
Multiple gate insulators, a top layer and a conductive mask layer.Grid layer is handed over gate insulator
Alternately it is arranged in bottom insulation layer.Top layer is arranged on grid layer and gate insulator.Lead
Electricity mask layer is arranged in top layer.Charge trapping structure and channel layer are arranged at each lamination knot
On one side surface of structure and a upper surface of bottom insulation layer.Each charge trapping structure includes multiple
One dielectric layer and multiple second dielectric layer.The top of channel layer higher than each the first dielectric layer top and
The top of each the second dielectric layer.Cushion layer is arranged at conductive mask layer, the first dielectric layer and second and is situated between
In electric layer, to connect conductive mask layer and channel layer.
More preferably understand in order to the above-mentioned and other aspect of the present invention is had, preferred embodiment cited below particularly,
And coordinate institute's accompanying drawings, it is described in detail below:
Accompanying drawing explanation
Fig. 1 illustrates semiconductor device.
Fig. 2 A～Fig. 2 F illustrates the flow chart of the manufacture method of the semiconductor device of an embodiment.
Fig. 3 A～Fig. 3 F illustrates the flow chart of the manufacture method of the semiconductor device of another embodiment.
[symbol description]
100,200: semiconductor device
110: substrate
120: bottom insulation layer
120a: upper surface
130,230: laminated construction
130a: groove
130b: side surface
131: grid layer
132: gate insulator
133: top layer
134,234: conductive mask layer
135: insulating mask layer
140: charge trapping structure
141: the first dielectric layers
142: the second dielectric layers
150: channel layer
160: cushion layer
170: spacer insulator layer
D: drain electrode
G: grid
T1, T2, T3: thickness
S: source electrode
Detailed description of the invention
The following is the various embodiments of proposition to be described in detail, it utilizes etched portions charge trapping structure
(charge trapping structure), and a cushion layer (landing pad layer) is set, to be formed
The connection pad (landing pad) of one thickness, is strongly attached to a bit line (bit line).But, real
Execute example only in order to illustrate as example, can't the scope to be protected of the limit present invention.Additionally, implement
Graphic in example is to omit unnecessary element, to clearly show that the technical characterstic of the present invention.
Refer to Fig. 1, it illustrates the schematic diagram of semiconductor device 100.For example, quasiconductor
Device 100 can be a three-dimensional perpendicular passage NAND device (three-dimensional vertical
channel NAND device).Semiconductor device 100 includes a substrate (substrate) 110,
Bottom insulation layer (bottom insulating layer) 120, at least two layer stacked structure (stacked
Structures) 130, one charge trapping structure 140, channel layer (channel layer) 150,
Cushion layer 160 and a spacer insulator layer (spaced insulating layer) 170.
Each laminated construction 130 includes multiple grid layer (gate layer) 131, multiple gate insulator
Layer (gate insulating layer) 132, one top layer (top insulating layer) 133 and
One conductive mask layer (conductive mask layer) 134.Charge trapping devices 140 includes multiple
First dielectric layer (first dielectric layer) 141 and multiple second dielectric layer 142 (second
dielectric layer).Each grid layer 131 is connected to a grid (gate) G.Cushion layer 160 is even
It is connected to a source electrode (source) S or drain electrode (drain) D.
Cushion layer 160 is connected to a bit line.As it is shown in figure 1, due to conductive mask layer 134 and connection pad
The thickness T1 of the combination of layer 160 is more than the thickness T2 of channel layer 150, between bit line and cushion layer 160
Between contact resistance just can reduce.Additionally, the Joining Technology carrying out bit line and cushion layer 160 also becomes
It is easier to.
Refer to Fig. 2 A～Fig. 2 F, it illustrates the manufacture of the semiconductor device 100 according to an embodiment
The flow chart of method.As shown in Figure 2 A, it is provided that substrate 110.Then, as shown in Figure 2 A, formed
Bottom insulation layer 120 is on substrate 110.For example, the material of bottom insulation layer 120 is e.g.
Silicon oxide (silicon oxide).This manufacture method be self-aligned technique and need not be extra mask journey
Sequence.Additionally, the connection of channel layer 150 and cushion layer 160 is in the sidewall of channel layer 150, and
It it not the top at channel layer 150.Consequently, it is possible to process window (process window) can be increased
And reduce resistance.Furthermore, this structure will not occur corner edge effect (corner edge effect),
Its reason is that the first dielectric layer 141 is neither positioned at any corner edge, therefore will not be because of field effect
Easily it is programmed or wipes.
Then, as shown in Figure 2 A, grid layer 131 is alternately formed with gate insulator 132 end of in
On portion's insulating barrier 120 so that each grid layer 131 can mutually insulated.Each grid layer 131
Material e.g. N+ or P+ DOPOS doped polycrystalline silicon (N+or P+doping polysilicon), preferably
P+ DOPOS doped polycrystalline silicon.The material of each gate insulator 132 e.g. silicon oxide.
Then, as shown in Figure 2 A, top layer 133 is formed in grid layer 131 and gate insulator
On layer 132.The material of top layer 133 e.g. silicon nitride (silicon nitride).
Then, as shown in Figure 2 A, formed conductive mask layer 134 in top layer 133, with
Avoid top layer 133 to be etched, and may be used to connect cushion layer 160 (being illustrated in Fig. 1) and
Channel layer 150 (being illustrated in Fig. 1).
Then, as shown in Figure 2 A, insulating mask layer 135 is formed on conductive mask layer 134.Absolutely
The material of edge mask layer 135 e.g. silicon nitride.
Then, as shown in Figure 2 B, etching grid layer 131, gate insulator 132, top layer
133, conductive mask layer 134 and insulating mask layer 135, to form at least two laminated construction 130
And the groove 130a between adjacent laminated construction 130.In manufacture process, insulating mask layer 135
Laminated construction 130 can be consolidated, to avoid laminated construction 130 avalanche.
Then, as shown in Figure 2 C, form charge trapping structure 140 and channel layer 150 to fold in each
One side surface 130b of a Rotating fields 130 and upper surface 120a of bottom insulation layer 120.Electric charge is caught
Catch structure 140 and channel layer 150 for U-shaped.The material of channel layer 150 can be intrinsic or undoped p
Channel layer 150.Charge trapping structure 140 can be O1N1O2N2O3N3O4 structure (O1
Close to channel layer 150, O4 is close to laminated construction 130).Four silicon oxide layers (O1, O2,
O3, O4) there is different thickness and three silicon nitride layers (N1, N2, N3) have different thickness
Degree.Or, charge trapping structure 140 can be that (O1 is close to passage for O1N1O2N2O3 structure
Layer 150, O3 is close to laminated construction 130).The silicon oxide layer (O1, O2, O3) of three has not
Same thickness, two silicon nitride layers (N1, N2) have different thickness.These different thickness
It is to catch (trapping), O3 or O3N3O4 based on O1N1O2 tunnelling (tunneling), N2
The purpose of barrier (blocking) designs.
Then, as shown in Figure 2 C, the spacer insulator layer 170 ditch between laminated construction 130 is filled
Groove 130a.The material of spacer insulator layer 170 e.g. silicon oxide.Spacer insulator layer 170 can not be complete
Entirely fill up groove 130a so that the air gap is formed in spacer insulator layer 170.Air is also fine
Insulator.
Furthermore, as shown in Figure 2 D, each first dielectric layer 141 of etching part, with expose portion
Each second dielectric layer 142.In this step, it is to utilize phosphoric acid (H3PO4) carry out etch nitride
Silicon.Owing to phosphoric acid has a high selectivity for polysilicon and silicon oxide, conductive mask layer 134, logical
Channel layer the 150, second dielectric layer 142 and spacer insulator layer 170 will not be etched in this step.In this
In step, insulating mask layer 135 (being illustrated in Fig. 2 C) is also removed so that conductive mask layer 134
Surface be exposed.Owing to each first dielectric layer 141 of part is etched, therefore the second dielectric
Two sidewalls of at least the one of layer 142 are partially exposed.
Owing to the thickness of the first dielectric layer 141 is different, the first dielectric layer 141 is at etching effect (etching
Loading effect) under can be etched out the different degree of depth.
Then, as shown in Figure 2 E, each second dielectric layer 142 of etched portions, with expose portion
Channel layer 150.In this step, it is to utilize dilute hydrofluoric acid solution (DHF) to carry out etching oxidation
Silicon.Because dilute hydrofluoric acid solution has high selectivity, conductive mask for polysilicon and silicon nitride
Layer 134, channel layer the 150, first dielectric layer 141 will not be etched.
In this step, owing to each second dielectric layer 142 of part is etched, therefore each first Jie
Two sidewalls of electric layer 141 are partially exposed out.Furthermore, due to the spacing insulating barrier 170 of part
Also it is etched, therefore two sidewalls of channel layer 150 also are partially exposed out so that channel layer 150
Top higher than the top of the first dielectric layer 141 and the top of the second dielectric layer 142.
Owing to the thickness of the second dielectric layer 142 is different, the second dielectric layer 142 can quilt under etching effect
Etch the different degree of depth.In this step, conductive mask layer 134 then can avoid top layer
133 are etched.
Then, as shown in Figure 2 F, cushion layer 160 is formed in conductive mask layer the 134, first dielectric layer
141 and second on dielectric layer 142, to connect conductive mask layer 134 and channel layer 150.Cushion layer
The material of 160 e.g. n-type doping polysilicon.
In this step, cushion layer 160 and channel layer 150 are more ground so that cushion layer 160,
The top of channel layer 150 and spacer insulator layer 170 is all positioned at identical height.Conductive mask layer 134 and
The combination of cushion layer 160 can connect bit line as a connection pad.Conductive mask layer 134 and cushion layer
The thickness T1 of the combination of 160 is more than the thickness T2 of channel layer 150 so that between bit line and cushion layer
Contact resistance between 160 just can reduce.Additionally, the connection of channel layer 150 and cushion layer 160 is position
In the sidewall of channel layer 150 rather than at the top of channel layer 150.Consequently, it is possible to can increase
Process window (process window) also reduces resistance.Furthermore, carry out bit line and cushion layer 160
Joining Technology also become easier to.Corner edge effect (corner edge will not occur in this structure
Effect), its reason is that the first dielectric layer 141 is neither positioned at any corner edge, therefore will not be because of electricity
Field effect and be easily programmed or wipe.
In above-mentioned manufacture method, insulating mask layer 135 in order to consolidate laminated construction 130 in process,
To avoid laminated construction 130 avalanche in technique.In another embodiment, the manufacture of semiconductor device
Method can not use insulating mask layer 135.Refer to Fig. 3 A～Fig. 3 F, it illustrates another and implements
The flow chart of the manufacture method of the semiconductor device 200 of example.In this embodiment, conductive mask layer 234
Thickness increase so that conductive mask layer 234 i.e. can be used to firm laminated construction 230.
As illustrated in Figure 3 F, cushion layer 160 and conductive mask layer 234 are in order to connect as a connection pad
Connect bit line.The thickness T3 of conductive mask layer 234 and cushion layer 160 is greater than the thickness T2 of channel layer,
Contact resistance between bit line and cushion layer 160 just can be reduced.Furthermore, carry out bit line and connect
The Joining Technology of bed course 160 also becomes easier to.
In sum, although the present invention is disclosed above with preferred embodiment, and so it is not limited to
The present invention.Persond having ordinary knowledge in the technical field of the present invention, in the spirit without departing from the present invention
With in scope, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when depending on enclosing
Being as the criterion of being defined of right.
Claims (10)
1. a manufacture method for semiconductor device, including:
Form a bottom insulation layer on a substrate；
Forming two laminated construction in this bottom insulation layer, respectively this laminated construction includes multiple grid
Layer, multiple gate insulator, a top layer and a conductive mask layer, these grid layers and these
Gate insulator is alternately arranged in this bottom insulation layer, and this top layer is arranged at these grids
On layer and these gate insulators, this conductive mask layer is arranged in this top layer；
Form a charge trapping structure and a channel layer in a side surface of respectively this laminated construction and this end
One upper surface of portion's insulating barrier, respectively this charge trapping structure includes multiple first dielectric layer and multiple
Second dielectric layer；
Respectively this first dielectric layer of etched portions, with respectively this second dielectric layer of expose portion；
Respectively this second dielectric layer of etched portions, with this channel layer of expose portion；And
Form a cushion layer (1anding pad layer) in this conductive mask layer, these first dielectric layers
And on these second dielectric layers, to connect this conductive mask layer and this channel layer.
The manufacture method of semiconductor device the most according to claim 1, respectively this lamination knot
Structure further includes an insulating mask layer, and this insulating mask layer is arranged on this conductive mask layer, in etching portion
In the step of respectively this first dielectric layer divided, this insulating mask layer is to be removed.
The manufacture method of semiconductor device the most according to claim 1, wherein in etched portions
Respectively this first dielectric layer step in, the degree of depth that respectively this first dielectric layer is etched is different.
The manufacture method of semiconductor device the most according to claim 1, wherein in etched portions
Respectively this first dielectric layer step in, two sidewalls of at least the one of these the second dielectric layers are by partly
Expose.
The manufacture method of semiconductor device the most according to claim 1, wherein in etched portions
Respectively this second dielectric layer step in, the degree of depth that respectively this second dielectric layer is etched is different.
The manufacture method of semiconductor device the most according to claim 1, further includes:
Filling a spacer insulator layer in a groove, this groove is formed between these laminated construction；
Wherein in the step of respectively this second dielectric layer of etched portions, this spacer insulator layer of part is also
It is etched so that the top of this channel layer is higher than top and these second dielectrics of these the first dielectric layers
The top of layer.
7. a semiconductor device, including:
One substrate；
One bottom insulation layer, is arranged on this substrate；
Two laminated construction, are arranged in this bottom insulation layer, and respectively this laminated construction includes:
Multiple grid layers and multiple gate insulator, these grid layers and these gate insulators are handed over
Alternately it is arranged in this bottom insulation layer；
One top layer, is arranged on these grid layers and these gate insulators；And
One conductive mask layer, is arranged in this top layer；
One charge trapping structure and a channel layer, be arranged at a side surface and this end of respectively this laminated construction
On one upper surface of portion's insulating barrier, respectively this charge trapping structure includes multiple first dielectric layer and many
Individual second dielectric layer, the top of this channel layer higher than each this first dielectric layer top and respectively this second is situated between
The top of electric layer；And
One cushion layer, is arranged at this conductive mask layer, these first dielectric layers and these the second dielectric layers
On, to connect this conductive mask layer and this channel layer.
Semiconductor device the most according to claim 7, wherein this cushion layer and this conduction mask
The thickness of the combination of layer is more than the thickness of this channel layer.
Semiconductor device the most according to claim 7, the wherein top of these the first dielectric layers
It is positioned at differing heights.
Semiconductor device the most according to claim 7, respectively two sides of this first dielectric layer
It is contacted with this cushion layer rim portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510087815.2A CN105990248A (en) | 2015-02-26 | 2015-02-26 | Semiconductor device and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510087815.2A CN105990248A (en) | 2015-02-26 | 2015-02-26 | Semiconductor device and manufacture method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105990248A true CN105990248A (en) | 2016-10-05 |
Family
ID=57039041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510087815.2A Pending CN105990248A (en) | 2015-02-26 | 2015-02-26 | Semiconductor device and manufacture method thereof |
Country Status (1)
| Country | Link |
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| CN (1) | CN105990248A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109801919A (en) * | 2017-11-17 | 2019-05-24 | 旺宏电子股份有限公司 | The manufacturing method of 3-D stacks semiconductor structure and its structure obtained |
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| US20140035026A1 (en) * | 2012-07-31 | 2014-02-06 | Byong-hyun JANG | Semiconductor memory devices and methods of fabricating the same |
| US8803222B2 (en) * | 2011-07-07 | 2014-08-12 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices using direct strapping line connections |
| US20150008499A1 (en) * | 2013-07-08 | 2015-01-08 | Jae-Goo Lee | Vertical semiconductor device |
| CN105914184A (en) * | 2015-02-24 | 2016-08-31 | 旺宏电子股份有限公司 | Semiconductor device and manufacturing method thereof |
-
2015
- 2015-02-26 CN CN201510087815.2A patent/CN105990248A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8803222B2 (en) * | 2011-07-07 | 2014-08-12 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices using direct strapping line connections |
| US20140035026A1 (en) * | 2012-07-31 | 2014-02-06 | Byong-hyun JANG | Semiconductor memory devices and methods of fabricating the same |
| US20150008499A1 (en) * | 2013-07-08 | 2015-01-08 | Jae-Goo Lee | Vertical semiconductor device |
| CN105914184A (en) * | 2015-02-24 | 2016-08-31 | 旺宏电子股份有限公司 | Semiconductor device and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109801919A (en) * | 2017-11-17 | 2019-05-24 | 旺宏电子股份有限公司 | The manufacturing method of 3-D stacks semiconductor structure and its structure obtained |
| CN109801919B (en) * | 2017-11-17 | 2021-06-04 | 旺宏电子股份有限公司 | Method for fabricating three-dimensional stacked semiconductor structure and structure fabricated thereby |
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