CN105989879B - High reliability Nonvolatile semiconductor memory device and its data erasing method - Google Patents
High reliability Nonvolatile semiconductor memory device and its data erasing method Download PDFInfo
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- CN105989879B CN105989879B CN201510062510.6A CN201510062510A CN105989879B CN 105989879 B CN105989879 B CN 105989879B CN 201510062510 A CN201510062510 A CN 201510062510A CN 105989879 B CN105989879 B CN 105989879B
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Abstract
The present invention provides the Nonvolatile semiconductor memory device and its data erasing method of a kind of deterioration of reliability caused by inhibiting because of rewriting data.The erasing method of flash memory of the invention includes: that control grid is remained 0V, P well (14) are applied with the pulse of erasing (Ps) of high voltage, thus discharge electronics to after P well (14) from floating grid, control grid is remained into 0V again, the voltage ratio low weak pulse of erasing (Pw) of pulse (Ps) of erasing is applied to P well (14).
Description
Technical field
The present invention relates to a kind of anti-and (NAND) type or or non-(NOR) type flash memory reliability, and be related to mentioning
Even if write-in is repeated for one kind to erase, deteriorated reliability also less high reliability Nonvolatile semiconductor memory device and
Its data erasing method.
Background technique
Fig. 1 shows the schematic sectional view of the cell array of NAND quick-flash memory (cell array), Fig. 2 indicates the unit
The equivalent circuit of array.It is formed with N well (well) 12 in P-type silicon substrate 10, P well 14 is formed in N well 12.In P well 14
It is interior, it is formed with the multiple transistors for constituting NAND string (string).1 NAND string includes multiple memory units of series connection；
Source electrode line selection transistor is connected to one of end of memory unit；Bit line selection transistor is connected to another end
Portion.In Fig. 1, the choosing of the control grid (wordline WL1, WL2 ... WLn) 20, source electrode line side selection transistor of memory unit is shown
Select the selection gate 24 of grid 22, bit line side selection transistor.In P well 14, multiple such NAND are formed with along line direction
It goes here and there, the NAND string in 1 P well 14 constitutes 1 block.
Source electrode line SL is electrically connected to the n- diffusion zone (source region) 23 of source electrode line selection transistor, and bit line BL is electrically connected
It is connected to the n- diffusion zone (drain region) 23 of bit line selection transistor.Moreover, being formed with the p of contact portion in P well 14
+ diffusion zone 26 is formed with n+ diffusion zone 27 in N well 12, the two p+ diffusion zones 26, n+ diffusion zone 27 pass through N
Well/P well common contact section 28 and connect.As described later, when carrying out when erasing of selected block, via N well/P well
Common contact section 28 applies the pulse of erasing of the high voltage of P well.
Referring to Fig. 2, along a plurality of wordline WL1, WL2 ... WLn is formed with the line direction that NAND string is intersected, each wordline WL is common
It is connected to the control grid 20 of the corresponding memory unit of line direction.Selection grid polar curve SGS is commonly connected to the source electrode of line direction
The selection gate 22 of line options transistor, selection grid polar curve DSG are commonly connected to the choosing of the bit line selection transistor of line direction
Select grid 24.When source electrode line selection transistor is connected by selection grid polar curve SGS, NAND string is electrically connected source electrode line SL, when logical
When crossing selection grid polar curve DSG conducting bit line options transistor, NAND string is electrically connected bit line BL.
Fig. 3 indicates that NAND quick-flash memory erasing when acting of erasing selects the voltage wave of each node (node) in block
Shape.Node N1 indicates N well/P well common contact section 28, and N2 indicates the n- diffusion zone 23, N3 of the contact portion of source electrode line SL
Indicate the selection gate 22 of source electrode line side selection transistor, N4 indicates that wordline (control grid) 20, N5 in same block is indicated
The selection gate 24 of bit line side selection transistor, N6 indicate the waveform of the diffusion zone of the contact portion of bit line BL.In addition,
In non-selection block, N4, which becomes, selects the same waveform of N3 in block or N5 with erasing.
NAND quick-flash memory carries out data as unit of block and erases.At this point, the wordline of selected block is set as
0V or the voltage lower than P well, the positive voltage for applying long strip type to the P well 14 for forming memory unit array are erased pulse Ps, are applied
It erases after pulse Ps, the current potential of P well 14 is restored to 0V.At this point, each node N2, N3, N5, N6 pass through the capacitive coupling with P well 14
And automatic boosting.After erasing, by verification (verify) read, and determine select memory unit in block threshold value whether for
Below particular value.If all units in block threshold value be particular value hereinafter, if erase movement complete, if but some list
The threshold value of first (cell) is particular value or more, then applies the pulse Ps that erases again, carries out verification again and reads (such as patent document
1)。
When write-in, P well 14 is set as 0V, gives high voltage to selected wordline.0V or positive potential are given to bit line BL,
In the case where 0V, the silicon face of selecting unit becomes 0V, has electronics tunnel current from silicon substrate towards floating grid flowing.By
This, the threshold value of unit becomes to be above certain specified value.
In NAND quick-flash memory, to improve integrated level, three-dimensional scheme (the non-patent text for constituting memory unit array is proposed
Offer 1, non-patent literature 2, non-patent literature 3).It is functioned for example, vertically being formed from silicon substrate as passage area
Polysilicon column, form multiple control grids along the column of the polysilicon.Between control grid and channel part, formation is used for
The layer of accumulated charge.
Existing technical literature
Patent document
Patent document 1: Japanese Patent Laid-Open 2012-027979 bulletin
Non-patent literature 1: TCAT (million megabits of cell array crystal are used in ultra high density NAND quick-flash memory
Pipe) technology vertical cell array (Vertical Cell Array using TCAT (Terabit Cell Array
Transistor)Technology for Ultra High Density NAND Flash Memory),Jaehonn Jang
Technical digest (the 2009Symposium on VLSI Technology Digest of of et.al, 2009VLSI Conference Papers
Technical Papers),p192-193
Non-patent literature 2: the expansible skill of the position cost using punching and plug process in ultra high density flash memory
Art (Bit Cost Scalable Technology with Punch and Plug Process for Ultra High
Density Flash Memory), the technical digest of H.Tanaka et.al, 2007VLSI Conference Papers
(2007Symposium on VLSI Technology Digest of Technical Papers),P14-15
Non-patent literature 3: using paging bit line layout and efficient binary bit and MiLC (smallest incremental layer cost) rank
8 layers of vertical gate 3D NAND of high scalability (A High Scalable 8-layer Vertical Gate 3D of terraced contact portion
NAND with Split-page Bit Line Layout and Efficient Binary-sum MiLC(Minimal
Incremental Layer Cost)Staircase Contacts),Shin-Hung et.al,IEDM12-21,P2.3.1-
2.3.4
Summary of the invention
Existing NAND quick-flash memory is written/erases if being repeated, and can cause the film of the oxidation film under floating grid
Shoddyization can mostly occur after unfavorable condition or data write-in are written caused by increasing because of threshold value dispersion of distribution when data are read
Placement when data variation a problem that.As a result, there is limitation in rewriting data number, more than number is reached and limited, exist
Not the problem of reliability not can guarantee.There are several for oxidation film deterioration factor, have distinguished 1 factor are as follows: erase to the application of P well
After pulse, until switch to write-in until during there are oxidation film deteriorations.After pulse of erasing to the application of P well, change until right
Rewriting data is repeated in interval until wordline applies write pulse, by survey when being measured to the I-V characteristic of unit
Determine result and is shown in Fig. 4 (A) and 4 (B).Specifically, for from the interval until write-in of erasing, prepare 0.05 second (solid line) with
0.5 second (dotted line) both, Fig. 4 (A) indicates that initial I-V characteristic, Fig. 4 (B) indicate that the I-V after 3000 rewriting datas is special
Property.By the chart it is found that in the I-V characteristic after 3000 rewriting datas, compared with initial I-V characteristic, it is spaced within 0.5 second
The variation of situation is bigger.That is, the capture energy level of silicon interface increases, as a result, I- if elongated from the interval until write-in of erasing
The control grid potential interdependence of V characteristic reduces.Thus, it is believed that the placement after pulse of erasing applies can cause oxidation film bad
Change.Such oxidation film deterioration can be such that the reliability of the memory unit of miniaturization deteriorates, and lead to the data that can keep reliability
Number of rewrites is reduced.
It is such previous present invention aims at solving the problems, such as, deteriorated reliability caused by a kind of inhibit because of rewriting data is provided
Nonvolatile semiconductor memory device.
During verification after pulse of erasing application is read, oxidation film can be deteriorated.Therefore in the preferred solution of the invention,
Pulse of respectively erasing applies another weak pulse of erasing after applying immediately.The preferred solution of the invention, weak pulse settings of erasing are at will select
The wordline of block is set as 0V or the positive voltage lower than P well, is lower than common pulse of erasing to the positive voltage that P well applies.If P well electricity
Position is set to lower, then does not have the tunnel current of the electronics flowed from floating grid towards silicon substrate.Thus, the threshold of memory unit
Value will not change.By applying weak pulse of erasing, oxidation film deteriorated reliability can be inhibited.
In more preferably scheme of the invention, Nonvolatile semiconductor memory device is set as 0V or positive ratio P for grid is controlled
The low voltage of well applies positive pulse of erasing with P well to the N well under memory unit array, from floating grid (charge accumulation layer)
Electronics is discharged to silicon substrate, control grid is set as 0V or the positive voltage (ibid) lower than P well again, N well and P well are applied
The application of this two subpulse is set as a combination, under needing to apply by the making alive positive pulse low compared with first pulse of erasing
It is secondary erase pulse when, apply the two pulses.Preferably, in the pulse applied to N well and P well after pulse of erasing applies,
Avoid causing the electronics from floating grid towards silicon substrate from discharging.
In more preferable scheme, in which: control grid is set as 0V, is applied just to the N well under memory unit array with P well
Pulse of erasing, discharge from floating grid by electronics to silicon substrate, identical pulse apply during, reduction give N well
With the peak value of pulse of P well.At this point, avoiding causing from floating grid court also by the current potential for giving N well Yu P well is reduced in midway
It is discharged to the electronics of silicon substrate.
In more preferable scheme, control grid is set as 0V, positive smear is applied with P well to the N well under memory unit array
It except pulse, discharges from floating grid by electronics to silicon substrate, during identical pulse applies, control is improved since 0V
Grid potential makes control grid potential be restored to 0V while terminating to apply the positive pulse of erasing of N well and P well.This
When, by improving the current potential of control grid since 0V in midway, avoid causing the electronics from floating grid towards silicon substrate from releasing
It puts, and avoids causing the electron injection from silicon substrate towards floating grid.
The grid oxidation film present invention can inhibit because of rewriting data repeatedly more in the past caused by deteriorates, and thus can increase can protect
Hold the rewriting data number of reliability.
Detailed description of the invention
Fig. 1 is the architectural overview cross-sectional view in the cell array portion of NAND quick-flash memory；
Fig. 2 is the equivalent circuit diagram of NAND quick-flash memory；
Fig. 3 expression is in existing NAND quick-flash memory, the figure of the voltage waveform of each node when pulse of erasing applies；
Fig. 4 (A), Fig. 4 (B) are indicated from the figure for the interval interdependence of the I-V characteristic of memory unit erased until write-in
Table, Fig. 4 (A) are the charts for indicating initial I-V characteristic, and Fig. 4 (B) is the figure for indicating the I-V characteristic after 3000 rewriting datas
Table；
Fig. 5 indicates the block diagram of integrally-built an example of the NAND quick-flash memory of the embodiment of the present invention；
Fig. 6 is the action flow chart of erasing of the flash memory of the embodiment of the present invention；
Fig. 7 is the 1st embodiment and the waveform diagram of pulse of erasing that applies through the invention；
Fig. 8 is the 2nd embodiment and the waveform diagram of pulse of erasing that applies through the invention；
Fig. 9 is the 3rd embodiment and the waveform diagram of pulse of erasing that applies through the invention；
Figure 10 is the cross-sectional view of the memory unit of the flowing of electronics when indicating to erase；
Figure 11 is the energy band diagram (band diagram) when erasing pulse application；
Figure 12 is the energy band diagram after the pulse of erasing of previous example applies；
Figure 13 be the embodiment of the present invention erase pulse apply after apply it is weak erase pulse when energy band diagram；
Figure 14 is the action flow chart of erasing of the flash memory of the 4th embodiment of the invention；
Figure 15 is illustrated to the structure of the memory unit array of applicable three dimensional NAND flash memory of the invention
Schematic sectional view；
Figure 16 (A), Figure 16 (B) are to three dimensional NAND flash memory, when erasing to the channel part of memory unit array
Apply the figure that the method for high voltage is illustrated；
Figure 17 is the 5th embodiment and the waveform diagram of pulse of erasing that applies through the invention；
Figure 18 is the 6th embodiment and the waveform diagram of pulse of erasing that applies through the invention；
Figure 19 is the 7th embodiment and the waveform diagram of pulse of erasing that applies through the invention；
Figure 20 is the architectural overview cross-sectional view for being applicable in the cell array portion of NOR flash memory of the invention.
Description of symbols:
10:P type silicon substrate；
12:N well；
14:P well；
20: control grid (wordline)；
20A, 32,32-1~32-n, 300: control grid；
22: the selection gate of source electrode line side selection transistor；
23:n- diffusion zone；
24: the selection gate of bit line side selection transistor；
26:p+ diffusion zone；
27:n+ diffusion zone；
28:N well/P well common contact section；
30: channel part；
34:ONO structure (charge accumulation layer)；
36,38: selection gate；
40: bit line contact portion；
42: source line contact portion；
100: flash memory；
110: memory array；
120: input/output (i/o) buffer；
130: address register；
140: data register；
150: controller；
160: word line selection circuit；
170: page buffer/reading circuit；
180: column select circuit；
190: internal voltage generating circuit；
200: system clock generation circuit；
310: floating grid；
320: oxidation film；
Ax: row address information；
Ay: column address information；
BL: bit line；
C1, C2, C3: control signal；
N1~N6: node；
Ps: pulse of erasing (voltage of erasing)；
Pw: weak pulse of erasing (voltage of erasing)；
S100、S102、S104、S106、S108、S110、S112、S114、S200、S202、S204、S206、S208、
S210, S212, S214: step；
SGS: selection grid polar curve；
DSG: selection grid polar curve；
SL: source electrode line；
T1, t2: moment；
Ts: pulse spacing；
Vers: voltage of erasing；
Vpgm: program voltage；
Vpass: pass through voltage；
Vread: read-out voltage；
WL1~WLn: wordline.
Specific embodiment
Embodiment that the present invention will be described in detail referring to the drawings.It should be noted that, it is in order to facilitate understanding and strong in attached drawing
Each section is shown in mileometer adjustment, not identical as the ratio of actual components.
Fig. 5 is the block diagram of a structural example of the present embodiment NAND quick-flash memory.Flash memory 100 includes: storage
Device array 110 is formed with and is arranged in rectangular multiple memory units；Input/output (i/o) buffer 120, be connected to external input/
Output terminal I/O keeps input/output data；Address register 130 receives the address from input/output (i/o) buffer 120
Data；Data register 140 keeps the data of input/output；Controller 150 generates control signal C1, C2, C3 etc., the control
Signal C1, C2, C3 processed etc. be based on from input/output (i/o) buffer 120 order data and external control signal it is ((not shown)
Chip is enabled or address latch is enabled etc.) control each section；Word line selection circuit 160, to the row from address register 130
Address information Ax is decoded, and carries out the selection of block and the selection of wordline etc. based on decoding result；Page buffer/reading
(sense) circuit 170 out keeps the data read via bit line, or keeps programming data etc. via bit line；Column
Selection circuit 180 is decoded the column address information Ay from address register 130, and is carried out based on the decoding result
The selection etc. of bit line；Internal voltage generating circuit 190 generates the reading for being used to carry out data, programming (write-in) and erases
Required voltage (program voltage Vpgm, (including is smeared by (pass) voltage Vpass, read-out voltage Vread, the voltage Vers that erases
Except voltage Ps, Pw))；And system clock (system clock) generation circuit 200, generate built-in system clock pulse CLK.
Memory array 110 is as shown in Fig. 2, the NAND string comprising being connected in series multiple memory units.Memory is single
Member has metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor, abbreviation MOS) structure, which includes:
The source/drain as n+ diffusion zone being formed in P well；The tunnel oxide film being formed on the channel of source/drain interpolar；
The floating grid (charge accumulation layer) being formed on tunnel oxide film；And it is formed on the floating gate via dielectric film
Control grid.Typically, when accumulation has positive charge in floating grid, that is, when being written with data " 1 ", threshold value is in
Negative state, memory unit are connected in control gate extremely 0V.When accumulation has electronics in floating grid, that is, when being written with number
When according to " 0 ", threshold transitions are positive, and memory unit is disconnected in control gate extremely 0V.But memory unit is not limited to storage list
A bit can also store multiple bits.
Table 1
Table 1 is the table for indicating an example of the bias applied in each movement of flash memory.In reading operation, comparison
Special line applies specific positive voltage, applies specific voltage (such as 0V) to selected wordline, is applied through electricity to non-selection wordline
It presses Vpass (such as 4.5V), positive voltage (such as 4.5V) is applied to selection grid polar curve DSG, SGS, makes bit line selection transistor
TD, source electrode line selection transistor TS conducting apply 0V to common source line.In programming (write-in) movement, to selected word
Line applies the program voltage Vpgm (15V~20V) of high voltage, to non-selected wordline apply it is intermediate by voltage (such as
10V), bit line selection transistor TD is connected, disconnects source electrode line selection transistor TS, and will be with the data phase of " 0 " or " 1 "
The current potential answered is supplied to bit line GBL.
Erase act when, to the wordline selected in block control grid apply specific voltage (such as 0V), to P
Well applies the pulse of erasing of high voltage (such as 20V), and the electronics of floating grid is drawn to substrate, is thus come as unit of block
It erases data.The details of the movement of erasing of the present embodiment are described hereinafter.
Then illustrate the movement of erasing of the 1st embodiment of the invention.In the present embodiment preferred embodiment, more effectively to be remembered
The data of unit are erased, and erase (Incremental Step PulseErase, abbreviation ISPE) just using increment step-by-step impulse
Formula.Which is pulse of erasing to the application of the memory unit of selected block, the memory unit that then carries out determining to be erased (with
Call erased cell in the following text) threshold value whether He Ge verification then applies than previous high pulse of erasing, carries out if it is determined that unqualified
Next verification, and the application for pulse of erasing is repeated, until finally determining that all erased cells are qualified in block.
Fig. 6 is the motion flow of erasing of the 1st embodiment.Controller 150 receives order of erasing and starts erase movement (S100).
Word line selection circuit 160 selects the block to be erased (S102), applies 0V (S104) to the wordline of selected block, and will be by interior
The pulse Ps that erases of the generation of portion's voltage generation circuit 190 is applied to P well 14 via N well/P well common contact section 28 (ginseng Fig. 1)
And N well 12 (S106).The pulse application circuit execution of erasing that the application of pulse Ps of erasing for example is controlled by controller 150.
Fig. 7 is the waveforms such as the pulse of erasing applied by the 1st embodiment.Each node N1~N6 and each node of Fig. 3 herein
It is identical.At node N1, when the pulse Ps that erases is applied to P well 14, the current potential of other nodes N2, N3, N5, N6 because with P well
Capacitive coupling and automatic boosting, at the end of the application for the pulse Ps that erases, the current potential of node N2, N3, N5, N6, which also drop to, erases
Preceding voltage (such as 0V).
In 1st embodiment, apply weak erase pulse Pw (S108) immediately after pulse Ps is erased in application.The weak pulse Pw that erases
It is to give specific positive electricity to P well and N well via N well/P well common contact section 28 in the same manner as when pulse Ps is erased in application
Position, and the control grid for selecting block (selection wordline) is set as 0V.The weak difference for erasing the pulse Pw and pulse Ps that erases exists
In, make the current potential that P well is given lower than erase when.Moreover, it is short than the pulse Ps that erases during the weak pulse Pw that erases, during this period
For the size that will not carry out electronics release from floating grid towards silicon substrate side.
When erasing, give sufficient high voltage to P well 14, and control grid be set as 0V, as a result, floating grid just under
The oxidation film of side becomes high electric field, there is the tunnel current of electronics from floating grid towards the flowing of silicon substrate side.The weak pulse Pw that erases will
The potential setting that P well 14 is given is obtained it is lower, in order to avoid flowing has tunnel current from floating grid towards the electronics of silicon substrate side.
The shorter the pulse spacing Ts that the pulse Ps that erases applies when applying another pulse immediately later the better.Such as, it may be desirable to, it smears
Except the pulse spacing Ts of pulse Ps and the weak pulse Pw that erases were set as within 0.5 second.
After the weak pulse Pw that erases applies, whether carrying out the threshold value for detecting erased cell, to be that particular value is below erase
The reading (S110) of verification.It is carried out under the bias condition verified be in common reading operation of erasing.If erased cell is spy
Threshold value is determined hereinafter, then determining qualification, therefore the application for pulse of erasing terminates.If erased cell is specific threshold or more, determine
Unqualified (S112) generates the pulse Ps that erases that Δ V is increased to the previous voltage for erasing pulse Ps at this time, and will erase pulse Ps
It is applied to selection block.The voltage of the weak pulse Pw that erases can also be fixed always, but when the voltage for the pulse Ps that erases increases, can also
Correspondingly, it is generated in a manner of than previous big Δ V.
Then cooperation Fig. 8 illustrates the movement of erasing of the 2nd embodiment of the invention, during the application for the pulse Ps that erases, from
Floating grid discharges electronics to silicon substrate, and the potential setting of pulse is made to change.P well 14 is given that is, being reduced from midway
The current potential given.During this period, the wordline of block is selected still to be fixed to 0V.By reducing the current potential of P well 14, thus in fact with the 1st
Same when applying, to reduce the potential difference of P well 14 Yu control gate interpolar, and electronics will not be tunneling to silicon substrate side from floating grid
Mode set the current potential of the weak pulse Pw that erases.2nd embodiment is visual are as follows: it is unlimited system the 1st embodiment erase pulse Ps with
The pulse spacing Ts of the weak pulse Pw that erases and be set as zero.
Then cooperation Fig. 9 illustrates that the movement of erasing of the 3rd embodiment of the invention makes P during the application for the pulse Ps that erases
Well 14 and the potential difference of control gate interpolar change since halfway, but from 2 embodiment when is different, do not change and give to P well
Current potential.That is, giving the weak pulse of erasing of specific positive potential by the wordline (control grid) to selection block in the present embodiment
Pw, thus, to reduce the potential difference of P well Yu control gate interpolar, and electronics will not be from the tunneling side to silicon substrate side of floating grid
Formula, to set current potential and the period of the weak pulse Pw that erases given to control grid.The weak pulse Pw that erases is restored to the opportunity of 0V
The opportunity for being restored to 0V with the pulse Ps that erases is roughly equal.
Then illustrate to apply the reasons why weak pulse Pw that erases improves reliability after the pulse Ps that erases applies.Such as Figure 10 institute
Show, when applying 0V to control grid 300, to the application of P well 14 erase pulse Ps when, to the tunneling oxygen immediately below floating grid 310
Change film 320 and be applied with high voltage, electronics flow to silicon substrate side from floating grid 310 using tunneling effect as a result,.As a result,
At the end of erasing, floating grid 310 has positive charge.As shown in figure 11, the electronics for reaching silicon substrate becomes high-energy, generates high
The hole of energy, part of it are injected into oxidation film 320.
Figure 12 be by existing method apply erase postimpulse memory unit threshold value become 0V or less when energy band diagram.
For being injected into the hole of oxidation film 320 when pulse of erasing applies, if floating grid when P well 14 being then set as 0V
310 have positive charge, then floating grid 310 relatively has positive potential relative to silicon face due to the charge.Then, it is present in
(Poole-Frank (Pool- is slowly moved towards silicon substrate side due to the own electric field in oxidation film in hole in oxidation film 320
Frenkel) electric current: referring to paper).The a part for reaching the hole of silicon interface is oxidized film capture (trap) and generates interface energy
Rank is (referring to paper；" IEEE nuclear science transactions (IEEE TRANSACTIONS ON NUCLEAR SCIENCE) ", VOL.55,
The 6th row of right column of NO.4, pp.1833-1853,2008.p.1836).When reader check, P well is fixed to 0V, and wordline becomes 0V
Or specific positive potential, therefore the phenomenon that hole is mobile towards silicon interface side, is constant.In this way, erasing in existing mode of erasing
During after pulse application, hole is mobile to silicon interface and forms interface energy rank (interface state).This situation and utilization
Situation illustrated by previous Fig. 4 is same.
On the other hand, in the present embodiment, the application for the pulse Ps that followed by erases and apply the weak pulse Pw that erases.Figure 13 is indicated
Energy band diagram at this time.When giving the positive potential of the weak pulse Pw that erases to P well 14, the current potential of floating grid 310 becomes to be above silicon
Surface.Then, during the application for the pulse Ps that erases, the hole of oxidation film 320 is injected into due to oxidation film electric field towards floating
310 side of grid is mobile.Hole will not be gathered near silicon interface as a result, and hole is difficult to be captured near silicon interface, it is also difficult to
Form silicon interface energy rank.Therefore, the deterioration of the reliability of memory unit is inhibited.
Then cooperation Figure 14 illustrates the 4th embodiment of the invention.In 1st to the 3rd embodiment, will erase pulse Ps with immediately following in
This weak pulse Pw that erases is set as 1 group, then carries out verification of erasing, but the present embodiment be by the application for the pulse Ps that erases with erase
Verification is set as 1 group, after being determined as qualification by verification of erasing, applies the weak pulse Pw that erases.In Figure 14, from step S200 to step
Sequence (sequence) until rapid S206, with the step S100 to step S106 shown in the 1st to the 3rd embodiment from Fig. 6
Until it is same, and the description is omitted.In 4th embodiment, after the application for the pulse Ps that erases, verification reading of erasing is carried out
(S208).If the threshold value of a part of erased cell does not fully decline and is judged as unqualified (S210), previous smear is generated
Except erasing pulse Ps (S212) for pulse Ps+ Δ V, apply this again and erase pulse Ps (S206), carries out verification reading of erasing
(S208).When selecting all erased cell qualifications in block, finally apply the weak pulse Pw that erases.Apply the weak pulse Pw that erases
When bias condition with the 1st to 3 embodiment when it is same, in such a way that electronics will not be discharged from floating grid to silicon substrate side and
Setting.In case of the present embodiment, by applying the weak pulse Pw that erases, it also can produce following effect, that is, hole is made to jump
(hopping) inhibits the hole trap (hole trap) on silicon interface, to be difficult to form silicon interface energy to floating grid side
Rank.
In 1st to the 3rd embodiment, instantiates and be two-dimensionally formed with memory unit array in silicon substrate
NAND quick-flash memory, but it is suitable for dimensionally it is formed with smearing for the NAND quick-flash memory of memory unit array
It removes.
In the memory unit array of three-dimensional structure, there are two types of structures for tool.It, will one is channel part is erected into vertical pillar
Grid level in a manner of being wrapped channel part is placed, and is laminated into multistage.Another kind is that channel part is the rodlike of level,
Be laminated into multistage, and gate vertical extend.Joint project is that channel part is not formed at the P well being set on N well
It is interior.
As shown in figure 15, rodlike channel part 30 is formed on the surface of the substrate.Channel part 30 is for example comprising the polycrystalline of p-type
Silicon.In a manner of surrounding the periphery of channel part 30, formed memory unit control grid 32-1,32-2 ... 32-n.In control gate
Pole 32-1,32-2 ... between 32-n and channel part 30, it is formed with to sandwich with silicon oxide layer and (sandwich) oxygen of silicon nitride film
Compound-Nitride Oxide (Oxide-Nitride-Oxide, abbreviation ONO) structure 34, silicon nitride film is as charge accumulation layer
It functions.One of end side in channel part 30 is formed with the selection gate 36 of bit line selection transistor, another
A end side is formed with the selection gate 38 of source electrode line selection transistor.When passing through 36 bit line options crystal of selection gate
When pipe is connected, channel part 30 is electrically connected to bit line contact portion 40, leads when by 38 source electrode line selection transistor of selection gate
When logical, channel part 30 is electrically connected to source line contact portion 42.Therefore, as shown in Figure 16 (A), Figure 16 (B), when erasing to logical
When high voltage is given in road portion 30, apply the arteries and veins of erasing of high voltage to bit line contact portion 40, source line contact portion 42 in moment t1
Ps is rushed, then, in moment t2, the potential setting of the selection gate 36,38 of the both ends or one end of cell array must be lower than and erased
Generated hole is injected into unit battle array so that the channel part 30 near selection gate be made to generate hole by the current potential of pulse Ps
The entire channel part of column.Entire channel part becomes high voltage as a result, if control grid 32 is set as 0V, by electronics from charge
Accumulating layer 34 is drawn to channel part 30 (referring to paper；Y.Fukuzumi et al., 2007, " IEEE International Electro element meeting
(Proc.of IEEE International Electron Device Meeting)"Proc.pp.449-452).Following table
Show and is applicable in the 5th to the 7th embodiment of the invention using the NAND quick-flash memory of three-dimensional element.
It,, will be to channel part in the memory unit of three-dimensional structure in the same manner as the 1st to the 3rd embodiment in 5th embodiment
The high voltage of application is set as the pulse Ps that erases, and applies the weak pulse Pw that erases immediately after the pulse Ps that erases applies, then carries out
Whether the threshold value for detecting erased cell is that particular value verification below of erasing is read.
Figure 17 indicates to carry out the waveform of pulse of erasing of the 5th embodiment applied when erasing etc..5th embodiment corresponds to the
1 embodiment applies the weak pulse Pw that erases immediately after pulse is erased in application.In three-dimensional element, channel part 30 will be applied
High voltage be set as the pulse Ps that erases, apply the weak pulse Pw that erases immediately after the application for the pulse Ps that erases, then, with the 1st
It is same when embodiment, carry out whether the threshold value for detecting erased cell is that particular value verification below of erasing is read (referring to figure
6).If threshold value be particular value hereinafter, if the erase application of pulse Ps therefore terminates, if threshold value to be more than particular value, again
Erase pulse Ps application and the application immediately following the weak pulse Pw that erases in this.When the weak pulse Pw that erases applies, with will not
Flowing has from charge accumulation layer 34 towards the mode of the tunnel current of the electronics of silicon side, the potential setting that will be given to channel part 30
It obtains shorter.Erase apply after the application of pulse Ps immediately it is another it is weak erase pulse Pw when pulse spacing Ts it is more shorter better.Such as
Pulse spacing Ts is in 0.5 second.
Then cooperation Figure 18 illustrates the 6th embodiment of the invention.6th embodiment is same as the 2nd embodiment, in three-dimensional element
In, to channel part 30 apply erase pulse Ps during, change potential setting since halfway.That is, since halfway
Reduce the current potential applied to channel part 30.At this point, the still fixed 0V of the wordline of selection block.By reducing the current potential of channel part 30,
To which as described above, to reduce channel part 30 and control the potential difference between grid 32, and electronics will not be from charge accumulation layer
The 34 tunneling modes to channel part 30, to set the current potential given to control grid 32.
Next cooperation Figure 19 illustrates the 7th embodiment of the invention.7th embodiment and the 3rd embodiment are again it is in arteries and veins of erasing
It rushes during the application of Ps, changes potential setting since halfway, the current potential given to channel part 30 is constant, to selection block
Control grid 32 apply specific positive potential, thus as described above, to reduce channel part 30 and control the current potential between grid 32
Difference, and electronics will not be from the tunneling mode to channel part 30 of charge accumulation layer 34, to set the current potential given to control grid 32.
In addition, the 5th to the 7th embodiment is as shown in fig. 6, the pulse Ps and weak pulse Pw that erases that will erase is set as 1 group
Apply, then carries out verification of erasing, but the 5th to the 7th embodiment can also be as the 4th embodiment (referring to Fig.1 4), by arteries and veins of erasing
It rushes the application of Ps and verification of erasing is set as 1 group, after the threshold value of all erased cells in selection block is determined qualification, apply
The weak pulse Pw that erases.
Then illustrate the 8th embodiment of the invention.1st to the 7th embodiment be using NAND quick-flash memory as object, but this
Invention is also applied for NOR flash memory.The cell array of NOR flash memory is to be independently accessing (access) in array
The mode of the memory unit arranged to shape is connected in parallel to each memory unit respectively between bit line and source electrode line.Figure 20 table
Show the architectural overview cross-sectional view of NOR type cell array, in figure, for structure identical with NAND type cell array shown in FIG. 1
Mark identical reference number.
In NOR type flash memory, unlike NAND type, data write-in is to be injected into the thermoelectron on channel surface
Charge accumulation layer (floating grid), and identical with NAND type is that it is that will control grid 20A to be set as 0V that data, which are erased, to P well 14
Apply high voltage, keeps electronics tunneling to silicon side from charge accumulation layer.Therefore, the 8th embodiment is implemented according to the described the 1st to the 4th
Example applies the pulse Ps that erases, applies the weak pulse Pw that erases immediately later when the data for selected memory unit of erasing, by
This, inhibits the hole trap of the silicon interface of NOR type memory unit, enables silicon interface rank to be difficult to be formed, so as to reduction factor evidence
Deteriorated reliability caused by rewriting.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (12)
1. a kind of data erasing method of Nonvolatile semiconductor memory device, which is characterized in that the nonvolatile semiconductor
Storage device is formed with memory unit, and the memory unit includes control grid, charge accumulation layer and passage area, the data
Erasing method includes:
The control grid is kept constant voltage, apply high voltage to the passage area first is erased pulse, thus
Electronics is discharged to the passage area from the charge accumulation layer, and the control grid is remained into the fixed voltage,
Low the first weak pulse punching of pulse that voltage is erased than described first is applied to the passage area；And
Pulse is being erased by described first and first weak pulse punching is set as 1 group and after applying, carries out verification of erasing, with judgement
Data erase it is qualified or not,
Wherein, when determining that the data erase unqualified, the control grid is kept constant voltage, to the channel region
Domain applies voltage and erases that pulse is big second to erase pulse than described first, thus from the charge accumulation layer make electronics discharge to
After the passage area, the control grid is remained into the fixed voltage, pulse that voltage is erased than described second is low
The punching of second weak pulse is applied to the passage area, wherein the voltage of second weak pulse punching is greater than or equal to first weak pulse
Punching.
2. the data erasing method of Nonvolatile semiconductor memory device according to claim 1, which is characterized in that described
First weak pulse punching be erase from described first pulse application after, during fixation within apply.
3. the data erasing method of Nonvolatile semiconductor memory device according to claim 1, which is characterized in that in institute
State first erase pulse application during, apply first weak pulse by reducing the peak value that described first erases pulse
Punching.
4. the data erasing method of Nonvolatile semiconductor memory device according to any one of claim 1 to 3, special
Sign is, the first weak pulse punching is will not generate electronics release from the charge accumulation layer towards the passage area big
It is small.
5. a kind of data erasing method of Nonvolatile semiconductor memory device, which is characterized in that the nonvolatile semiconductor
Storage device has memory unit, and the memory unit includes that control grid, charge accumulation layer and passage area, the data are smeared
Except method includes:
The control grid is kept constant voltage, apply high voltage to the passage area first is erased pulse, thus
Discharge electronics to the passage area from the charge accumulation layer, described first erase pulse application during, will
Voltage erase than described first pulse it is low the first weak pulse punching be applied to the control grid；And
Pulse is being erased by described first and first weak pulse punching is set as 1 group and after applying, carries out verification of erasing, with judgement
Data erase it is qualified or not,
Wherein, when determining that the data erase unqualified, the control grid is kept constant voltage, to the channel region
Domain applies voltage and erases that pulse is big second to erase pulse than described first, thus from the charge accumulation layer make electronics discharge to
After the passage area, described second erase pulse application during, pulse that voltage is erased than described second it is low
The punching of two weak pulses is applied to the passage area, wherein the voltage of second weak pulse punching is rushed more than or equal to first weak pulse.
6. a kind of Nonvolatile semiconductor memory device characterized by comprising
Memory unit array, is formed with memory unit, and the memory unit includes control grid, charge accumulation layer and channel region
Domain；
Alternative pack, selection should erase the memory unit of data from the memory unit array；And
Control unit is erased to the data by the selected memory unit of the alternative pack and is controlled,
Wherein, the control grid is kept constant voltage by the control unit, applies high voltage to the passage area
First erases pulse, thus discharges electronics to the passage area from the charge accumulation layer, and the control grid is protected
It holds as the fixed voltage, low the first weak pulse punching of pulse that voltage is erased than described first is applied to the passage area,
The control unit is erasing pulse for described first and first weak pulse punching is set as 1 group and after applying, is smeared
Except verification, with determine data erase it is qualified or not,
Wherein, when determining that the data erase unqualified, the control grid is kept constant voltage by the control unit,
Voltage is applied to the passage area and erases than described first that pulse is big second to erase pulse, thus from the charge accumulation layer
Discharge electronics to the passage area, the control grid is remained the fixed voltage by the control unit, will be electric
Described in pressure ratio second erase pulse it is low the second weak pulse punching be applied to the passage area, wherein second weak pulse punching voltage
It is rushed more than or equal to first weak pulse.
7. Nonvolatile semiconductor memory device according to claim 6, which is characterized in that the control unit is from institute
State first erase pulse application after, during fixation within apply first weak pulse punching.
8. Nonvolatile semiconductor memory device according to claim 6, which is characterized in that the control unit is described
First erase pulse application during, rushed by reducing the peak value that described first erases pulse to apply first weak pulse.
9. Nonvolatile semiconductor memory device according to claim 6, which is characterized in that the weak pulse punching is will not to produce
The size of the raw electronics release from the charge accumulation layer towards the passage area.
10. Nonvolatile semiconductor memory device according to claim 6, which is characterized in that the memory unit array
With the anti-and string being connected in series by multiple memory units, wherein the alternative pack is selected from the memory unit array
Select block, the control unit applies described first to selected block and erases pulse and first weak pulse rushes.
11. Nonvolatile semiconductor memory device according to claim 6, which is characterized in that the memory unit array
With the anti-and string being connected in series by multiple memory units, wherein the alternative pack is selected from the memory unit array
Select block, the control unit applies described first to selected block and erases pulse, and erases pulse described first
During application, first weak pulse is applied to the control grid of the memory unit in the selected block and is rushed.
12. a kind of Nonvolatile semiconductor memory device characterized by comprising
Memory unit array, is formed with memory unit, and the memory unit includes control grid, charge accumulation layer and channel region
Domain；
Alternative pack, selection should erase the memory unit of data from the memory unit array；And
Control unit is erased to the data by the selected memory unit of the alternative pack and is controlled,
Wherein, the control grid is kept constant voltage by the control unit, applies high voltage to the passage area
First erases pulse, thus discharges electronics to the passage area from the charge accumulation layer, erases arteries and veins described first
During the application of punching, low the first weak pulse punching of pulse that voltage is erased than described first is applied to the control grid,
The control unit is erasing pulse for described first and first weak pulse punching is set as 1 group and after applying, is smeared
Except verification, with determine data erase it is qualified or not,
Wherein, when determining that the data erase unqualified, the control grid is kept constant voltage by the control unit,
Voltage is applied to the passage area and erases than described first that pulse is big second to erase pulse, thus from the charge accumulation layer
Discharge electronics to the passage area, described second erase pulse application during, the control unit is by voltage
Low the second weak pulse punching of pulse of erasing than described second is applied to the passage area, wherein the voltage of second weak pulse punching is big
In or equal to first weak pulse punching.
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Citations (3)
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|---|---|---|---|---|
| US5191551A (en) * | 1990-11-30 | 1993-03-02 | Nec Corporation | Non-volatile semiconductor memory device with transistor paralleling floating gate transistor |
| CN1902711A (en) * | 2003-10-29 | 2007-01-24 | 赛芬半导体有限公司 | Method, system and circuit for programming a non-volatile memory array |
| CN101414483A (en) * | 2007-08-20 | 2009-04-22 | 三星电子株式会社 | Program and erase methods for nonvolatile memory |
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| US6894931B2 (en) * | 2002-06-20 | 2005-05-17 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5191551A (en) * | 1990-11-30 | 1993-03-02 | Nec Corporation | Non-volatile semiconductor memory device with transistor paralleling floating gate transistor |
| CN1902711A (en) * | 2003-10-29 | 2007-01-24 | 赛芬半导体有限公司 | Method, system and circuit for programming a non-volatile memory array |
| CN101414483A (en) * | 2007-08-20 | 2009-04-22 | 三星电子株式会社 | Program and erase methods for nonvolatile memory |
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