CN105974446A - Low-power-consumption digital frequency synthesis method capable of being applied to satellite navigation - Google Patents
Low-power-consumption digital frequency synthesis method capable of being applied to satellite navigation Download PDFInfo
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- CN105974446A CN105974446A CN201610250448.8A CN201610250448A CN105974446A CN 105974446 A CN105974446 A CN 105974446A CN 201610250448 A CN201610250448 A CN 201610250448A CN 105974446 A CN105974446 A CN 105974446A
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- frequency
- system clock
- satellite navigation
- road
- local oscillation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/24—Acquisition or tracking or demodulation of signals transmitted by the system
- G01S19/29—Acquisition or tracking or demodulation of signals transmitted by the system carrier including Doppler, related
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- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Position Fixing By Use Of Radio Waves (AREA)
- Circuits Of Receivers In General (AREA)
- Radio Relay Systems (AREA)
Abstract
The invention relates to a low-power-consumption digital frequency synthesis method capable of being applied to satellite navigation. The method provided by the invention can generate 1-bit quantization accuracy orthogonal local oscillation signals, can be applied to a satellite signal capturing and tracking circuit so as to complete digital frequency mixing, and belongs to the technical field of satellite navigation. The core idea of the method is that the 1-bit quantization accuracy local oscillation signals (I-path signals) are acquired through carrying out cyclic shift on 0011, system clock time delay is carried out on the I-path signals so as to acquire Q-path output; and in order to realize frequency control, the method provided by the invention realizes frequency control through a method of supplementing a 1 or 0 into a repetitive 0011 sequence at regular intervals.
Description
Technical field
The present invention relates to a kind of low power consumption digital frequency combining method that can be used for satellite navigation, belong to satellite and lead
Boat technical field.
Background technology
Digital frequency synthesizer (hereinafter referred to as DDFS) is the Important Circuit in satellite navigation receiver chip,
Can be that satellite signal acquisition is followed the tracks of circuit and provided frequency controlled orthogonal local carrier signal.
Tradition DDFS stores sinusoidal wave sampled value in memory, and makes the address of memorizer with sinusoidal wave
Phase place corresponding.Phase accumulator continuous cumulative frequency control word produces sine wave phase, according to different
Phase place, takes out corresponding sampled value to realize Digital Frequency Synthesize.
When frequency resolution demand is higher, DDFS needs the biggest memory space to store the sampled value of sine wave,
Therefore power consumption and area that satellite navigation receiver chip is bigger can be caused.Although there being a lot of algorithm can be direct
Calculate the sampled value of sine wave according to phasometer, to realize the DDFS of no memory, thus reduce power consumption and become
This, but combine the concrete application of satellite navigation receiver, and no memory DDFS can also be at power consumption and cost
Upper continuation optimizes.
Satellite navigation receiver main circuit to be made up of RF receiving circuit and numeral baseband processing circuitry.Satellite
First navigation radio circuit receives and amplifies radiofrequency signal, and is mixed it and filters, and obtains intermediate frequency letter
Number, then after intermediate-freuqncy signal digitized, send digital baseband circuit to, digital baseband circuit satellite is believed
Number carry out acquisition and tracking and navigator fix calculates.
On market, the satellite navigation chip of main flow is all set as 4.092MHz, quantified precision digital medium-frequency signal
Being 1 or 1.5, sample frequency is 16.368MHz.Acquisition and tracking algorithm needs carry out digital mixing,
I.e. it is multiplied with the local oscillation signal that intermediate-freuqncy signal and two-way are mutually orthogonal.Through the mathematics of acquisition and tracking algorithm is imitated
True and optimization shows, above-mentioned digital mixing can use the local oscillation signal of 1 quantified precision, and this is low-power consumption
The design of satellite reception chip provides the space of optimization further.
When using the digital local oscillator signal of above-mentioned 16.368MHz system clock frequency synthesis 4.092MHz, by
Frequency ratio in system clock frequency Yu composite signal is 4, so the digital local oscillator signal of 1 quantified precision will
Change in quality into the repetition of " 0011 " sequence；(lead according to satellite when needing and synthesizing the frequency near 4.092MHz
Boat principle, peak frequency excursion is positive and negative 10KHz), digital local oscillator the most above-mentioned " 0011 "
The repetition of sequence, but owing to the frequency ratio of system clock frequency Yu composite signal is not strict 4, so needing
At a certain time interval certain " 0011 " is mended one " 1 " (when synthesis is less than 4.092MHz frequency),
Or cut out one " 1 " (when synthesis is higher than 4.092MHz frequency).
Owing to the frequency ratio of 16.368MHz system clock frequency Yu 4.092MHz is 4, therefore synthesize 4.092MHz
Without mending/cut " 1 "；When frequency synthesis is slightly below 4.092MHz, the cycle of composite signal will be slightly larger than 4
In the individual system cycle, through accumulation after a while, need that " 0011 " is once mended " 1 " and just can make this
Shake and composite signal re-synchronization.When frequency synthesis is slightly above 4.092MHz, one can be cut out accordingly
The operation of individual " 1 ".
Summary of the invention
The purpose of the present invention is to propose to a kind of 1 quantified precision that can be used for realizing satellite signal acquisition tracking
DDFS method, to reduce power consumption and the cost of satellite navigation reception chip further.The method is applicable to system
Clock frequency and the acquisition and tracking circuit that ratio is about 4 of composite signal frequency.
The low power consumption digital frequency combining method of 1 quantified precision for satellite navigation that the present invention proposes,
Including following steps:
(1) " 0011 " sequence loops is moved to right, export as orthogonal local oscillation I road with lowest order, and to circulation time
Counting number obtains M, enters step (2) when M is more than N；
(2) when frequency synthesis is higher than 1/4 system clock frequency, just " 001 " is moved to right 3 times, use
Low level exports as orthogonal local oscillation I road, and M is reset to 0, then proceedes to step (1)；Work as frequency synthesis
During less than 1/4 system clock frequency, just " 00111 " is moved to right 5 times, with lowest order as orthogonal
Shake the output of I road, and M is reset to 0, then proceed to step (1)；
(3) output of above-mentioned I road is carried out 1 system clock time delay, obtain the output of orthogonal local oscillation Q road.
In said method, N is that system clock frequency is divided by 16 times of Δ f.Wherein Δ f is the frequency and 1/4 of synthesis local oscillator
The absolute value of system clock frequency difference.
The low power consumption digital frequency combining method for satellite navigation that the present invention proposes, compared with prior art,
Owing to using the method " 0011 " sequence periodically being mended/being cut " 1 " to produce local oscillation signal, do not use memorizer,
So not reading to memory data data, it is possible to reduce chip power-consumption and area.Due to satellite navigation
During need to follow the tracks of the satellite-signal of about 10, it is therefore desirable to a lot of DDFS, reduce the power consumption of DDFS
And area, the present invention has important practical to the receiver chip of design low cost low-power consumption and is worth.
Detailed description of the invention:
The low power consumption digital frequency combining method for satellite navigation that the present invention proposes, can produce digital local oscillator
Signal, in the digital mixing circuit of satellite navigation signals acquisition and tracking circuit.Below with system clock frequency
Rate is 16.368MHz, digital intermediate frequency frequency is 4.092MHz, and local oscillation signal is centered by 4.092MHz, frequently
As a example by rate variance is Δ fHz (Δ f is less than positive negative 10KHz), introduce the detailed description of the invention of the present invention.By
Verilog language can be used to carry out in Design of Digital Circuit, so detailed description below has only to
The duty providing circuit describes and redirects condition.
The work of this circuit is segmented into 3 duties:
State 1 (cyclic shift state): carry out " 0011 " sequence cyclic shift (moving to right), and lowest order
Regard the I road output of orthogonal local oscillation as；Often complete once to circulate whether observation M is more than 1023000, if not
Just M is added Δ f, if being put into mending one state (when frequency synthesis is less than 4.092MHz) or cutting " 1 "
State (when frequency synthesis is higher than 4.092MHz), and clear for M 0；
State 2 (benefit one state): carry out " 00111 " sequence and move to right 5 times, and lowest order is regarded as orthogonal
The I road output of local oscillator, then returnes to cyclic shift state (state 1)；
State 3 (section one state): carry out " 001 " sequence and move to right 3 times, and lowest order is regarded as orthogonal
The I road output shaken, then returnes to cyclic shift state (state 1).
I road signal is carried out the time delay of a kind of system clock, orthogonal Q road local oscillation signal can be produced.
Claims (2)
1. the low power consumption digital frequency combining method for satellite navigation, it is characterised in that the method includes following
Each step:
(1) " 0011 " sequence loops is moved to right, export as orthogonal local oscillation I road with lowest order, and to following
Ring counting how many times obtains M, enters step (2) when M is more than N；
(2) when frequency synthesis is higher than 1/4 system clock frequency, just " 001 " is moved to right 3 times, use
Lowest order exports as orthogonal local oscillation I road, and M is reset to 0, then proceedes to step (1)；When synthesis frequency
When rate is less than 1/4 system clock frequency, just " 00111 " is moved to right 5 times, with lowest order as orthogonal
Local oscillator I road exports, and M is reset to 0, then proceedes to step (1)；
(3) the I road output producing above-mentioned 2 steps carries out 1 system clock time delay, obtains orthogonal
Shake Q road output.
2. in said method, N is that system clock frequency is divided by 16 times of Δ f.Wherein Δ f be synthesis local oscillator frequency with
The absolute value of 1/4 system clock frequency difference.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610250448.8A CN105974446A (en) | 2016-04-16 | 2016-04-16 | Low-power-consumption digital frequency synthesis method capable of being applied to satellite navigation |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610250448.8A CN105974446A (en) | 2016-04-16 | 2016-04-16 | Low-power-consumption digital frequency synthesis method capable of being applied to satellite navigation |
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| Publication Number | Publication Date |
|---|---|
| CN105974446A true CN105974446A (en) | 2016-09-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610250448.8A Pending CN105974446A (en) | 2016-04-16 | 2016-04-16 | Low-power-consumption digital frequency synthesis method capable of being applied to satellite navigation |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109889197A (en) * | 2019-03-11 | 2019-06-14 | 电子科技大学 | Multichannel coherent frequency synthesizer circuit based on linear frequency modulation continuous wave |
| CN112596087A (en) * | 2021-03-04 | 2021-04-02 | 长沙海格北斗信息技术有限公司 | FIR digital filtering method for satellite navigation, navigation chip and receiver |
-
2016
- 2016-04-16 CN CN201610250448.8A patent/CN105974446A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109889197A (en) * | 2019-03-11 | 2019-06-14 | 电子科技大学 | Multichannel coherent frequency synthesizer circuit based on linear frequency modulation continuous wave |
| CN109889197B (en) * | 2019-03-11 | 2021-05-14 | 电子科技大学 | Multi-path coherent frequency synthesis circuit based on linear frequency modulation continuous waveform |
| CN112596087A (en) * | 2021-03-04 | 2021-04-02 | 长沙海格北斗信息技术有限公司 | FIR digital filtering method for satellite navigation, navigation chip and receiver |
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| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160928 |