CN105956250A

CN105956250A - Graphical interface-based integrated circuit SoC (System on a Chip) design fast connecting method

Info

Publication number: CN105956250A
Application number: CN201610267321.7A
Authority: CN
Inventors: 孙建伟; 朱昱; 杨军; 袁本荣
Original assignee: Beijing Core Leather Electronic Technology Co Ltd
Current assignee: Beijing Core Leather Electronic Technology Co Ltd
Priority date: 2016-04-27
Filing date: 2016-04-27
Publication date: 2016-09-21

Abstract

The invention provides a graphical interface-based integrated circuit SoC (System on a Chip) design fast connecting method, which comprises the following steps of 1, obtaining the graphical representation of an IP (Internet Protocol) core, wherein the graphical representation includes a bus interface and a special interface of the IP core; (2) putting the IP core required for designing the SoC in an integrated circuit SoC design schematic graph; and (3) when a certain interface of a certain IP core needs to be interconnected with an interface of another IP core, and performing highlight or color-change display on the interface corresponding to another IP, wherein the corresponding interfaces are the interfaces of the same type, only the corresponding interfaces are mutually connected during connection, and the connection realization is a simple straight line on a graph. By adding an automatic wire distribution function, the connected straight line is changed into a horizontal vertical connecting line capable of bypassing the IP core graph. The method has the advantages that the connecting speed can be accelerated; errors during the connection are greatly reduced; the straight line can be used for connection, so that the connection realization of the schematic graph can be accelerated; and the automatic wire distribution function is added, so that the schematic graph is clear and attractive.

Description

A kind of integrated circuit system-on-chip designs Speediness link line method based on graphical interfaces

Technical field

The present invention relates to integrated circuit electronic design automation (EDA) technical field, more particularly, it relates to a kind of integrated circuit system-on-chip designs Speediness link line technology based on graphical interfaces.

Background technology

At present, the design of integrated circuit is broadly divided into design and SOC(system on a chip) based on IP kernel (SoC) design of two big classes, i.e. IP core (IP kernel).The structure of SoC is extremely complex, and door number is huge.The design of SoC chip at present typically uses modular mode, i.e. assembles System on Chip/SoC based on existing IP kernel.These IP kernels include CPU, memorizer, analog circuit, commissure logic, I/O interface etc..The design process of SoC is exactly the searching of IP, the process of form, fit, and function checking.IP therein is probably the IP of enterprises, it is also possible to third-party IP.Along with intelligence system, the development of Internet of Things, the application demand of SoC rapidly increases, application variation, and market periods is short, and the design verification accelerating SoC is a very important problem of integrated circuit fields.

The line of IP kernel is the important step of SoC design based on IP kernel, and general line has two ways, i.e. based on hand-written register transfer level circuit (RTL) code text mode, is called for short text mode；Another kind is connected mode based on graphical interfaces, is called for short graphics mode, or schematic diagram is drawn.For a complicated SoC design, the line between IP module may have thousands of bar, either text mode or schematic diagram mode, it is the most careful to be required for, the mistake that this line stage introduces can cause follow-up emulation, authentication error, even results in the failure of whole design.Can try one's best the interconnection quickly realized between IP kernel, reduce the important technology that Miswire is SoC design automatization the most as far as possible.

Summary of the invention

It is an object of the invention to provide a kind of Speediness link line technology based on graphical interfaces, for SoC design, accelerate the interconnection between IP kernel, reduce Miswire

For achieving the above object, the technical scheme is that

A kind of integrated circuit system-on-chip designs Speediness link line method based on graphical interfaces, it is characterised in that described Speediness link line method includes step:

1) figure obtaining IP kernel represents, described figure represents the EBI and particular interface comprising IP kernel；

2) in integrated circuit SOC(system on a chip) design principle figure, the IP kernel required for design SoC is placed；

3) need when certain interface of certain IP kernel and during the interface interconnection of other IP kernel, then by highlighted for corresponding for other IP interface or variable color show, described corresponding interface is the interface of same type, only by corresponding interface interconnection during connection；The realization connected is a simple straight line on figure.

Described EBI includes IEEE and user-defined EBI；Described IEEE includes AHB system bus and APB peripheral bus；Described particular interface is the interface being not defined as EBI.

In described step 3, after corresponding interface straight line connects, add self routing function, the straight line connected is become the horizontal vertical line that can walk around IP kernel figure.

Described self routing function uses Star Algorithm or labyrinth algorithm.

The integrated circuit system-on-chip designs Speediness link line method based on graphical interfaces of the present invention, the speed that can accelerate to connect, error when can greatly reduce connection；Owing to can connect with straight line, also can acceleration principle figure connection realize；It is attractive in appearance that addition self routing function makes schematic diagram become apparent from.

Accompanying drawing explanation

The figure of Fig. 1: IP kernel represents；

Fig. 2 shows the connection between IP kernel；

Before Fig. 3 shows self routing, the AHB_a port of IP1 is connected with the AHB_c port straight line of IP3；

After Fig. 4 shows self routing, the AHB_a port of IP1 is connected with horizontal vertical line with the AHB_c port of IP3.

Detailed description of the invention

For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with the drawings and specific embodiments, the present invention is described in more detail.

1, the figure obtaining IP kernel represents, as shown in Figure 1.This figure represents the EBI and particular interface comprising IP kernel.EBI includes IEEE, such as AHB (Advanced High performance Bus) system bus and APB (Advanced Peripheral Bus) peripheral bus, and user-defined EBI.Particular interface is the interface being not defined as EBI.The present invention does not also include how that this figure realizing IP kernel represents.Multiple physical ports that the possible corresponding IP kernel RTL of bus interior interface realizes.Interconnection between IP kernel based on figure is exactly mainly the interconnection between substantial amounts of EBI and the interconnection of a small amount of particular interface.

2, placing the IP kernel required for design SoC in schematic diagram, when certain interface of certain IP kernel needs the interface interconnection with other IP kernel, then corresponding for other IP interface is highlighted or variable color shows, only has corresponding interface can interconnect, as shown in Figure 2 during connection.So-called corresponding interface, it is simply that refer to the interface of same type, such as AHB corresponding A HB, APB corresponding A PB, particular interface correspondence particular interface.Fig. 2 shows the connection between IP kernel；The named AHB_a of AHB port of IP1；The named AHB_b of AHB port of IP2；The named AHB_c of AHB port of IP3；When the ahb bus port AHB_a of IP1 to interconnect with the bus port of other IP, the ahb bus port AHB_b of IP2 is highlighted, and the ahb bus port AHB_c of IP3 is highlighted.

Due to EBI may multiple physical ports of corresponding RTL, therefore connecting of a pair EBI just can the physical port of corresponding tens the most up to a hundred connect, and can accelerate the speed of connection.Owing to defining that only corresponding interface could connect, and can greatly reduce error during connection.The realization connected can be a simple straight line on figure, as shown in Figure 3.Owing to can connect with straight line, also can acceleration principle figure connection realize.

3, after corresponding interface straight line connects, attractive in appearance in order to make schematic diagram become apparent from, self routing function can be added, this function uses Star Algorithm or labyrinth algorithm, the straight line connected is become the horizontal vertical line that can walk around IP kernel figure, as shown in Figure 4.

Particular embodiments described above; the purpose of the present invention, technical scheme and beneficial effect have been carried out further detailed description; it is it should be understood that; the foregoing is only the specific embodiment of the present invention; it is not limited to the present invention; all within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. done, should be included within the scope of the present invention.

Claims

1. an integrated circuit system-on-chip designs Speediness link line method based on graphical interfaces, it is characterised in that described Speediness link line method includes step:

Speediness link line method the most according to claim 1, it is characterised in that described EBI includes IEEE and user-defined EBI；Described IEEE includes AHB system bus and APB peripheral bus；Described particular interface is the interface being not defined as EBI.

Speediness link line method the most according to claim 2, it is characterised in that in described step 3, after corresponding interface straight line connects, add self routing function, the straight line connected is become the horizontal vertical line that can walk around IP kernel figure.

Speediness link line method the most according to claim 3, it is characterised in that described self routing function uses Star Algorithm or labyrinth algorithm.