CN105955672B

CN105955672B - Solid-state storage system and method for flexibly controlling wear leveling

Info

Publication number: CN105955672B
Application number: CN201610333979.3A
Authority: CN
Inventors: 王军辉; 霍小四
Original assignee: HENAN ZHONGTIAN YIKE ELECTRONIC SCIENCE AND TECHNOLOGY Co Ltd
Current assignee: HENAN ZHONGTIAN YIKE ELECTRONIC SCIENCE AND TECHNOLOGY Co Ltd
Priority date: 2016-05-19
Filing date: 2016-05-19
Publication date: 2019-12-06
Anticipated expiration: 2036-05-19
Also published as: CN105955672A

Abstract

The invention relates to a solid-state storage control system and a method for flexibly controlling wear leveling. The method is unified for memory cells with the goal of replacing worn out memory cells with memory modules that are not used often. The wear leveling method is performed by changing the physical location of the memory in each memory area or plane. The baseline parameters for target memory block and wear memory block erase times are used to search for the target memory module to be replaced. Therefore, when the space of the cache unit is reduced and the processing time of the wear leveling process is also reduced, the operation performance and the cost efficiency of the solid-state storage system are improved.

Description

Solid-state storage system and method for flexibly controlling wear leveling

Technical Field

the present invention relates to a solid-state storage system and method, and more particularly, to a system for flexibly controlling wear leveling and a method for performing the same.

Background

Generally, a non-vulnerable memory is widely used as a storage memory of a portable information device. In recent years, solid state disks using NAND flash memory storage are used for personal computers instead of hard disk drives, are starting to be sold in the market, and are expected to enter the HDD (hard disk drive) market by a large margin.

typically, control of data files in solid state storage systems, such as SSDs (solid state drives), is performed by writing, erasing, and updating real data in pages specified by logical addresses that identify the data files. More specifically, with the flash transport layer, a logical address can be mapped to a physical address of a data storage area. By being mapped to a logical address according to the logical address pointed to by the host command, the logical address specifies a location where data can be written, read, or erased. The physical address is the location information on the page or memory block subblock.

the NAND flash memory cell is a non-vulnerable memory cell. Therefore, when updating data of a NAND flash memory cell, the data of the corresponding cell must be erased first, and then new data can be compiled. However, data cannot be uniformly programmed into all the storage units, but is programmed into a specific unit area in a set frequently. In other words, a specific cell region or some cells are not used due to wear due to frequent data writing and erasing operations. Even further, despite the existence of completely new state memory cells, the overall performance of a solid-state memory system is still subject to worn out cells.

thus, before these memory cells are worn out, wear leveling methods are performed by changing the physical location of the memory cells within each memory area or plane to ensure that all memory cells are used uniformly. To perform the wear leveling process, the erasable times information of all the block areas is stored to the NAND memory area. When a wear leveling process needs to be performed, the erase count information of a block area is loaded into a RAM (random access memory) cache, and the block is changed by retrieving a physical location that can replace the block area.

Although, according to the current trend of large-capacity SSDs, more memory block areas can be owned as memory areas, the size of the RAM cache in which all the block erasure count information is loaded inevitably increases. In addition, increasing the RAM cache in memory is still limited by price and memory capacity.

disclosure of Invention

The invention aims to provide a solid-state storage system and a method for flexibly controlling wear leveling. The solid-state storage system is used for controlling the links and application examples of the wear leveling process; application segments and application instances for controlling the solid-state storage system method are also described.

in one embodiment of the present invention, a solid-state storage system comprises: the buffer unit can be used for sequentially loading a plurality of mapping pages which store mapping information and erasing times after being configured; a memory control for allocating a reference value for setting the erase count of the target block and the number of map pages of the object to be searched in the target block, in order to find a target block that can replace the damaged block, and executing a wear leveling program after the map pages are adopted.

In another embodiment of the present invention, a solid-state memory system includes a flash memory area including a set of memory blocks for storing mapping pages for storing mapping information and erase times, a memory controller configured to set a reference value for searching a target number of blocks to be replaced, and to replace a block in the memory that has been worn out by a wear leveling program using reference value information on a worn-out block regarding the erase times of the replacement block, find an initial replacement block as a target block, and replace the initial replacement block with a damaged block.

The present invention can also be applied to a method example, a method for controlling a solid-state storage system comprising the steps of: setting a first parameter value by determining the number of erasures during wear leveling of a target block that replaces a damaged block; setting a second parameter value by searching a target block corresponding to the damaged block erase number; in case the search for a target block between the first and second parameter values does not result, the first parameter value needs to be changed and updated in order to influence the search condition of the next target block.

A solid-state storage system of the present invention comprises: the cache unit is configured to partially load mapping pages, and each mapping page comprises mapping information and erasure number information corresponding to the storage block; configuring a storage control for searching a target block based on the accumulated failure number, the value being derived based on the number of failures to search the target block and the number of accesses to the mapped page during a previous wear leveling process; and also configured to handle a wear leveling process to replace the damaged block with the target block. In the solid-state storage system, the storage control determines: when data is erased, whether to perform a wear leveling process. The solid-state storage system described above, when the wear leveling process is executed, stores the number of the change target blocks. The solid-state storage system stores and controls the number of accumulated failure times of the search target block lifting failure, and meanwhile, the number of the target blocks is lifted according to the increased number of accumulated failure times. According to the solid-state storage system, the access times of the mapping pages are promoted in a storage control mode, and meanwhile the number of the target blocks is promoted according to the increased access times of the mapping pages. According to the solid-state storage system, when the erasing times of the damaged blocks exceed the preset value, the access times of the mapping pages are increased through storage control. In the solid-state storage system, when the access times of the mapping pages are increased, the storage control increases the number of the mapping pages loaded to the cache unit. In the solid-state storage system, the mapping pages are loaded into the cache units in order. The solid-state storage system further comprises a flash memory area containing a group storage block, wherein the group storage block contains a plurality of mapping pages.

Another solid-state storage system of the present invention comprises: the flash memory area composed of the storage blocks is used for storing a mapping page after being configured, and the mapping page stores mapping information and erasing frequency information of the storage blocks; the storage control is configured to change the number of target blocks that replace the corrupted block, the number determined by using the cumulative number of failures to search for the target block and the number of accesses to the mapped page in the wear leveling process. The above solid-state storage system, wherein the storage control increases the number of target blocks in order to increase the search success rate of the target blocks. In the solid-state storage system described above, the storage control promotes the accumulated failure number when the search for the target block fails in the previous wear leveling process. In the solid-state storage system, in order to increase the number of target blocks, the storage control increases the access times of the mapping pages. In the solid-state storage system, when the target block is successfully searched in the previous wear leveling process, the storage control reduces the accumulated failure number so as to reduce the number of the target blocks.

the invention discloses a solid-state storage system control method, which comprises the following steps: setting a first parameter value according to the accumulated failure times of the failure times of searching a single target block in the previous loss balancing process; setting a second parameter value according to the access times of the mapping page; setting a search condition of a target block according to the first and second parameter values; in the wear leveling process, a target block for replacing the damaged block is searched according to the search condition of the target block. In the solid-state storage system control method, when the accumulation failure number increases, the search condition of the target block needs to be changed. In the above-described solid-state storage system control method, the number of blocks to be searched as target blocks increases according to the changed search condition of the target blocks. In the solid-state storage system control method, when the number of access times of the mapping page increases, the search condition of the target block is changed. According to the solid-state storage system control method, when the erasing times of the damaged blocks exceed the sum of the average erasing times and the error range, the access times of the mapping pages are increased. The above-described solid-state storage system control method, the number of blocks to be searched as target blocks will be increased according to the changed search condition of the target blocks.

By implementing the invention, in connection with practical application, even when the storage space is enlarged, the space of the cache unit for temporarily storing the mapping information and the erasure number information is not required to be increased; the cache unit may be kept small compared to current technology. Only the erasure number information and the mapping information of the defective block are loaded, and the erasure number parameter value condition and the search number parameter value condition are set separately. The wear leveling process processing time may be reduced. Therefore, when the space of the cache unit is reduced and the processing time of the wear leveling process is also reduced, the operation performance and the cost efficiency of the solid-state storage system are improved.

Drawings

FIG. 1 is a block diagram illustrating an example application corresponding to a solid state storage system;

FIG. 2 is a conceptual block diagram illustrating the address mapping of FIG. 1, wherein FIG. 2(a) is a sector view, FIG. 2(b) is a NAND view, and FIG. 2(c) is a cache unit view;

FIG. 3 is a flow chart illustrating the method of FIG. 1 with respect to controlling the solids storage system;

FIG. 4 is a graph illustrating the correlation between the target block erase count and the cumulative number of failures in FIG. 3;

FIG. 5 is a table illustrating the correlation between sensitivity and the number of defective block erases in tabular form; and

fig. 6 is a graph illustrating variations in the erase count and access count of a damaged block in a graph according to the sensitivity of fig. 5.

Detailed Description

Here, application examples related to the present invention will be disclosed in detail as prescribed. It should be noted that the disclosed application examples are only examples of the present invention, and the application examples may be embodied in other forms. Therefore, specific details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in appropriately detailed manner.

A solid-state storage system and a method for controlling the same according to the present method will be described below by way of preferred application examples in the drawings.

first, a solid-state storage system according to an application example thereof will be described with reference to fig. 1 and 2. In fig. 1, a solid-state storage system 100 is shown in block diagram form, and fig. 2 illustrates, in conceptual block diagram form, the relationship between a physical/logical address mapping table and a cache unit 120. Herein, a memory system using a NAND flash memory will be considered as an application example of the solid-state memory system 100. Referring to fig. 1 and 2, the solid-state memory system includes a host interface 110, a cache unit 120, a Micro Control Unit (MCU)130, a memory control 140, and a memory area 150.

the host interface 110 is connected to the buffer unit 120, and transmits and receives control commands, address signals, and data signals between an external host and the buffer unit 120. The interface mode between the host interface 110 and the external host may be one of SATA, PATA, SCSI, Express Card, or PCI-Express, but is not limited thereto.

The signal output from the host interface 110 is buffered to the buffer unit 120, or temporarily stores mapping information between logical addresses and physical addresses, block allocation information of the memory area 150, external data, the number of block erasures, and other external data, etc. The cache unit 120 can also be used as a cache for SRAM or DRAM. As shown in fig. 2, a 1000 th sector of a logical block viewed from above represents a 30 th page in a 200 th block of a practical physical block in the NAND view of the memory area 150, and the buffer unit 120 stores mapping information and the number of times of erasing of the block actually accessed (200 th block area). The present invention is not limited to the use case of fig. 2.

In particular connection with some aspect or practical use case, the cache unit 120 does not load the erase count of all memory blocks, but only the erase count of the damaged block. Therefore, the space of the cache unit 120 does not need to be large, and the space utilization rate can be improved while the cost is reduced. The MCU 130 can transmit or receive control commands, addressing signals, or data signals to or from the host interface 110, or control the storage control 140 through these signals.

the memory control 140 selects a predetermined NAND memory among the plurality of flash memories of the memory area 150 and performs a write command, an erase command, or a read command thereon. In particular, when storage control 140 involves a need for flexible control of wear leveling processes, such as: in the wear leveling program, two parameter values are used for controlling the searching condition and the searching times of the target block, so that the purpose of uniformly managing the service life of the storage is realized.

Normally, the erasable times information of all blocks is stored on the storage area 150 of the large block flash memory. Therefore, when the wear leveling process needs to be performed, the erasure count information of all the blocks is loaded onto the cache unit 120, and then the physical addresses having the maximum erasure count block and the minimum erasure count block are exchanged. In this case, the cache unit 120 needs a storage capacity large enough to load the number of times of erasing of each block at a time. Although, when the wear leveling process is actually performed, it is highly possible that the memory control 140 does not load the erasure information of all blocks onto the cache unit 120, the wear leveling process can still be performed by sampling the predetermined condition of the block according to the search condition. In addition, in some cases, the memory control 140 increments the erase count after the memory block is erased. When the value is greater than the predetermined value, the wear leveling process is automatically performed. In this case, a value calculated with an error is used as a search condition for the block, and when there is an error between the number of erasures of the damaged block and the average number of erasures, the average number of erasures is used as a parameter for the number of searches. Thus, both the number of searches and the search conditions must be flexible. In other words, when the wear leveling course information is minimized, both search parameter values are to be set. Therefore, the number of searches is reduced, and the search probability of the substitute target block is increased.

The storage controller 140 may control the storage area 150 by performing read, write, and erase operations of data. The flash memory cells may be SLC (single level cell) or MLC (multi-level cell). The memory area 150 may be composed of multiple chips, each chip containing a plurality of blocks composed of multiple pages. Meanwhile, the memory area 150 has not only the mapping information but also the above-described erasure count information (hereinafter referred to as "mapping page"). The so-called map page is a process unit or a memory unit in the NAND flash memory. A mapping page may be defined as the number of erasures and the storage of mapping information between logical addresses and physical addresses with respect to a single block. The mapping information is also called a mapping storage area.

Fig. 3 illustrates, in flow diagram form, the method of fig. 1 for controlling a solid-state storage system. For example, it is also described that whether the wear leveling process is performed is determined by each erase command. In connection with fig. 1-3, any block of data may be erased. After the data of the block is erased, the number of times of this erasing is increased based on the existing number of times, and it is checked (S10). It is then determined whether the number of erasures that have been confirmed is greater than a predefined value (S20). The predefined value should be calculated by the mathematical formula:

The predefined value (average erase count + error range) [ mathematical formula 1]

for example, when the average erase count is 100 and the error range is 40, the predefined value is 140. When the number of erasures performed on a corrupted block is greater than 140, storage control 140 begins to handle performing a wear leveling process. The accumulated failure number (S30) is used as a first query parameter for the target block. The cumulative failure number is an identification signal whose function is to indicate the success or failure of a search in the target block in place of the corrupted block. The initial value of the accumulation failure number is set to 0, and in the subsequent process, the accumulation failure number is incremented by one if the target block for replacing the worn block is not searched. This is done to relax the basic reference value of the target block erase count in the case where the accumulated failure count increases. In other words, as the accumulation failure number increases, the search parameter value of the target block expands. Specifically, the initial parameter value for the target block is a small erase count, which is obtained by subtracting the error margin from the average erase value. For example, when the average erase value is 100 and the error range is 40, then the initial parameter value for the block is 60. A block erased more than the above-mentioned number should be considered as a replacement block. Thus, as the number of accumulated failures increases, the parameter values for blocks with smaller erase counts are incrementally increased by "5" increments (45, 50, 55, … …). Although, the allowable number of accumulation failures is set to be smaller than the average while preventing the number of accumulation failures from being accumulated endlessly. Thus, the first condition for finding the target block is the number of erasures of the target block that are replaced, which is used as a selection parameter for the target block.

Meanwhile, the number of searches of the target block will be taken as the second search parameter value of the target block (S40). The number of searches for the target block is taken as a condition, meaning the number of accesses to the mapping page of the memory area. Blocks stored in a single mapping page can only perform one access operation at a time. If the target block is not searched for by one-time access, other mapping pages need to be accessed to determine whether the target block exists in the accessed mapping pages. The number of accesses increases, resulting in an increase in query objects. The access times are neither randomly nor uniformly set, but are flexibly changed according to the erasing times of the damaged blocks. The access times of the mapping pages need to be flexibly controlled by referring to the value that the erasing times of the damaged blocks exceed the sum of the average erasing times and the error range. That is, the number of accesses to the map page is increased under flexible control, and timely replacement is performed in consideration of the urgency of the damaged block to be replaced. Therefore, it is important to know the difference between the erase count of the defective block and the average erase count. E.g., depending on the importance of the system, the depth to which the wear leveling process is performed is differentiated. Of course, given the architecture of the solid-state storage system in use and its usage, it also needs to be treated separately when performing the wear leveling process. This part is illustrated in fig. 5, and a detailed description is given later. Therefore, it is determined whether the second search condition is used for the number of executions (S50).

That is, the number of accesses derived from the calculation formula does not exceed the predetermined value, and the repetitive loop is executed until the target block is searched (S60). Once the access times value reaches the predetermined parameter value, it is determined whether the target block is found within the access times limit value. In using the repetitive loop, the target block is found with less than the preset number of accesses, the cumulative number of failures is reduced and updated (S80). Once the existing state satisfies the first and second conditions, the remaining value of the allowable cumulative number of failures may be confirmed by subtracting the value of the cumulative number of failures from a predetermined value.

If the target block is not found within the access number threshold, the search criteria need to be relaxed. That is, the cumulative failure number needs to be raised and updated (S90). This occurs when the target block as the substitute block is not found even though the first and second search conditions have been set at present. In this case, the accumulated failure number is increased and updated so as to affect the next search condition, and thus the search success rate of the wear leveling process in the erase operation of the next block is improved.

For example, the erasure number reference value condition and the search number reference value condition need to be set separately in order to more effectively search the distributed erasure number information of the block. The initial search for blocks means that in the wear leveling process (or in the next wear leveling run), the blocks are searched within a predefined number of searches to preliminarily satisfy the erase count condition. Thus, the number of times that this type of situation needs to be performed is significantly reduced compared to the case where the wear leveling process needs to be performed on all blocks.

FIG. 4 graphically illustrates a correlation between erase counts and cumulative failure counts for a target block based on an application example. In fig. 4, the X-axis represents the cumulative number of failures and the Y-axis represents the number of times the target block was erased. In this case it can be assumed that the average erase count, the error range and the allowable cumulative number of failures are 100, 40 and 5 (or less), respectively.

The curve a in fig. 4 can be realized by the following mathematical formula:

First search condition of target block ═ (average number of erasures-error range)

+ error range/(maximum allowable cumulative failure number-cumulative failure number) [ mathematical formula 2]

This formula can be applied only when the number of allowable accumulation failures is 5 or less. If the number of allowable cumulative failures is greater than the limit value, it is possible to generate a straight line with a small slope when the target block is realized by applying the first condition, as shown in the b-curve in fig. 4.

Target block first condition (average erase count + threshold error value upper line) -cumulative failure number [ mathematical formula 3]

Thus, it is suggested in fig. 4 that it is more practical to actively search for a target block in a sector whose cumulative failure number is lower than the allowable cumulative failure number of 5. When the number of allowable accumulated failures is larger than the extreme value and the number of times of erasing of the target block has exceeded the sum of the average erase count and the extreme value, the meaning of relaxing the search condition of the target block is not so large. Therefore, in connection with this example, the allowable cumulative failure number limit is set to 5, and the solid-state storage system is managed so as not to exceed the limit.

FIG. 5 shows the correlation of sensitivity and block erase counts in tabular form: when the number of erasures of a defective block increases, the number of sensitivity-based searches is set to increase. In addition, since the strength of the sensitivity increases, the number of searches for a defective block having the same number of erasures must also increase.

second search condition of target block

(number of access times of basic mapping page-1) + (number of erase times of defective block- (average number of erase times + extremum)). sensitivity [ mathematical formula 4]

the number of access times of the basic mapping page, the average number of times of erasing, and the extreme value are set to 7, 100, and 40, respectively. Therefore, when the erase count of the worn block is greater than the sum of the average erase count and the extreme value, the search count of the target block corresponding to the worn block must be enhanced. The second search condition for the target block should be set to increase the number of map accesses, for example, using mathematical formula 4. Meanwhile, once a high-performance system requires high sensitivity, equation 4 can be implemented with a sensitivity function.

FIG. 6 graphically illustrates the relationship between sensitivity and number of visits: the X-axis shows the erase count of the defective block, and the Y-axis represents the access count. The number of visits can be calculated using mathematical formula 4. If the sensitivity of fig. 5 is used, the corresponding slope in this figure will be steeper. That is, the sensitivity intensities at 1-5 of FIG. 6 correspond to 1-5 of FIG. 5. The number of accesses with respect to the number of erases varies depending on the strength of sensitivity. For example, when the number of times of erasing is 150, the interval of the number of times of access according to the sensitivity intensity is [18,58 ]. When the sensitivity of the system is higher, intensive search of the target block is required even if the number of accesses increases. In the wear leveling process, not all of the erase count information for the blocks can be loaded, and the overall comparison may not be possible. Therefore, the target block can be searched more efficiently by setting an appropriate search condition.

A block search with an alternative value takes less time than a target block with a low value. That is, the originally searched block with replacement capability will be sacrificed in replacing the target block with the lowest value in the wear leveling process of the worn block. Finally, the number of times the target block is erased, i.e., the first search condition for the target block, still needs to be controlled during the period of constantly changing to improve the search success rate; and the number of target blocks to search may be increased according to the urgency of defective block replacement.

In connection with practical application, even when the storage space is expanded, the space of a cache unit for temporarily storing the mapping information and the erasure number information is not required to be increased; the cache unit may be kept smaller than in the prior art. Only the erasure number information and the mapping information of the defective block are loaded, and the erasure number parameter value condition and the search number parameter value condition are set separately. The wear leveling process processing time may be reduced. Therefore, when the space of the cache unit is reduced and the processing time of the wear leveling process is also reduced, the operation performance and the cost efficiency of the solid-state storage system are improved.

as mentioned above, the described application examples are only for the understanding of the persons skilled in the art. Accordingly, the present systems and methods are not limited to the examples presented herein.

Claims

1. A solid-state storage system for flexible control of wear leveling, comprising: the host interface is connected with the cache unit, transmits and receives control commands, address signals and data signals between an external host and the cache unit, and the interface mode between the host interface and the external host is one of SATA, PATA, SCSI, Express Card or PCI-Express; and a memory control for searching for a target block based on an accumulated failure number, the accumulated failure number being based on a failure number of searching for the target block in a previous wear leveling process and an access number to a mapped page, the erasure number parameter value condition and the search number parameter value condition being set respectively, data of any block being erasable, after the data of the block being erased, increasing the number of times of this erasure on the basis of an existing number of times and checking it, and then determining whether the number of times of erasure that has been confirmed is greater than a predefined value, the predefined value being calculated by mathematical formula 1:

The predefined value (average erase count + error range) [ mathematical formula 1],

When the average erase count is 100 and the error range is 40, the predefined value is 140, and when the erase count performed on the damaged block is greater than 140, the memory control starts to perform the wear leveling process, which is implemented by the following mathematical formula 2:

+ error range/(maximum allowable cumulative failure number-cumulative failure number) [ mathematical formula 2],

This mathematical formula 2 can be applied only when the number of allowable accumulation failures is 5 or less, searches for a target block in a sector where the number of accumulation failures is lower than the number of allowable accumulation failures 5,

Second search condition of target block

(number of access times of basic mapping page-1) + (number of erase times of defective block- (average number of erase times + extremum)). sensitivity [ math figure 4],

The number of access times of the basic mapping page, the average erase number, and the extreme value are set to 7, 100, and 40, respectively, and when the erase number of the worn block is greater than the sum of the average erase number and the extreme value, the number of search times of the target block corresponding to the damaged block must be enhanced, and using mathematical formula 4, the second search condition for the target block should be set to increase the number of access times of the mapping, wherein sensitivity is sensitivity associated with the erase number of the worn block.

2. A solid-state storage system control method for flexibly controlling wear leveling, which only loads the erasing times of a damaged block, comprises the following steps:

a) Setting a first parameter value according to the accumulated failure times of the failure times of searching a single target block in the previous loss balancing process;

b) setting a second parameter value according to the access times of the mapping page;

c) Setting a search condition of a target block according to the first and second parameter values; and

d) In the wear leveling process, searching a target block for replacing the damaged block according to the search condition of the target block,

the erasing times parameter value condition and the searching times parameter value condition are set respectively, data of any block can be erased, after the data of the block is erased, the erasing times of this time is increased on the basis of the existing times, the erasing times are checked, then whether the confirmed erasing times are larger than a predefined value is determined, and the predefined value is calculated through a mathematical formula 1:

Second search condition of target block