CN105931969A - Method for manufacturing terminal structure - Google Patents
Method for manufacturing terminal structure Download PDFInfo
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- CN105931969A CN105931969A CN201610374737.9A CN201610374737A CN105931969A CN 105931969 A CN105931969 A CN 105931969A CN 201610374737 A CN201610374737 A CN 201610374737A CN 105931969 A CN105931969 A CN 105931969A
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- opening
- terminal structure
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000007772 electrode material Substances 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 238000000407 epitaxy Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 239000004744 fabric Substances 0.000 claims description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 16
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract description 2
- 238000001459 lithography Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 142
- 238000009826 distribution Methods 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 12
- 238000002372 labelling Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 238000010276 construction Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000009514 concussion Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/765—Making of isolation regions between components by field effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a method for manufacturing a terminal structure. The method comprises the following steps: forming a trench in a semiconductor substrate; forming a first insulating layer to completely fill the trench; depositing a second hard mask layer; carrying out lithography etching on the second hard mask layer to form a first opening; carrying out first time anisotropic etching on the first insulating layer at the bottom of the first opening with the second hard mask layer as a mask to form a second groove; carrying out transverse etching on the second hard mask layer to expand the width of the first opening; carrying out second time anisotropic etching on the first insulating layer at the bottom of the first opening with the second hard mask layer as the mask to expand the second groove in the longitudinal and transverse direction and form a stepped structure; repeating the sixth step and the seventh step in sequence to form a shielding medium layer at last; and removing the second hard mask layer, and filling an electrode material layer in the second groove. According to the invention, the shielding medium layer with gradually variational thickness can be formed, the electric field strength of the terminal structure can be uniformly distributed, the breakdown voltage is increased, the process is simple, and the cost is low.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, particularly relate to the manufacturer of a kind of terminal structure
Method.
Background technology
Since power MOS technology is invented, this technology is achieved with a lot of important development and significant progress.In recent years
Coming, new device structure and the coming of new technique of power MOS technology are constantly emerged in large numbers, to reach two most basic targets:
Maximum power handling capability, minimum power attenuation.Trench gate mosfet (Trench MOS) technology is to realize this
One of target most important promoting technology power.Initially, the invention of Trench MOS technology is in order to increase planar device
Gully density, to improve the current handling capability of device, but, the new Trench MOS structure of improvement not only can
Reducing gully density, moreover it is possible to reduce drift zone resistance further, its main target of Trench MOS technology development is:
(1) forward conduction resistance is reduced to reduce static power consumption；(2) improve switching speed to damage to reduce transient power
Consumption.
In new Trench MOS structure, the most representational is shield grid (Shield-Gate) technology, can profit
Reduce the electric field of drift region with its ground floor polysilicon (Shield) as " internal field plate ", thus reduce drift
District's resistance, so Shield-Gate technology is generally of lower conducting resistance and higher breakdown voltage, and can
Trench MOS product for high voltage (20V-250V).Additionally, due to Shield-Gate technology can
There is higher input capacitance (Ciss) and Miller (Miller) electric capacity (Cgd) ratio, Ciss/Cgd, so,
Shield-Gate device has the higher anti-drain voltage concussion ability on grid impact.In recent years there is shield grid
The improvement of Trench MOS structure and process aspect emerges in an endless stream, and these new structures and technique improve this structure greatly
The market share of device, the Trench MOS product market share produced by this technology is improved year by year, obtains
Flourish.
Formed, by ground floor polysilicon, the terminal structure that the shielding dielectric layer of bucking electrode and bottom forms and can reduce ditch
The drift region electric field of groove side, the impact of electric field is had by the thickness distribution of the shielding dielectric layer being wherein positioned at groove side surface
Considerable influence, as it is shown in figure 1, be the terminal structure of the shielding dielectric layer with uniform thickness and stepped construction thickness
Electric Field Distribution comparison diagram；Shielding dielectric layer such as oxidation it is formed with in the groove of Semiconductor substrate such as silicon substrate 101a
Layer 102a, is formed with shielding dielectric layer such as oxide layer 102b in the groove of Semiconductor substrate such as silicon substrate 101b.From
The bottom of groove is uniform to the thickness of top barrier dielectric layer 102a, and the thickness shielding dielectric layer 102a can gradually subtract
Thin.From the electric-field intensity distribution line corresponding to labelling 103a it can be seen that bottom Electric Field Distribution less of groove,
And more concentrate in the top Electric Field Distribution of groove；From the electric-field intensity distribution line corresponding to labelling 103b it can be seen that
In the range of the entire depth of groove, Electric Field Distribution ratio is more uniform.Curve 104 represents the shielding medium with gradient thickness
The electric-field intensity distribution curve of layer groove side surface corresponding to 102b, curve 105 represents have shielding in uniform thickness
The electric-field intensity distribution curve of the groove side surface of terminal structure corresponding to dielectric layer 102a.It can be seen that shielding medium
Corresponding to layer 102b, the electric-field intensity distribution of the groove side surface of terminal structure is more uniform, and voltage endurance capability is higher.Fig. 1
In show that there is the pressure for 59.6V of shielding terminal structure corresponding to dielectric layer 102a, there is shielding dielectric layer
Terminal structure corresponding to 102b pressure for 114.8V.
Summary of the invention
The technical problem to be solved is to provide the manufacture method of a kind of terminal structure, can form thickness from groove
The bottom shielding dielectric layer the most thinning to top, it is possible to the electric-field intensity distribution of terminal structure uniformly and improves and punctures
Voltage, and technique is simple, low cost.
For solving above-mentioned technical problem, the manufacture method of the terminal structure that the present invention provides comprises the steps:
Step one, offer semi-conductive substrate, use lithographic etch process to form groove in described Semiconductor substrate.
Step 2, carrying out the first insulating layer growth, described groove is filled up completely with by described first insulating barrier.
Step 3, deposit the second hard mask layers, the material of described second hard mask layers and described first insulating barrier
Material is different；And described second hard mask layers can carry out anisotropic etching as follow-up to described first insulating barrier
Mask and the follow-up etch rate of lateral etching that carries out described second hard mask layers are more than described first insulating barrier
Etch rate.
Step 4, described second hard mask layers is carried out chemical wet etching form the through described second hard mask layers
One opening, described first opening is positioned at the surface of described groove, in the central and described groove of described first opening
Centre alignment, the width of described first opening is less than the width of described groove.
Step 5, described first insulating barrier of described first open bottom is entered with described second hard mask layers for mask
Row anisotropic etching for the first time forms the second groove, and the width of described second groove is true by the width of described first opening
Fixed.
Step 6, described second hard mask layers to described first opening both sides carry out lateral etching makes described first to open
The width expansion of mouth.
Step 7, with described second hard mask layers after described first enlarged open for mask to described first open bottom
Described first insulating barrier in portion carries out second time anisotropic etching makes described second groove expand also at vertical and horizontal
In hierarchic structure.
Step 8, it is repeated in step 6 and step 7 and is finally formed by remaining in the bottom of described groove and side
The shielding dielectric layer of described first insulating barrier composition.
After step 7 completes every time, the width at described second groove top ladder is right by working as time anisotropic etching institute
The width of described first opening answered determines, at described second groove top ladder below each ladder at width divide
Cloth successively by a front anisotropic etching until described first opening corresponding to described first time anisotropic etching
Width determine.
From the bottom of described groove up, the described shielding dielectric layer of described groove side surface is hierarchic structure and along with ladder
Increase thickness the most thinning.
Step 9, remove described second hard mask layers, described second groove is filled electrode material layer and forms end
End structure.
Further improving is that described Semiconductor substrate is to be formed with the silicon substrate of silicon epitaxy layer, and described groove is formed at
In described silicon epitaxy layer.
Further improving is that described first insulating barrier is made up of silicon oxide.
Further improving is that described second hard mask layers is made up of silicon nitride.
Further improve is that step 6 uses the isotropic etching described second hard to described first opening both sides
Mask layer carries out lateral etching.
Further improve is that the isotropic etching that step 6 uses is wet etching.
Further improve is that the described electrode material layer filled in step 9 is polysilicon layer.
Further improving is that described terminal structure is applied in shield grid power MOSFET, described electrode material layer
As bucking electrode.
Further improve and be, the thickness being positioned at described trench bottom surfaces of the described shielding dielectric layer that step 8 is formed
More than or equal to the thickness being positioned at described groove side surface.
The present invention use a trench fill process and add the most progressively etching just can be formed thickness from the bottom of groove to
The shielding dielectric layer that top is the most thinning, it is possible to the electric-field intensity distribution of terminal structure uniformly and improves breakdown voltage；By
Use a trench fill to add the most progressively etching in the present invention to can be achieved with, whole etching technics is carried out enter for the first time
Row lithographic definition, does not carries out lithographic definition at needs in subsequent process, therefore technique is simple, low cost.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is that the Electric Field Distribution of the terminal structure of the shielding dielectric layer with uniform thickness and stepped construction thickness compares
Figure；
Fig. 2 A-2H is the device architecture schematic diagram in each step of manufacture method of the first terminal structure existing；
Fig. 3 A-3H is the device architecture schematic diagram in each step of manufacture method of existing the second terminal structure；
Fig. 4 is the flow chart of the manufacture method of embodiment of the present invention terminal structure；
Fig. 5 A-5J is the device architecture schematic diagram in each step of manufacture method of embodiment of the present invention terminal structure.
Detailed description of the invention
As shown in Fig. 2 A to 2H, it it is the device architecture signal in each step of manufacture method of the first terminal structure existing
Figure；Terminal structure is applied in shield grid power MOSFET；Bottom insulation layer in existing first method i.e. shields
Dielectric layer uses bottom oxidization layer, is progressively to deposit (Stepped-Oxide-Deposition, SOD) by oxide layer
Realize, comprise the steps:
As shown in Figure 2 A, it is provided that surface is formed with the silicon substrate 201 of N-type silicon epitaxy layer 202, at silicon epitaxy layer 202
Trench gate formed region formed groove 203, Fig. 2 A only show a groove 203, shield grid power MOSFET
Typically can be made up of multiple MOSFET cellular constructions, a groove 203 is corresponding to a MOSFET cellular construction.It
After form oxide layer 204a in the lower surface of groove 203 and side.
As shown in Figure 2 B, groove 203 is filled sacrifice layer 205a, and carries out back sacrifice layer 205a carving, return and carve
After sacrifice layer 205a be positioned at the bottom of groove 203.Will be located in the side of groove 203 bottom sacrifice layer 205a afterwards
Oxide layer 204a in face is removed.
As shown in Figure 2 C, sacrifice layer 205a is removed afterwards.Form oxide layer 204b afterwards, the bottom of groove 203
Oxide layer will be made up of oxide layer 204a and 204b superposition, and the oxide layer of the bottom of groove 203 is by oxide layer 204b
Composition, so the bottom oxidization layer of groove 203 can be thicker.Form sacrifice layer 205b afterwards and return quarter, Hui Kehou's
But the longitudinal thickness that sacrifice layer 205b is positioned at the bottom sacrifice layer 205b of groove 203 can sacrifice layer 205a than Fig. 2 B
Thick.Afterwards oxide layer 204b at sacrifice layer 205b top is removed.
Repeat oxide layer deposit, sacrifice layer deposit and time quarter afterwards, the oxide layer at sacrifice layer top is removed.From
And form the bottom oxidization layer 204 with gradient thickness.Wherein, Fig. 2 D is formed with oxide layer 204c, sacrifice layer
205c；Fig. 2 E is formed oxide layer 204d, sacrifice layer 205d；Fig. 2 F is formed oxide layer 204e, sacrifices
Layer 205e；Fig. 2 G is formed with oxide layer 204f.After Fig. 2 G forms oxide layer 204f, have been obtained for oxidation
Layer 204, from Fig. 2 G, the oxide layer bottom oxide layer 204 is that the oxide layer deposited by more number of times is formed by stacking,
Therefore oxide layer 204 has the structure that thickness from bottom to top is gradually reduced.
The most as illustrated in figure 2h, the first polysilicon layer 206 is filled.Will be to the first polysilicon layer 206 in subsequent step
Carry out back carving and form polysilicon shield electrode.I.e. i.e. shielded dielectric layer by polysilicon shield electrode 206 and bottom oxidization layer
204 compositing terminal structures, form other structure of shield grid power MOSFET afterwards, including: form polysilicon gate,
Gate dielectric layer, p-well, source region, interlayer film, the step such as contact layer and front metal layer is no longer discussed in detail.
As shown in Fig. 3 A to 3H, it it is the device architecture signal in each step of manufacture method of existing the second terminal structure
Figure；Bottom insulation layer in existing second method uses bottom oxidization layer, is progressively to be etched removal by oxide layer
(Stepped-Oxide-Etch-Off, SOE) realizes, and comprises the steps:
As shown in Figure 3A, it is provided that surface is formed with the silicon substrate 301 of N-type silicon epitaxy layer 302, at silicon epitaxy layer 302
Trench gate formed region formed groove 303, Fig. 3 A only show a groove 303.Afterwards at groove 303
Lower surface and side form oxide layer 304.
As shown in Figure 3 B, groove 303 is filled sacrifice layer 305.Etching technics is used to will be located in sacrifice layer afterwards
The oxide layer 304 of the both sides, top of 305 is removed, and removes region as shown in labelling 306a.
As shown in Figure 3 C, sacrifice layer 305 carries out back carving afterwards, makes sacrifice layer 305 reduce certain degree of depth.Afterwards
The oxide layer 304 at sacrifice layer 305 top is performed etching removal, removes region as shown in labelling 306b.
Repeat sacrifice layer afterwards to carve for 305 times, the technique of oxide layer 304 etching, thus form the end with gradient thickness
Portion's oxide layer 304.Wherein, in Fig. 3 D the removed region of oxide layer 304 as shown in labelling 306c；Oxygen in Fig. 3 E
Change the removed region of layer 304 as shown in labelling 306d；The removed region of oxide layer 304 such as labelling 306e in Fig. 3 F
Shown in.Sacrifice layer 305 is removed by Fig. 3 G completely, thus completes the formation process of the oxide layer 304 of gradient thickness.
From Fig. 3 G, the oxide layer bottom oxide layer 304 be by the number of times being etched less thus thicker, therefore oxide layer
304 have the structure that thickness from bottom to top is gradually reduced.
The most as shown in figure 3h, the first polysilicon layer 307 is filled.Will be to the first polysilicon layer 307 in subsequent step
Carry out back carving and form polysilicon shield electrode.Form polysilicon gate afterwards, gate dielectric layer, p-well, source region, interlayer film,
The step such as contact layer and front metal layer is no longer discussed in detail.
As shown in Figure 4, it is the flow chart of manufacture method of embodiment of the present invention terminal structure；As shown in Fig. 5 A to 5J,
It it is the device architecture schematic diagram in each step of manufacture method of embodiment of the present invention terminal structure.Embodiment of the present invention terminal
The manufacture method of structure comprises the steps:
Step one, as shown in Figure 5A, it is provided that semi-conductive substrate 1, uses lithographic etch process to serve as a contrast at described quasiconductor
The end 1, is formed groove 2.Preferably, described Semiconductor substrate 1 is the silicon substrate being formed with silicon epitaxy layer, described ditch
Groove 2 is formed in described silicon epitaxy layer.
Step 2, as shown in Figure 5 B, carries out the first insulating barrier 3 and grows, and described first insulating barrier 3 is by described groove 2
It is filled up completely with.Preferably, described first insulating barrier 3 is made up of silicon oxide.
Step 3, as shown in Figure 5 C, deposits the second hard mask layers 4, the material of described second hard mask layers 4 and
The material of described first insulating barrier 3 is different；And described second hard mask layers 4 can be as follow-up to described first insulation
Layer 3 carries out the mask of anisotropic etching and the follow-up etching that described second hard mask layers 4 carries out lateral etching
Speed is more than the etch rate of described first insulating barrier 3.Preferably, described second hard mask layers 4 is by silicon nitride group
Become.
Step 4, as shown in Figure 5 C, carries out chemical wet etching and is formed through described the described second hard mask layers 4
First opening 5 of two hard mask layers 4, described first opening 5 is positioned at the surface of described groove 2, and described first
The central alignment of the central and described groove 2 of opening 5, the width of described first opening 5 is less than the width of described groove 2
Degree.
Step 5, as shown in Figure 5 D, with described second hard mask layers 4 for mask to described first opening 5 bottom
Described first insulating barrier 3 carry out for the first time anisotropic etching and form the second groove 6, the width of described second groove 6
Degree is determined by the width of described first opening 5.
Step 6, as shown in fig. 5e, uses described second hard to described first opening 5 both sides of isotropic etching
Matter mask layer 4 carries out lateral etching makes the width expansion of described first opening 5.Preferably, step 6 use each to
Same sex etching is wet etching.
Step 7, as illustrated in figure 5f, described second hard mask layers 4 after expanding with described first opening 5 is for covering
Mould carries out second time anisotropic etching to described first insulating barrier 3 bottom described first opening 5 to be made described second recessed
Groove 6 expands and in hierarchic structure at vertical and horizontal；In Fig. 5 F, labelling 61 represents the rank, bottom of described second groove 6
Ladder, labelling 62 represents the ladder at ladder 61 top, it is known that the width of ladder 62 can be by second time anisotropic etching
The width of the first corresponding opening 5 determines, ladder 61 be front once, here for first time anisotropic etching institute
The width of the first corresponding opening 5 determines.
Step 8, it is repeated in step 6 and step 7 and is finally formed by remaining in the bottom of described groove 2 and side
Described first insulating barrier 3 composition shielding dielectric layer 31.
As depicted in fig. 5g for repeating the schematic diagram corresponding to step 6 for the first time, the first opening 5 is made further to expand；
Fig. 5 H show the schematic diagram repeated for the first time corresponding to step 7, makes the second groove 6 further expand and occur
Three ladders, respectively ladder 61,62 and 63, ladder 63 is by anisotropic etching institute during repetition step 7 for the first time
The width of corresponding the first opening 5 corresponding to the first opening 5 i.e. Fig. 5 G determines.
Circulation is carried out the most successively, finally obtains the shielding dielectric layer 31 of required thickness structure, as shown in fig. 5i,
For the shielding dielectric layer 31 finally given and the structure of the second corresponding groove 6, shielding dielectric layer labelling 31 represents.
Understanding, after each step 7 completes, at described second groove 6 top ladder, the width of 6n is by when time anisotropy
The width of described first opening 5 corresponding to etching determines, at described second groove 6 top ladder below each rank
Width distribution at Ti successively by a front anisotropic etching until corresponding to described first time anisotropic etching
The width of described first opening 5 determines.
From the bottom of described groove 2 up, the described shielding dielectric layer 31 of described groove 2 side in hierarchic structure and
Along with ladder increase thickness is the most thinning.Preferably, described shielding dielectric layer 31 be positioned at table bottom described groove 2
The thickness in face is more than or equal to the thickness being positioned at described groove 2 side.
Step 9, as indicated at figure 5j, removes described second hard mask layers 4, fills electricity in described second groove 6
Pole material layer 7 also forms terminal structure.Preferably, described electrode material layer 7 is polysilicon layer.
In the embodiment of the present invention, described terminal structure is applied in shield grid power MOSFET, described electrode material layer 7
As bucking electrode.
Above by specific embodiment, the present invention is described in detail, but these have not constituted the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improves, this
Also should be regarded as protection scope of the present invention a bit.
Claims (9)
1. the manufacture method of a terminal structure, it is characterised in that comprise the steps:
Step one, offer semi-conductive substrate, use lithographic etch process to form groove in described Semiconductor substrate；
Step 2, carrying out the first insulating layer growth, described groove is filled up completely with by described first insulating barrier；
Step 3, deposit the second hard mask layers, the material of described second hard mask layers and described first insulating barrier
Material is different；And described second hard mask layers can carry out anisotropic etching as follow-up to described first insulating barrier
Mask and the follow-up etch rate of lateral etching that carries out described second hard mask layers are more than described first insulating barrier
Etch rate；
Step 4, described second hard mask layers is carried out chemical wet etching form the through described second hard mask layers
One opening, described first opening is positioned at the surface of described groove, in the central and described groove of described first opening
Centre alignment, the width of described first opening is less than the width of described groove；
Step 5, described first insulating barrier of described first open bottom is entered with described second hard mask layers for mask
Row anisotropic etching for the first time forms the second groove, and the width of described second groove is true by the width of described first opening
Fixed；
Step 6, described second hard mask layers to described first opening both sides carry out lateral etching makes described first to open
The width expansion of mouth；
Step 7, with described second hard mask layers after described first enlarged open for mask to described first open bottom
Described first insulating barrier in portion carries out second time anisotropic etching makes described second groove expand also at vertical and horizontal
In hierarchic structure；
Step 8, it is repeated in step 6 and step 7 and is finally formed by remaining in the bottom of described groove and side
The shielding dielectric layer of described first insulating barrier composition；
After step 7 completes every time, the width at described second groove top ladder is right by working as time anisotropic etching institute
The width of described first opening answered determines, at described second groove top ladder below each ladder at width divide
Cloth successively by a front anisotropic etching until described first opening corresponding to described first time anisotropic etching
Width determine；
From the bottom of described groove up, the described shielding dielectric layer of described groove side surface is hierarchic structure and along with ladder
Increase thickness the most thinning；
Step 9, remove described second hard mask layers, described second groove is filled electrode material layer and forms end
End structure.
2. the manufacture method of terminal structure as claimed in claim 1, it is characterised in that: described Semiconductor substrate is
Being formed with the silicon substrate of silicon epitaxy layer, described groove is formed in described silicon epitaxy layer.
3. the manufacture method of terminal structure as claimed in claim 2, it is characterised in that: described first insulating barrier by
Silicon oxide forms.
4. the manufacture method of terminal structure as claimed in claim 3, it is characterised in that: described second hardmask
Layer is made up of silicon nitride.
5. the manufacture method of the terminal structure as described in claim 1 or 3, it is characterised in that: step 6 uses each
To same sex etching, described second hard mask layers of described first opening both sides is carried out lateral etching.
6. the manufacture method of terminal structure as claimed in claim 5, it is characterised in that: step 6 use each to
Same sex etching is wet etching.
7. the manufacture method of terminal structure as claimed in claim 1, it is characterised in that: the institute filled in step 9
Stating electrode material layer is polysilicon layer.
8. the manufacture method of the terminal structure as described in claim 1 or 7, it is characterised in that: described terminal structure
Being applied in shield grid power MOSFET, described electrode material layer is as bucking electrode.
9. the manufacture method of terminal structure as claimed in claim 1, it is characterised in that: it is described that step 8 is formed
The thickness being positioned at described trench bottom surfaces of shielding dielectric layer is more than or equal to the thickness being positioned at described groove side surface.
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| CN201610374737.9A CN105931969A (en) | 2016-05-31 | 2016-05-31 | Method for manufacturing terminal structure |
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| CN108400094A (en) * | 2018-04-19 | 2018-08-14 | 张帅 | Shielded gate field effect transistor and its manufacturing method（Capitate） |
| CN109216438A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The manufacturing method of the stacking polysilicon grating structure of semiconductor devices |
| CN112736123A (en) * | 2019-10-28 | 2021-04-30 | 苏州东微半导体股份有限公司 | Semiconductor power device terminal structure |
| CN113299745A (en) * | 2021-06-10 | 2021-08-24 | 珠海市浩辰半导体有限公司 | Terminal structure, semiconductor device and manufacturing method |
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| EP1271655A3 (en) * | 2001-06-29 | 2004-03-17 | Kabushiki Kaisha Toshiba | Vertical power MOSFET having a trench gate electrode and method of making the same |
| US20100264486A1 (en) * | 2009-04-20 | 2010-10-21 | Texas Instruments Incorporated | Field plate trench mosfet transistor with graded dielectric liner thickness |
| CN104488084A (en) * | 2012-07-25 | 2015-04-01 | 电力集成公司 | Method of forming a tapered oxide |
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| US20020166838A1 (en) * | 2001-05-10 | 2002-11-14 | Institute Of Microelectronics | Sloped trench etching process |
| EP1271655A3 (en) * | 2001-06-29 | 2004-03-17 | Kabushiki Kaisha Toshiba | Vertical power MOSFET having a trench gate electrode and method of making the same |
| US20100264486A1 (en) * | 2009-04-20 | 2010-10-21 | Texas Instruments Incorporated | Field plate trench mosfet transistor with graded dielectric liner thickness |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109216438A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The manufacturing method of the stacking polysilicon grating structure of semiconductor devices |
| CN109216438B (en) * | 2017-07-03 | 2021-06-04 | 无锡华润上华科技有限公司 | Method for manufacturing stacked polysilicon gate structure of semiconductor device |
| CN108400094A (en) * | 2018-04-19 | 2018-08-14 | 张帅 | Shielded gate field effect transistor and its manufacturing method（Capitate） |
| CN112736123A (en) * | 2019-10-28 | 2021-04-30 | 苏州东微半导体股份有限公司 | Semiconductor power device terminal structure |
| CN113299745A (en) * | 2021-06-10 | 2021-08-24 | 珠海市浩辰半导体有限公司 | Terminal structure, semiconductor device and manufacturing method |
| CN113299745B (en) * | 2021-06-10 | 2022-04-15 | 珠海市浩辰半导体有限公司 | Terminal structure, semiconductor device and manufacturing method |
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