CN105912441A - Bandwidth monitoring method, device and system for NUMA chips - Google Patents
Bandwidth monitoring method, device and system for NUMA chips Download PDFInfo
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- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
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Abstract
The invention provides a bandwidth monitoring method, device and system for NUMA chips. The method comprises following steps: monitoring data traffic of an uplink bus and obtaining uplink bus bandwidth data, wherein the uplink bus is a bus for data transmission between a NUMA chip and all other NUMA chips; monitoring data traffic of the downlink data, obtaining bandwidth data of the downlink data, wherein the downlink bus is a bus for data transmission between the NUMA chip and all processors in the same NUMA node; monitoring data traffic of all internal buses of the NUMA chip, obtaining internal bus bandwidth data corresponding to all the internal buses, wherein internal buses are ones used for data transmission between any two function modules in the NUMA chip; and storing the bandwidth data of the uplink bus and the downlink bus and that of all internal buses to state registers corresponding to the NUMA chips.The scheme can determine the bandwidth conditions of NUMA chips.
Description
Technical field
The present invention relates to communication technical field, particularly to a kind of NUMA chip width monitoring method,
Apparatus and system.
Background technology
Along with development and the progress of computer technology, some high-performance computers include multiple process
Device, to meet user's requirement to calculating speed.In the computer of multiprocessor, each processor
Mode of operation mainly has three kinds, respectively SMP (Symmetric Multiprocessing Processing,
Symmetric multi-processors) pattern, NUMA (Non Uniform Memory Access, non-homogeneous storage access)
Pattern and MPP (Massively Parallel Processing, MPP) pattern.
Wherein, NUMA pattern for being divided into multiple NUMA node by computer, and each NUMA saves
Point includes a NUMA chip, a number of processor chips and internal memory.Same NUMA node
In, each processor can access this NUMA by the NUMA chip on this NUMA node and save
Data in some internal memory；NUMA chip in different NUMA node is connected with each other, a NUMA
Processor in node is accessed in another NUMA node internal memory by two the NUMA chips being connected
Data.
It is directed to NUMA pattern, due to factors such as the design of NUMA chip are unreasonable, often occurs one
When processor in individual NUMA node accesses other NUMA node data in EMS memory, NUMA chip
Bandwidth declines substantially, causes the situation that access speed is slower, but owing to NUMA chip cannot be determined
Concrete bandwidth situation, it is impossible to NUMA chip is optimized.
Summary of the invention
Embodiments provide a kind of method of NUMA chip width monitoring, Apparatus and system,
Can determine the bandwidth situation that NUMA chip is concrete.
A kind of method embodiments providing NUMA chip width monitoring, including:
The data traffic of upper row bus is monitored, it is thus achieved that up bus bandwidth data, wherein, described
Upper row bus is the bus that each NUMA chip of described NUMA chip and other carries out data transmission；
The data traffic of lower row bus is monitored, it is thus achieved that descending bus bandwidth data, wherein, described
Lower row bus is that described NUMA chip carries out data transmission with each processor in same NUMA node
Bus；
The data traffic of each internal bus of described NUMA chip is monitored, it is thus achieved that in each
The internal bus band data that portion's bus is corresponding, wherein, described internal bus is described NUMA chip
The bus that internal any two functional module carries out data transmission；
By described up bus bandwidth data, descending bus bandwidth data and each internal bus bandwidth number
According in status register corresponding in storage to described NUMA chip.
Preferably, described up bus bandwidth data include: the real-time bandwidth of described upper row bus, peak value
Any one or more in bandwidth, valley bandwidth and average bandwidth.
Preferably, described descending bus bandwidth data include: the real-time bandwidth of described lower row bus, peak value
Any one or more in bandwidth, valley bandwidth and average bandwidth.
Preferably, described internal bus band data includes: the corresponding real-time bandwidth of internal bus, peak value
Any one or more in bandwidth, valley bandwidth and average bandwidth.
Preferably, described real-time bandwidth includes: in nearest one second, corresponding bus transfer valid data is total
Amount.
Preferably, described peak bandwidth includes: the maximum of corresponding real-time bandwidth in storage and monitoring time segment.
Preferably, described valley bandwidth includes: the non-zero minimum of corresponding real-time bandwidth in storage and monitoring time segment.
Preferably, described average bandwidth includes: each described real-time bandwidth corresponding in storage and monitoring time segment
Meansigma methods.
Preferably, the total amount of described valid data includes: the total amount of the valid data that corresponding bus receives and
The total amount of the valid data that this correspondence bus sends.
Preferably, the method farther includes:
From described status register, described up bus bandwidth is read by baseboard management controller BMC
Any one or more in data, descending bus bandwidth data and each internal bus band data,
So that described NUMA chip is carried out bandwidth performance analysis.
The embodiment of the present invention additionally provides the device of a kind of NUMA chip width monitoring, including: up
Width monitoring unit, downlink bandwidth monitoring means, internal bandwidth monitoring means and memory element；
Described upstream bandwidth monitoring means, for being monitored the data traffic of upper row bus, it is thus achieved that on
Row bus band data, wherein, described upper row bus is described NUMA chip and other each NUMA
The bus that chip carries out data transmission；
Described downlink bandwidth monitoring means, for being monitored the data traffic of lower row bus, it is thus achieved that under
Row bus band data, wherein, described lower row bus is that described NUMA chip saves with same NUMA
The bus that in point, each processor carries out data transmission；
Described internal bandwidth monitoring means, for each internal bus to described NUMA chip internal
Data traffic be monitored, it is thus achieved that the internal bus band data that each internal bus is corresponding, wherein,
Described internal bus be described NUMA chip internal any two functional module carry out data transmission total
Line；
Described memory element, for by described upstream bandwidth monitoring means obtain up bus bandwidth data,
Descending bus bandwidth data and described internal bandwidth monitoring means that described downlink bandwidth monitoring means obtains obtain
Each internal bus band data obtained stores in status register corresponding in described NUMA chip.
Preferably,
Described upstream bandwidth monitoring means, for the data traffic according to described upper row bus, it is thus achieved that described
Any one or more in the real-time bandwidth of upper row bus, peak bandwidth, valley bandwidth and average bandwidth.
Preferably,
Described downlink bandwidth monitoring means, for the data traffic according to described lower row bus, it is thus achieved that described
Any one or more in the real-time bandwidth of lower row bus, peak bandwidth, valley bandwidth and average bandwidth.
Preferably,
Described internal bandwidth monitoring means, for the data traffic according to each internal bus, it is thus achieved that corresponding
Any one or more in the real-time bandwidth of internal bus, peak bandwidth, valley bandwidth and average bandwidth.
Preferably, this device farther includes: read unit；
Described reading unit, for reading from described status register by baseboard management controller BMC
Take in described up bus bandwidth data, descending bus bandwidth data and each internal bus band data
Any one or more, monitor in real time with the bandwidth situation to described NUMA chip.
Preferably, described upstream bandwidth monitoring means, downlink bandwidth monitoring means and internal bandwidth monitoring are single
Any one or more in unit include bandwidth statistics logic circuit.
The embodiment of the present invention additionally provides the system of a kind of NUMA chip width monitoring, including: at least
Any one NUMA chip belt that the embodiment of the present invention of two NUMA node and respective amount provides
The device of wide monitoring；
Processor in described NUMA node, for by NUMA node each described
NUMA chip, accesses the data in the internal memory of each NUMA node, with row bus on described,
Data traffic is produced on lower row bus and internal bus.
Embodiments provide a kind of method of NUMA chip width monitoring, Apparatus and system,
Respectively the data traffic on the upper row bus of NUMA chip, lower row bus and internal bus is supervised
Survey, it is thus achieved that corresponding up bus bandwidth data, descending bus bandwidth data and each internal bus band
Wide data, wherein, up bus bandwidth data represent NUMA chip and other each NUMA chips
The bandwidth situation carried out data transmission, descending bus bandwidth data represent NUMA chip and same NUMA
The bandwidth situation that in node, each processor carries out data transmission, internal bus band data represents correspondence
The bandwidth situation carried out data transmission between each functional module of NUMA chip internal.By by NUMA
The bandwidth partition of chip is upper row bus, lower row bus and internal bus, and acquisition three kinds is dissimilar respectively
The bandwidth of bus such that it is able to determine the bandwidth situation that NUMA chip is concrete.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to reality
Execute the required accompanying drawing used in example or description of the prior art to be briefly described, it should be apparent that below,
Accompanying drawing in description is some embodiments of the present invention, for those of ordinary skill in the art, not
On the premise of paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the method flow of a kind of NUMA chip width monitoring that one embodiment of the invention provides
Figure；
Fig. 2 is the device signal of a kind of NUMA chip width monitoring that one embodiment of the invention provides
Figure；
Fig. 3 is the system signal of a kind of NUMA chip width monitoring that one embodiment of the invention provides
Figure；
Fig. 4 is the method stream of a kind of NUMA chip width monitoring that another embodiment of the present invention provides
Cheng Tu.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with this
Accompanying drawing in bright embodiment, is clearly and completely described the technical scheme in the embodiment of the present invention,
Obviously, described embodiment is a part of embodiment of the present invention rather than whole embodiments, based on
Embodiment in the present invention, those of ordinary skill in the art are institute on the premise of not making creative work
The every other embodiment obtained, broadly falls into the scope of protection of the invention.
As it is shown in figure 1, a kind of method embodiments providing NUMA chip width monitoring,
The method may comprise steps of:
Step 101: the data traffic of upper row bus is monitored, it is thus achieved that up bus bandwidth data,
Wherein, described upper row bus is that described NUMA chip carries out data biography with other each NUMA chips
Defeated bus；
Step 102: the data traffic of lower row bus is monitored, it is thus achieved that descending bus bandwidth data,
Wherein, described lower row bus is that described NUMA chip enters with each processor in same NUMA node
The bus of row data transmission；
Step 103: the data traffic of each internal bus of described NUMA chip is monitored, obtains
Obtaining the internal bus band data that each described internal bus is corresponding, wherein, described internal bus is described
The bus that NUMA chip internal any two functional module carries out data transmission；
Step 104: by described up bus bandwidth data, descending bus bandwidth data and each inside
Bus bandwidth data store in status register corresponding in described NUMA chip.
A kind of method embodiments providing NUMA chip width monitoring, respectively to NUMA
Data traffic on the upper row bus of chip, lower row bus and internal bus is monitored, it is thus achieved that corresponding
Up bus bandwidth data, descending bus bandwidth data and each internal bus band data, wherein,
Up bus bandwidth data represent what each NUMA chip of NUMA chip and other carried out data transmission
Bandwidth situation, descending bus bandwidth data represent in NUMA chip and same NUMA node at each
The bandwidth situation that reason device carries out data transmission, internal bus band data represents in corresponding NUMA chip
The bandwidth situation carried out data transmission between each functional module of portion.By the bandwidth by NUMA chip
It is divided into row bus, lower row bus and internal bus, obtains the bandwidth of three kinds of dissimilar buses respectively,
It is thus possible to determine the bandwidth situation that NUMA chip is concrete.
In an embodiment of the invention, upstream bandwidth data, downlink bandwidth data and internal bandwidth data
May each comprise correspondence real-time bandwidth, peak bandwidth, valley bandwidth and average bandwidth in any one
Or multiple, by the band data of multiple multi-form, the bandwidth situation of bus is characterized, can be anti-
Reflect the bandwidth situation of change of each bus in NUMA chip, improve NUMA chip width monitoring
Accuracy.
In an embodiment of the invention, being directed to a bus, real-time bandwidth is should in nearest one second
By real-time bandwidth, the total amount of bus transfer valid data, may determine that this bus is in data transmission procedure
The bandwidth situation in each moment；Peak bandwidth is the real-time bandwidth that this bus is corresponding in storage and monitoring time segment
Maximum, may determine that, according to peak bandwidth, the maximum bandwidth that this bus occurs in storage and monitoring time segment；Paddy
Value is with a width of non-zero minimum of the real-time bandwidth that this bus is corresponding in storage and monitoring time segment, according to valley band
Width may determine that this bus minimum bandwidth in storage and monitoring time segment when there being message transmissions；Average bandwidth is
In the meansigma methods of each real-time bandwidth corresponding to bus in storage and monitoring time segment.Real-time according to each bus
Bandwidth, peak bandwidth, valley bandwidth and average bandwidth, it may be determined that the concrete defect that bus exists, from
And for the defect determined, the design of bus can be optimized.
In an embodiment of the invention, at the real-time band determining this bus according to the data traffic in bus
Time wide, the real-time bandwidth of this bus is valid data that in nearest one second, this bus receives and the having of transmission
The total amount of effect data.So the speed of the real-time bandwidth reflection bus bi-directional transfer of data of bus, eliminates double
To the transmission data impact on bus bandwidth, further increase the standard to NUMA chip width monitoring
Really property.
In an embodiment of the invention, by the up bus bandwidth data got, descending bus bar
Wide data and each internal bus band data store status register corresponding in NUMA chip
After in, can the status register from NUMA chip be read by baseboard management controller BMC
In up bus bandwidth data, descending bus bandwidth data and each internal bus band data one
Point or full content, it is achieved the purpose that the bandwidth performance of NUMA chip is monitored in real time, and energy
The bandwidth performance of NUMA chip is analyzed by enough band data according to reading, corresponding to formulate
Prioritization scheme.
As in figure 2 it is shown, one embodiment of the invention provides the dress of a kind of NUMA chip width monitoring
Put, including: the monitoring of upstream bandwidth monitoring means 201, downlink bandwidth monitoring means 202, internal bandwidth is single
Unit 203 and memory element 204；
Described upstream bandwidth monitoring means 201, for being monitored the data traffic of upper row bus, obtains
Up bus bandwidth data, wherein, described upper row bus be described NUMA chip with other each
The bus that NUMA chip carries out data transmission；
Described downlink bandwidth monitoring means 202, for being monitored the data traffic of lower row bus, obtains
Obtaining descending bus bandwidth data, wherein, described lower row bus is described NUMA chip and same NUMA
The bus that in node, each processor carries out data transmission；
Described internal bandwidth monitoring means 203, is used for each inside to described NUMA chip internal total
The data traffic of line is monitored, it is thus achieved that the internal bus band data that each internal bus is corresponding, wherein,
Described internal bus be described NUMA chip internal any two functional module carry out data transmission total
Line；
Described memory element 204, for the upper row bus obtained by described upstream bandwidth monitoring means 201
The descending bus bandwidth data of band data, described downlink bandwidth monitoring means 202 acquisition and described inside
Each internal bus band data that width monitoring unit 203 obtains stores in described NUMA chip
In corresponding status register.
Embodiments provide the device of a kind of NUMA chip width monitoring, upper in this device
Row width monitoring unit 201 obtains NUMA chip up bus bandwidth data, and downlink bandwidth monitoring is single
Unit 202 obtains NUMA chip descending bus bandwidth data, and internal bandwidth monitoring means 203 obtains
Each internal bus band data in NUMA chip, each monitoring means is got by memory element 204
Band data store in NUMA chip in corresponding status register.Can not by this device
Only can obtain a NUMA chip and other NUMA chips and carry out data transmission with processor
Bandwidth, additionally it is possible to obtain the band carried out data transmission between each functional module of NUMA chip internal
Wide such that it is able to determine the bandwidth situation that NUMA chip is concrete.
In an embodiment of the invention, upstream bandwidth monitoring means 201 is up according to NUMA chip
The data traffic of bus, it is possible to obtain go up the real-time bandwidth of row bus, peak bandwidth, valley bandwidth and put down
All bandwidth；Downlink bandwidth monitoring means 202, can according to the data traffic of row bus under NUMA chip
To obtain the lower real-time bandwidth of row bus, peak bandwidth, valley bandwidth and average bandwidth；Internal bandwidth is supervised
Survey unit 203 according to the data traffic of each internal bus in NUMA chip, it is possible to obtain in each
The real-time bandwidth of portion's bus, peak bandwidth, valley bandwidth and average bandwidth.Each bus includes many
The amount of individual sign bandwidth, improves the accuracy being monitored NUMA chip bandwidth.
In an embodiment of the invention, this device farther includes to read unit, reads unit and passes through base
Memory element 204 is read on the status register that board management controller BMC is corresponding from NUMA chip
The band data of storage, thus realize the bandwidth situation of NUMA chip is monitored in real time.
In an embodiment of the invention, upstream bandwidth monitoring means 201, downlink bandwidth monitoring means 202
And internal bandwidth monitoring means 203 all can be realized by bandwidth statistics logic circuit.
It should be noted that the device of the NUMA chip width monitoring of embodiment of the present invention offer is permissible
It is integrated on NUMA chip.
As it is shown on figure 3, one embodiment of the invention provide a kind of NUMA chip width monitoring be
System, including: it is any that above-described embodiment of at least two NUMA node 301 and respective amount provides
A kind of device 302 of NUMA chip width monitoring；
Processor 3015 in described NUMA node 301, for by NUMA node each described
NUMA chip 3013 in 301, accesses the number in the internal memory 3014 of each NUMA node 301
According to, with at the upper row bus 3011 of NUMA chip 3013, lower row bus 3012 and NUMA chip
Data traffic is produced on the internal bus of 3013.
For making the object, technical solutions and advantages of the present invention clearer, shown in Fig. 2
The system of the NUMA chip width monitoring shown in the device of NUMA chip width monitoring and Fig. 3 is right
The method of the NUMA chip width monitoring that the embodiment of the present invention provides is described in further detail.
As shown in Figure 4, a kind of method embodiments providing NUMA chip width monitoring,
The method may comprise steps of:
Step 401: to the upper row bus of NUMA chip, lower row bus and the data traffic of internal bus
It is monitored.
In an embodiment of the invention, as it is shown on figure 3, be directed to a current NUMA node 301,
The data stream of the real-time upper row bus 3011 to NUMA chip 3013 of upstream bandwidth monitoring means 3021
Amount is monitored, the real-time lower row bus to NUMA chip 3013 of downlink bandwidth monitoring means 3022
The data traffic of 3012 is monitored, and internal bandwidth monitoring means 3023 is in real time to NUMA chip 3013
The data traffic of the internal internal bus connecting each functional module is monitored.
In embodiments of the present invention, in current NUMA node 301, under processor 3015 passes through
When row bus 3012 and NUMA chip 3013 carries out read operation or write operation to internal memory 3014, will be
Data traffic is produced on internal bus in lower row bus 3012 and NUMA chip 3013；Work as process
Device 3015 by lower row bus 3012, NUMA chip 3013 and upper row bus 3011 to other NUMA
When internal memory in node carries out read operation or write operation, will be at lower row bus 3012, NUMA chip 3013
In internal bus and upper row bus 3011 on produce data traffic.
In embodiments of the present invention, the internal bus of NUMA chip is used for connecting NUMA chip and includes
Each functional module, be used for realizing carrying out data transmission between each functional module, such as, NUMA
Chip includes routing module, protocol process module and cross switch module, and internal bus 1 is for link road
By module and protocol process module, internal bus 2 is for connection route module and cross switch module, interior
Portion's bus 3 is for connection protocol processing module and cross switch module.NUMA chip is receiving data
After, alternately data are processed by each functional module internal, and the data after processing are sent to
Corresponding receiving terminal.
Step 402: according to monitoring result, determines that upper row bus, lower row bus and internal bus are the most right
The band data answered.
In an embodiment of the invention, as it is shown on figure 3, upstream bandwidth monitoring means 3021 is according to up
The data traffic situation of bus 3011, the real-time bandwidth of row bus 3011, peak bandwidth, paddy in calculating
Value bandwidth and average bandwidth；Downlink bandwidth monitoring means 3022 is according to the data traffic of lower row bus 3012
Situation, calculates the lower real-time bandwidth of row bus 3012, peak bandwidth, valley bandwidth and average bandwidth；In
Portion's width monitoring unit 3023 is according to the data traffic of NUMA chip 3013 each internal bus internal
Situation, calculates the real-time bandwidth of each internal bus, peak bandwidth, valley bandwidth and average bandwidth respectively.
In embodiments of the present invention, being directed to a bus, real-time bandwidth is this bus in nearest 1 second
The total amount of secured transmission of payload data, wherein, the total amount of valid data is the total amount of bi-directional transfer of data；Peak value
With a width of maximum started to current time real-time bandwidth from monitoring；Valley band a width of from monitoring start to
The non-zero minimum of current time real-time bandwidth；Each is real in order to start to the current time from monitoring for average bandwidth
The meansigma methods of Time Bandwidth.
Such as, NUMA chip core clock frequency F is 600MHz, takes F/100 clock cycle work
Be a bandwidth sampling period, i.e. 6 clock cycle as a bandwidth sampling period, upper row bus
Bit wide is w, occurs in that m valid data message altogether in the current bandwidth sampling period on upper row bus,
Real-time bandwidth BW [C] corresponding to current bandwidth sampling period can be calculated by equation below and obtain:
Wherein, the unit calculating the real-time bandwidth BW [C] obtained is GB/s, takes F/100 clock cycle
Calculating speed can be improved as a bandwidth sampling period；
It is the L second from starting the data traffic of upper row bus is monitored to the time span of current time,
Then according to calculating each real-time bandwidth BW [C] of acquisition in this L second,
By equation below calculating peak bandwidth BW [P]:
BW [P]=max{BW [C] }
By equation below calculating valley bandwidth BW [V]:
BW [V]=min{BW [C] } ≠ 0
By equation below calculating average bandwidth BW [A]:
BW [A]=average{BW [C] }
Correspondingly, lower row bus and the real-time bandwidth of each internal bus, peak value are calculated by the way
Bandwidth, valley bandwidth and average bandwidth.
Step 403: the band data determined is stored status register corresponding in NUMA chip
In.
In an embodiment of the invention, what upstream bandwidth monitoring means 3021 was obtained by memory element is up
In the real-time bandwidth of bus, peak bandwidth, valley bandwidth and average bandwidth storage NUMA chip 3013
In corresponding uplink state depositor, the lower row bus that downlink bandwidth monitoring means 3022 is obtained real-time
In bandwidth, peak bandwidth, valley bandwidth and average bandwidth storage NUMA chip 3013, correspondence is descending
In status register, the real-time bandwidth of each internal bus that internal bandwidth monitoring means 3023 is obtained,
Peak bandwidth, valley bandwidth and average bandwidth store internal state corresponding in NUMA chip and deposit
In device.
Such as, the band data of the upper row bus that upstream bandwidth monitoring means 3021 is obtained by memory element is deposited
Storing up in uplink state depositor, form the record data shown in table 1, table 1 is as follows:
Table 1
| Band merit | Upper row bus |
| Real-time bandwidth BW [C] | |
| Peak bandwidth BW [P] | |
| Valley bandwidth BW [V] | |
| Average bandwidth BW [A] |
The band data of the lower row bus that downlink bandwidth monitoring means 3022 is obtained by memory element stores
In downstream state depositor, forming the record data shown in table 2, table 2 is as follows:
Table 2
| Band merit | Lower row bus |
| Real-time bandwidth BW [C] | |
| Peak bandwidth BW [P] | |
| Valley bandwidth BW [V] | |
| Average bandwidth BW [A] |
The band data of each internal bus that internal bandwidth monitoring means 3023 obtains is deposited by memory element
Storing up in internal status register, form the record data shown in table 3, table 3 is as follows:
Table 3
| Band merit | Internal bus 1 | Internal bus 2 | …… | Internal bus n |
| Real-time bandwidth BW [C] | ||||
| Peak bandwidth BW [P] | ||||
| Valley bandwidth BW [V] | ||||
| Average bandwidth BW [A] |
Step 404: by the Status register that baseboard management controller BMC is corresponding from NUMA chip
Device reads band data.
In an embodiment of the invention, unit is read by baseboard management controller BMC from NUMA
The status register that chip is corresponding reads upper row bus, lower row bus and the reality of each internal bus in real time
Time Bandwidth, peak bandwidth, valley bandwidth and average bandwidth, it is achieved in NUMA chip part band
Wide real-time monitoring.
It should be noted that in order to the NUMA chip bandwidth that the embodiment of the present invention provides clearly is described
The method of monitoring, as shown in Fig. 1 and Fig. 4, is divided into multiple step by the method, real at practical business
During Xian, between each step, there is no a strict sequencing, such as step 101, step 102 and
Step 103 can perform simultaneously.
The method of NUMA chip width monitoring of embodiment of the present invention offer, Apparatus and system, at least
Have the advantages that
1, in the embodiment of the present invention, respectively to the upper row bus of NUMA chip, lower row bus and inside
Data traffic in bus is monitored, it is thus achieved that corresponding up bus bandwidth data, descending bus bar
Wide data and each internal bus band data, wherein, up bus bandwidth data represent NUMA core
The bandwidth situation that each NUMA chip of sheet and other carries out data transmission, descending bus bandwidth data generation
The bandwidth situation that table NUMA chip carries out data transmission with each processor in same NUMA node,
Internal bus band data represents and carries out data biography between corresponding each functional module of NUMA chip internal
Defeated bandwidth situation.By being upper row bus, lower row bus and interior by the bandwidth partition of NUMA chip
Portion's bus, obtains the bandwidth of three kinds of dissimilar buses such that it is able to determine that NUMA chip has respectively
The bandwidth situation of body.
2, in the embodiment of the present invention, the bandwidth of upper row bus, lower row bus and each internal bus is carried out
During monitoring, it is possible to obtain real-time bandwidth, peak bandwidth, valley bandwidth and the average band that each bus is corresponding
Width, is characterized the bandwidth situation of each bus by multiple band merits, improves NUMA
The accuracy that chip bandwidth is monitored.
3, in the embodiment of the present invention, when NUMA chip is carried out width monitoring, respectively to upper row bus,
The bandwidth situation of lower row bus and each internal bus is monitored, and improves NUMA chip bandwidth
Be monitored is comprehensive.
4, in the embodiment of the present invention, go the BMC can be in real time from NUMA core by substrate management control
The status register that sheet is corresponding reads required band data, thus realizes the band to NUMA chip
Wide feature monitors in real time.
5, in the embodiment of the present invention, by the bandwidth performance of NUMA each bus of chip is carried out in real time
Monitoring, quickly can position the design defect causing NUMA chip bandwidth to reduce, thus carry
The high efficiency that NUMA chip is debugged.
The contents such as the information between each unit in said apparatus is mutual, execution process, due to the present invention
Embodiment of the method is based on same design, and particular content can be found in the narration in the inventive method embodiment, this
Place repeats no more.
It should be noted that in this article, the relational terms of such as first and second etc be used merely to by
One entity or operation separate with another entity or operating space, and not necessarily require or imply this
Relation or the order of any this reality is there is between a little entities or operation.And, term " includes ",
" comprise " or its any other variant is intended to comprising of nonexcludability, so that include that one is
The process of row key element, method, article or equipment not only include those key elements, but also include the brightest
Other key elements really listed, or also include intrinsic for this process, method, article or equipment
Key element.In the case of there is no more restriction, statement " include one " and limit
Key element, it is not excluded that there is also another in including the process of described key element, method, article or equipment
Outer same factor.
One of ordinary skill in the art will appreciate that: realize all or part of step of said method embodiment
Can be completed by the hardware that programmed instruction is relevant, aforesaid program can be stored in embodied on computer readable
Storage medium in, this program upon execution, performs to include the step of said method embodiment；And it is aforementioned
Storage medium include: various Jie that can store program code such as ROM, RAM, magnetic disc or CD
In matter.
Last it should be understood that the foregoing is only presently preferred embodiments of the present invention, it is merely to illustrate this
The technical scheme of invention, is not intended to limit protection scope of the present invention.All spirit in the present invention and former
Any modification, equivalent substitution and improvement etc. done within then, are all contained in protection scope of the present invention.
Claims (10)
1. the method for a NUMA chip width monitoring, it is characterised in that including:
The data traffic of upper row bus is monitored, it is thus achieved that up bus bandwidth data, wherein, described
Upper row bus is the bus that each NUMA chip of described NUMA chip and other carries out data transmission；
The data traffic of lower row bus is monitored, it is thus achieved that descending bus bandwidth data, wherein, described
Lower row bus is that described NUMA chip carries out data transmission with each processor in same NUMA node
Bus；
The data traffic of each internal bus of described NUMA chip is monitored, it is thus achieved that in each
The internal bus band data that portion's bus is corresponding, wherein, described internal bus is described NUMA chip
The bus that internal any two functional module carries out data transmission；
By described up bus bandwidth data, descending bus bandwidth data and each internal bus bandwidth number
According in status register corresponding in storage to described NUMA chip.
Method the most according to claim 1, it is characterised in that
Described up bus bandwidth data include: the real-time bandwidth of described upper row bus, peak bandwidth, paddy
Be worth in bandwidth and average bandwidth is any one or more；
And/or,
Described descending bus bandwidth data include: the real-time bandwidth of described lower row bus, peak bandwidth, paddy
Be worth in bandwidth and average bandwidth is any one or more；
And/or,
Described internal bus band data includes: the corresponding real-time bandwidth of internal bus, peak bandwidth, paddy
Be worth in bandwidth and average bandwidth is any one or more.
Method the most according to claim 2, it is characterised in that
Described real-time bandwidth includes: the total amount of corresponding bus transfer valid data in nearest a second；
And/or,
Described peak bandwidth includes: the maximum of corresponding real-time bandwidth in storage and monitoring time segment；
And/or,
Described valley bandwidth includes: the non-zero minimum of corresponding real-time bandwidth in storage and monitoring time segment；
And/or,
Described average bandwidth includes: the meansigma methods of each described real-time bandwidth corresponding in storage and monitoring time segment.
Method the most according to claim 3, it is characterised in that
The total amount of described valid data includes: total amount and this correspondence of the valid data that corresponding bus receives are total
The total amount of the valid data that line sends.
5. according to described method arbitrary in Claims 1-4, it is characterised in that farther include:
From described status register, described up bus bandwidth is read by baseboard management controller BMC
Any one or more in data, descending bus bandwidth data and each internal bus band data,
So that described NUMA chip is carried out bandwidth performance analysis.
6. the device of a NUMA chip width monitoring, it is characterised in that including: upstream bandwidth is supervised
Survey unit, downlink bandwidth monitoring means, internal bandwidth monitoring means and memory element；
Described upstream bandwidth monitoring means, for being monitored the data traffic of upper row bus, it is thus achieved that on
Row bus band data, wherein, described upper row bus is described NUMA chip and other each NUMA
The bus that chip carries out data transmission；
Described downlink bandwidth monitoring means, for being monitored the data traffic of lower row bus, it is thus achieved that under
Row bus band data, wherein, described lower row bus is that described NUMA chip saves with same NUMA
The bus that in point, each processor carries out data transmission；
Described internal bandwidth monitoring means, for each internal bus to described NUMA chip internal
Data traffic be monitored, it is thus achieved that the internal bus band data that each internal bus is corresponding, wherein,
Described internal bus be described NUMA chip internal any two functional module carry out data transmission total
Line；
Described memory element, for by described upstream bandwidth monitoring means obtain up bus bandwidth data,
Descending bus bandwidth data and described internal bandwidth monitoring means that described downlink bandwidth monitoring means obtains obtain
Each internal bus band data obtained stores in status register corresponding in described NUMA chip.
Device the most according to claim 6, it is characterised in that
Described upstream bandwidth monitoring means, for the data traffic according to described upper row bus, it is thus achieved that described
Any one or more in the real-time bandwidth of upper row bus, peak bandwidth, valley bandwidth and average bandwidth；
And/or,
Described downlink bandwidth monitoring means, for the data traffic according to described lower row bus, it is thus achieved that described
Any one or more in the real-time bandwidth of lower row bus, peak bandwidth, valley bandwidth and average bandwidth；
And/or,
Described internal bandwidth monitoring means, for the data traffic according to each internal bus, it is thus achieved that corresponding
Any one or more in the real-time bandwidth of internal bus, peak bandwidth, valley bandwidth and average bandwidth.
8. according to the device described in claim 6 or 7, it is characterised in that farther include: read single
Unit；
Described reading unit, for reading from described status register by baseboard management controller BMC
Take in described up bus bandwidth data, descending bus bandwidth data and each internal bus band data
Any one or more, monitor in real time with the bandwidth situation to described NUMA chip.
Device the most according to claim 7, it is characterised in that
Appointing in described upstream bandwidth monitoring means, downlink bandwidth monitoring means and internal bandwidth monitoring means
Anticipate and one or more include bandwidth statistics logic circuit.
10. the system of a NUMA chip width monitoring, it is characterised in that including: at least two
Arbitrary described NUMA chip bandwidth prison in the claim 6 to 9 of NUMA node and respective amount
The device surveyed；
Processor in described NUMA node, for by NUMA node each described
NUMA chip, accesses the data in the internal memory of each NUMA node, with row bus on described,
Data traffic is produced on lower row bus and internal bus.
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| US20050018697A1 (en) * | 1996-07-25 | 2005-01-27 | Hybrid Networks, Inc. | High-speed internet access system |
| CN103324592A (en) * | 2013-06-24 | 2013-09-25 | 华为技术有限公司 | Data migration control method, data migration method and data migration device |
| CN103530191A (en) * | 2013-10-18 | 2014-01-22 | 杭州华为数字技术有限公司 | Hot spot recognition processing method and device |
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|---|---|---|---|---|
| US20050018697A1 (en) * | 1996-07-25 | 2005-01-27 | Hybrid Networks, Inc. | High-speed internet access system |
| CN103324592A (en) * | 2013-06-24 | 2013-09-25 | 华为技术有限公司 | Data migration control method, data migration method and data migration device |
| CN103530191A (en) * | 2013-10-18 | 2014-01-22 | 杭州华为数字技术有限公司 | Hot spot recognition processing method and device |
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