CN105883712A - 具有支撑结构的微元件的制作方法 - Google Patents
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- 238000010276 construction Methods 0.000 claims description 57
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 31
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
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Abstract
一种具有支撑结构的微元件的制作方法,包含以下步骤:提供一第一晶圆;形成一与该第一晶圆接合的第一结构层;形成多个至少贯穿该第一结构层的沟槽,以界定出多个结构体;及可选择地对应至少一结构体形成一支撑结构,该支撑结构由介电材料形成且连接该结构体及该第一晶圆,以加强该结构体与该第一晶圆的接合强度。借此,避免结构体受后续制程应力作用与第一晶圆分离,而提升制程良率与元件的可靠度。
Description
技术领域
本发明涉及一种制作方法,特别是涉及一种具有支撑结构的微元件的制作方法。
背景技术
参阅图1,现有的一种微元件,例如电容感测元件,包含一下电极层91、一介电层92、一上电极层93及一金属层94。下电极层91材质为低阻值硅。介电层92材质为二氧化硅形成于下电极层91上且具有多个空腔921。上电极层93材质为低阻值硅,一般以晶圆接合方式与介电层92连接。金属层94形成在上电极层93上且为导电金属。金属层94与上电极层93一起图案化而形成多个上电极单元95,相邻的上电极单元95以沟槽96间隔开而互相绝缘。
然而,由于上电极层93与介电层92之间的接合面积小,容易因为膜层堆栈的应力而脱层(peeling),大幅降低制程的良率。此外,当微元件施加高电压操作时,相邻的两上电极单元95容易发生崩溃(break down)毁损,也使得可靠性不佳。
发明内容
因此,本发明的其中一目的在于提供一种可提升良率的具有支撑结构的微元件的制作方法。
本发明的具有支撑结构的微元件的制作方法在一些实施态样中,是包含以下步骤:
提供一第一晶圆;
形成一与该第一晶圆接合的第一结构层;
形成多个至少贯穿该第一结构层的沟槽,以界定出多个结构体;及
可选择地对应至少一结构体形成一支撑结构,该支撑结构由介电材料形成且连接该结构体及该第一晶圆,以加强该结构体与该第一晶圆的接合强度。
在一些实施态样中,该第一晶圆包括一第一基材及一形成于该第一基材表面的第一绝缘层,且该第一结构层与该第一绝缘层连接。
在一些实施态样中,连接有该支撑结构的结构体与该第一晶圆的接触区域的宽度小于10um。
在一些实施态样中,该第一绝缘层具有多个凹槽;该第一结构层覆盖所述凹槽且所形成的沟槽位置与所述凹槽相错开。
在一些实施态样中,所述沟槽贯穿该第一结构层及部分该第一晶圆。
在一些实施态样中,形成所述支撑结构后,还包含在该第一结构层表面形成一第二结构层的步骤。
在一些实施态样中,该第二结构层未覆盖所述相邻结构体间的沟槽处。
在一些实施态样中,所述结构体与该第一基材相配合分别形成一电极单元,且该第一基材的材质为低阻值硅以作为所述电极单元的下电极,且该第一结构层的材质为低阻值硅以使所述结构体作为所述电极单元的上电极。
在一些实施态样中,该支撑结构由该结构体靠近侧缘的上表面区域延伸至该第一晶圆界定对应沟槽的至少一部分表面区域。
在一些实施态样中,形成该支撑结构的材料选自二氧化硅、氮化硅、苯丙环丁烯(Benzocyclobutene,BCB)、聚乙烯胺(polyimide)及光阻剂。
在一些实施态样中,形成该第一结构层的步骤包括提供一第二晶圆并将该第二晶圆与该第一晶圆接合,再将该第二晶圆厚度减少而形成该第一结构层。
在一些实施态样中,该第二晶圆包括一第一硅层、一第二硅层及一夹置于该第一硅层与该第二硅层之间的第二绝缘层;该第二晶圆是透过该第一硅层与该第一晶圆接合,而且将该第二晶圆厚度减少的步骤是移除该第二硅层及该第二绝缘层而使该第一硅层形成该第一结构层。
本发明的功效在于:借由支撑结构将结构体与第一晶圆连结固定,能够强化结构体与第一晶圆的接合强度,避免结构体受后续制程应力作用与第一晶圆分离,而提升制程良率与元件可靠度。而且,借由支撑结构也能在后续制程,避免蚀刻溶液渗入结构体与第一晶圆的接合界面。此外,支撑结构为介电材料制成,可以使结构体的侧面有较佳的绝缘特性。
附图说明
本发明的其它的特征及功效,将于参照图式的实施例详细说明中清楚地呈现,其中:
图1是一截面示意图,说明现有一种电容感测元件的局部结构;
图2是一方块图,说明本发明具有支撑结构的微元件的制作方法的一实施例的步骤流程;
图3至图7是说明该实施例的实施步骤对应形成的结构的截面示意图;
图8是一俯视示意图,说明该实施例形成的微元件的结构的平面分布;
图9与图10是说明该实施例形成沟槽的另一实施态样的截面示意图;
图11是一截面示意图,说明该实施例可形成不同结构形态的微元件;
图12是一图11的俯视示意图,说明该实施例的支撑结构可具有不同态样。
具体实施方式
在本发明被详细描述之前,应当注意在以下的说明内容中,类似的元件是以相同的编号来表示。
参阅图2,本发明具有支撑结构的微元件的制作方法的一实施例主要包含以下步骤:
步骤S1,提供一第一晶圆;
步骤S2,形成一与该第一晶圆接合的第一结构层;
步骤S3,形成多个至少贯穿该第一结构层的沟槽,以界定出多个结构体;及
步骤S4,可选择地对应至少一结构体形成一支撑结构,该支撑结构由介电材料形成且连接该结构体及该第一晶圆,以加强该结构体与该第一晶圆的接合强度。
以下配合其它图式详细说明实施步骤,在本实施例是以制作电容感测元件为例说明,但本发明不以制作电容感测元件为限,其也可应用于其它以晶圆接合方式为基础所制成的微元件。
参阅图3,说明步骤S1提供一第一晶圆1。在本实施例中,第一晶圆1包括一第一基材10及一形成于该第一基材10表面的第一绝缘层11。再者,第一晶圆1由一低阻值晶圆在表面以热氧化制程形成二氧化硅层所形成,故该第一基材10的材质为低阻值硅,其阻值范围约为1~0.01ohm-cm,且该第一绝缘层11的材质为二氧化硅。此外,该第一绝缘层11具有多个凹槽12。
参阅图4,说明步骤S2,形成一与该第一晶圆1接合的第一结构层20。在本实施例中,先提供一第二晶圆2,将该第二晶圆2与该第一晶圆1接合,再将该第二晶圆2厚度减少而形成该第一结构层20。其中,接合的方式可采用熔合接合(fusion bonding)等微机电制程中常用的接合方法。第二晶圆2采用SOI晶圆,包括一第一硅层21、一第二硅层22及一夹置于该第一硅层21与该第二硅层22之间的第二绝缘层23。该第二晶圆2是透过该第一硅层21与该第一晶圆1接合,且于接合后还进一步包含将该第二晶圆2厚度减少的步骤,也就是说移除该第二硅层22及该第二绝缘层23,仅留下第一硅层21而形成该第一结构层20,且该第一结构层20的材质为低阻值硅。本实施步骤的第二晶圆2也可采用单层的低阻值硅晶圆,并视第二晶圆2的厚度决定与第一晶圆1接合后是否需要进一步减少第二晶圆2的厚度,若第二晶圆2本身的厚度已经够薄,在接合后即可直接做为第一结构层20,无需进行减薄的步骤,但若第二晶圆2的厚度较厚,再进行减薄的步骤以形成第一结构层20。
参阅图5,说明步骤S3,形成多个贯穿该第一结构层20的沟槽3。在本实施例是要制作电容感测元件,所以在形成所述沟槽3前还可包含形成多个贯穿该第一结构层20及该第一绝缘层11的穿孔30(配合参见图8)的步骤,以在所述穿孔30处露出该第一基材10。形成穿孔30后,再于该第一结构层20形成沟槽3且所形成的沟槽3位置与所述凹槽12相错开。借由所述沟槽3界定出多个结构体24,所述结构体24与该第一基材10相配合分别形成一电极单元4,且该第一基材10作为所述电极单元4的下电极,而所述结构体24作为所述电极单元4的上电极。本实施例中,沟槽3仅贯穿第一结构层20,但是在另一实施态样,沟槽3也可以进一步蚀刻部分该第一晶圆1,例如贯穿第一绝缘层11及蚀刻部分该第一基材10(见图9)。
参阅图6,说明步骤S4,以介电材料在至少一结构体24形成一支撑结构5,使该支撑结构5连接该结构体24及该第一晶圆1,以加强该结构体24与该第一晶圆1的接合强度。该支撑结构5可由形成一介电材料层后再图案化该介电材料层而成。形成该支撑结构5的材料可选自二氧化硅、氮化硅、苯丙环丁烯(Benzocyclobutene,BCB)、聚乙烯胺(polyimide)及光阻剂。由于形成介电材料层时的温度亦会产生应力使结构体24与第一晶圆1分离,因此较低的介电材料层形成温度(如小于400℃)为较佳之选择。在本实施例中,每一结构体24的相反两侧都形成一支撑结构5,且支撑结构5由该结构体24靠近侧缘的上表面242区域延伸至该第一晶圆1界定对应沟槽3的至少一部分表面区域,也就是说由结构体24的上表面242区域延伸通过结构体24的侧面241直至第一晶圆1相邻该侧面241的表面区域,借此支撑结构5可达到强化结构体24与第一晶圆1的接合强度的效果,然而,若支撑结构5未延伸至上表面242区域也可实施。而且,支撑结构5可以是一整体或由多个相间隔的子部分51构成(见图12)。此外,在本实施例中,支撑结构5覆盖第一晶圆1的表面是第一绝缘层11表面,但是,若沟槽3贯穿第一绝缘层11时,支撑结构5可延伸覆盖第一基材10表面(见图10)。在同一沟槽3处的相邻支撑结构5可以连接或断开,也可填满沟槽3,并不限制。
参阅图7与图8,形成所述支撑结构5后,还可包含在该第一结构层20表面形成一第二结构层6的步骤。在本实施例中,第二结构层6的材质为金属且未覆盖相邻结构体24间的沟槽3处,也就是说形成一图案化的导电层60,使该导电层60包括多个分别有部分覆盖所述结构体24的上表面242的上电极导电部61,及多个分别对应所述穿孔30覆盖该第一基材10的下电极导电部62。所述下电极导电部62用以作为下电极焊垫以供外部导线焊接,且所述上电极导电部61除覆盖于结构体24外还有部份作为所述电极单元4的上电极焊垫以供外部导线焊接。由于第二结构层6未覆盖相邻结构体24间的沟槽3处,使得相邻结构体24的上电极导电部61于沟槽3处未互相连接,而能分隔各结构体24间的电子信号。
通常第二结构层6于沉积过程中会由于沉积温度或原子于沉积接口上的排列致密程度等因素而产生内应力(intrinsic stress),该应力所造成的拉伸力量若大于结构体24与第一晶圆1间的接合力量,将造成结构体24由第一晶圆1表面剥离或脱落,因此借由支撑结构5分别连接于结构体24的相反两侧面241并与该第一晶圆1连接,可以使结构体24与第一晶圆1的结合更为稳固。例如当结构体24与第一晶圆1的接触区域的宽度W小于10um时,由于接合面积较小,因此接合力量亦较小,易使结构体24与第一晶圆1分离,而借由支撑结构5连结固定结构体24与第一晶圆1,能够强化结构体24与第一晶圆1的接合强度,避免结构体24受应力作用与第一晶圆1分离。而且,借由所述支撑结构5也能在后续制程中,例如形成图案化的导电层60,避免蚀刻溶液渗入结构体24与第一晶圆1的接合界面。此外,在本实施例中,由于所述支撑结构5为介电材料制成,可以提供良好的绝缘特性,以降低相邻电极单元4之间因结构体24侧面241粗糙,在高电压(如200至300伏特)操作时产生尖端放电而发生元件崩溃的风险。特别是使用热氧化制程来成长形成支撑结构5的介电材料时,由于在成长过程中亦会消耗结构体24的硅材料,若原本在结构体24的侧面241上存在尖端结构,则尖端结构有机会被氧化成二氧化硅,因此可避免尖端放电效应产生。
虽然在本实施例中是以制作电容感测元件为例说明,但是本发明还可适用例如图11与图12所示的不同结构形态的微元件,而且在同一晶圆上可以形成不同结构形态的结构体24,可以选择在其中需要强化接合强度的结构体24形成支撑结构5,特别是结构体24与第一晶圆1的接触区域的宽度W小于10um的类型,也就是与第一晶圆1接合面积较小的结构体24,即可借由支撑结构5来强化结构体24与第一晶圆1的接合强度。而且支撑结构5可为环绕整个结构体24的一整体或只覆盖结构体24的单一侧的一整体,或者支撑结构5可由多个子部分51构成而相间隔的分布于结构体24的相反两侧或沿周侧分布,可视需求调整并不限制。
综上所述,借由支撑结构5将结构体24与第一晶圆1连结固定,能够强化结构体24与第一晶圆1的接合强度,避免结构体24受后续制程应力作用与第一晶圆1分离,而提升制程良率与元件可靠度。而且,借由支撑结构5也能在后续制程,避免蚀刻溶液渗入结构体24与第一晶圆1的界面。此外,支撑结构5为介电材料制成,可以提供结构体24的侧面241有较佳的绝缘特性。
以上所述,仅为本发明的实施例而已,当不能以此限定本发明实施的范围,即凡依本发明权利要求书及说明书内容所作的简单的等效变化与修饰,皆仍属本发明的范围。
Claims (12)
1.一种具有支撑结构的微元件的制作方法,其特征在于:包含以下步骤:
提供一第一晶圆;
形成一与该第一晶圆接合的第一结构层;
形成多个至少贯穿该第一结构层的沟槽,以界定出多个结构体;及
可选择地对应至少一结构体形成一支撑结构,该支撑结构由介电材料形成且连接该结构体及该第一晶圆,以加强该结构体与该第一晶圆的接合强度。
2.根据权利要求1所述具有支撑结构的微元件的制作方法,其特征在于:该第一晶圆包括一第一基材及一形成于该第一基材表面的第一绝缘层,且该第一结构层与该第一绝缘层连接。
3.根据权利要求1或2所述具有支撑结构的微元件的制作方法,其特征在于:连接有该支撑结构的结构体与该第一晶圆的接触区域的宽度小于10um。
4.根据权利要求2所述具有支撑结构的微元件的制作方法,其特征在于:该第一绝缘层具有多个凹槽;该第一结构层覆盖所述凹槽且所形成的沟槽位置与所述凹槽相错开。
5.根据权利要求1所述具有支撑结构的微元件的制作方法,其特征在于:所述沟槽贯穿该第一结构层并蚀刻部分该第一晶圆。
6.根据权利要求1所述具有支撑结构的微元件的制作方法,其特征在于:形成该支撑结构后,还包含在该第一结构层表面形成一第二结构层的步骤。
7.根据权利要求6所述具有支撑结构的微元件的制作方法,其特征在于:该第二结构层未覆盖所述相邻结构体间的沟槽处。
8.根据权利要求1所述具有支撑结构的微元件的制作方法,其特征在于:所述结构体与该第一基材相配合分别形成一电极单元,且该第一基材的材质为低阻值硅以作为所述电极单元的下电极,且该第一结构层的材质为低阻值硅以使所述结构体作为所述电极单元的上电极。
9.根据权利要求1所述具有支撑结构的微元件的制作方法,其特征在于:该支撑结构由该结构体靠近侧缘的上表面区域经由该侧缘延伸至该第一晶圆界定对应沟槽的至少一部分表面区域。
10.根据权利要求1所述具有支撑结构的微元件的制作方法,其特征在于:形成该支撑结构的材料选自二氧化硅、氮化硅、苯丙环丁烯、聚乙烯胺及光阻剂。
11.根据权利要求1所述具有支撑结构的微元件的制作方法,其特征在于:形成该第一结构层的步骤包括提供一第二晶圆并将该第二晶圆与该第一晶圆接合,再将该第二晶圆厚度减少而形成该第一结构层。
12.根据权利要求11所述具有支撑结构的微元件的制作方法,其特征在于:该第二晶圆包括一第一硅层、一第二硅层及一夹置于该第一硅层与该第二硅层之间的第二绝缘层;该第二晶圆是透过该第一硅层与该第一晶圆接合,而且将该第二晶圆厚度减少的步骤是移除该第二硅层及该第二绝缘层而使该第一硅层形成该第一结构层。
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002324815A (ja) * | 2001-04-25 | 2002-11-08 | Tdk Corp | 電子装置の製造方法 |
CN1705124A (zh) * | 2004-06-02 | 2005-12-07 | 卡西欧计算机株式会社 | 半导体器件及其制造方法 |
CN1897258A (zh) * | 2002-03-26 | 2007-01-17 | 夏普公司 | 半导体器件及其制法、soi衬底及其制法和其显示器件 |
US20070218584A1 (en) * | 2006-03-14 | 2007-09-20 | Chih-Hsien Chen | Method for wafer-level package |
CN101207113A (zh) * | 2006-12-19 | 2008-06-25 | 台湾积体电路制造股份有限公司 | 半导体结构及其制造方法 |
CN102148262A (zh) * | 2010-02-08 | 2011-08-10 | 艾普特佩克股份有限公司 | 电子装置封装及其制造方法 |
CN103438936A (zh) * | 2013-09-02 | 2013-12-11 | 东南大学 | 基于soi片器件层硅阳极键合的电容式温度、湿度和气压传感器集成制造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8119500B2 (en) * | 2007-04-25 | 2012-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer bonding |
US8735260B2 (en) * | 2010-12-13 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to prevent metal pad damage in wafer level package |
-
2015
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Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002324815A (ja) * | 2001-04-25 | 2002-11-08 | Tdk Corp | 電子装置の製造方法 |
CN1897258A (zh) * | 2002-03-26 | 2007-01-17 | 夏普公司 | 半导体器件及其制法、soi衬底及其制法和其显示器件 |
CN1705124A (zh) * | 2004-06-02 | 2005-12-07 | 卡西欧计算机株式会社 | 半导体器件及其制造方法 |
US20050269698A1 (en) * | 2004-06-02 | 2005-12-08 | Casio Computer Co., Ltd. | Semiconductor device having adhesion increasing film and method of fabricating the same |
US20070218584A1 (en) * | 2006-03-14 | 2007-09-20 | Chih-Hsien Chen | Method for wafer-level package |
CN101207113A (zh) * | 2006-12-19 | 2008-06-25 | 台湾积体电路制造股份有限公司 | 半导体结构及其制造方法 |
CN102148262A (zh) * | 2010-02-08 | 2011-08-10 | 艾普特佩克股份有限公司 | 电子装置封装及其制造方法 |
CN103438936A (zh) * | 2013-09-02 | 2013-12-11 | 东南大学 | 基于soi片器件层硅阳极键合的电容式温度、湿度和气压传感器集成制造方法 |
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