CN105872432A - Rapid self-adaptive frame rate conversion device and method - Google Patents
Rapid self-adaptive frame rate conversion device and method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/234—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
- H04N21/2343—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
- H04N21/234381—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements by altering the temporal resolution, e.g. decreasing the frame rate by frame skipping
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
- H04N21/440281—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by altering the temporal resolution, e.g. by frame skipping
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Abstract
The invention relates to the field of image processing and display and aims at providing a rapid self-adaptive frame rate conversion display device. The device can meet the demands for multiple kinds of video input and display equipment and rapidly achieve a self-adaptive frame rate conversion function according to system requirements in a real-time video system, and is high in universality. Meanwhile, in the high-speed cache process of data, the device can effectively process data loss or overflow in a self-adaptive mode, so that data transmission precision is effectively improved. According to the structure of the rapid self-adaptive frame rate conversion device, a video input control unit stores the data into a first row cache unit and a second row cache unit in an alternate storage mode; a window selection control unit screens and adjusts the row cache data in the first row cache unit and the row cache data in the second row cache unit to obtain effective row data of the same size; later, the effective row data is transmitted into a first-in-first-out (FIFO) memory. The device is mainly applied to image processing and display occasions.
Description
Technical field
The present invention relates to image procossing and display field, belong to caching process and the display category of real-time video.Concretely relate to fast
The apparatus and method of speed self adaptation frame rate conversion.
Background technology
Along with the development of commercial Application demand, various video image acquisition and display device and various video format emerge in an endless stream.
Owing to it each other itself can not be completely compatible, so needing distinct methods mutually to change.Frame rate conversion
As the effective means of one, different acquisition equipment video flowing under different frame per second can be risen to and meet multiple display device
Demand, is increasingly paid attention to by people.
Frame per second boosting algorithm is according to whether carrying out estimation and corresponding motion compensation can be divided into two big classes.The first kind is fortune
Dynamic compensation frame per second boosting algorithm, this algorithm mainly comprises estimation (Motion Estimation, ME) and motion compensation (Motion
Compensation, MC) two parts, main consider that inter motion information carrys out interpolation frame.Within 1993, De Hann proposes three-dimensional
Recursive search block matching algorithm is to increase the accuracy of estimation.Blume in 2002 et al. proposes image Segmentation Technology right
Zones of different is respectively adopted different estimations or compensation method to promote interpolation frame quality.Within 2004, Dane and Truoug proposes base
In variable-sized search window estimation the frame rate conversion algorithm that uses Full-search block matching algorithm.Lei Zhang in 2009 etc.
People proposes the estimation frame per second boosting algorithm processed based on weighting.This kind of frame rate conversion side comprising the complicated algorithms such as estimation
Although method can solve the fuzzy jitter phenomenon that moving object produces to a certain extent, but operation computation complexity is higher, and
Algorithm performance is directly proportional to complexity, brings the huge challenge on hardware cost.Another kind of is that non-motion compensation frame per second promotes calculation
Method, the means that the duplication of this dependence field or field Average Strategy carry out frame per second lifting are the most extensive on hardware is implemented, its advantage
Essentially consisting in realization simple, fast operation, hardware cost is low with design cost.But this simple strategy is generally based on solid
Fixed input and output frame per second ratio, determines fixing input and output velocity ratio, such as from 30 frames per second to the frame of 60 frames per second
Rate promotes, and first caches a two field picture in memorizer, then carries out writing a line and reads the alternately read-write of two row, i.e. ensures to read every time
Data volume is to write the twice of data stream, thus ensures that overall frame per second promotes the requirement of twice.Utilize large-scale cache resources to frame of video
Although the method being fixed multiple copies output can realize the function of frame rate conversion, but this method lacks extensibility,
The frame per second numerical value between fixing input and outut device and ratio can only be met.How to save circuit resource, and ensure video
Quality and effect on the premise of, quick efficient self-adapted carries out frame rate conversion, can be automatically adjusted the side of frame rate conversion ratio
Method there is also many challenges.
On the other hand, along with the fast development of semiconductor sensing technology, use high frame per second, large area array CCD camera to obtain high-quality
Amount, high-resolution view data are more and more extensive, and the data volume having thus resulted in hardware transport is greatly improved, and required precision
More and more stricter.This proposes challenge to the cache of image, it is necessary to use rational high speed image caching screening control mechanism,
The mistake being likely to occur on hardware transport carries out screening judge and correct.From the beginning of gathering view data, through data buffer storage,
Finally shown in real time by display devices such as VGA.This process usually uses Pingpang Memory technology.Ping-pong operation is commonly used for logarithm
According to the processing method of flow control, usually it is applied to pipeline system algorithm, completes seamless buffering and the process of data.But how to exist
During caching, the loss of data during hardware transport or spilling are effectively treated simultaneously, still have certain
Difficulty.
Summary of the invention
For overcoming the deficiencies in the prior art, it is contemplated that propose the display device of a kind of quick self-adapted frame rate conversion, it is possible to full
Foot various video input and the demand of display device, for system requirements in Real-time Video System, be rapidly completed adaptive frame
Rate mapping function, versatility is stronger.Simultaneously in data high-speed process of caching, with self adaptation, loss of data or spilling can be carried out
Effectively process, effectively promote data transmission precision.The hardware that the method is suitable in Real-time Video System realizes, and has versatility relatively
Strong feature, on the premise of meeting function and required precision, had both saved time and the energy of circuit design exploitation, had saved again
Valuable hardware resource also reduces power consumption.The technical solution used in the present invention is, the device of quick self-adapted frame rate conversion,
Structure is, video input control unit utilizes the mode of alternately storage that data are stored in the first row buffer unit respectively and the second row delays
Memory cell；Window selects control unit to be adjusted by the row cache data screening in the first row buffer unit and the second line buffer unit respectively
Effective row data of formed objects；After this, effective row data are delivered in pushup storage FIFO, when in FIFO
When data volume exceedes threshold value a, sending write data requests to storage address computation and administrative unit, storage address computation is single with management
Unit responds this write data requests, starts data transmission and data is stored in chip external memory, amounting to and open up in chip external memory
The memory space of three BANK is used for carrying out frame buffer, by rotation storage make reading and writing BANK address difference away from all the time 1 with
On；When another pushup storage FIFO data volume therein is less than threshold value b, will be to storage address computation and administrative unit
Send read data request, from chip external memory, after meeting with a response, read caching pixel data, another pushup storage described
FIFO drives module to be connected with output, by video frequency output driver element according to certain video formats output video data.
Video input control unit writes data into the first row buffer unit and the second line buffer unit uses ping-pong buffer mode,
First video input control unit caches data line to the first row buffer unit, then reads from the first row buffer unit when data
Going out while pushup storage FIFO, video input control unit now caches the second row data to the second line buffer unit；
With should data while the second line buffer unit reads into pushup storage FIFO, video input control unit is the most again
The third line data are cached, by that analogy to pushup storage FIFO.
The method of quick self-adapted frame rate conversion, utilizes video input control unit to take ping-pong buffer mode to write data into first
Line buffer unit caches data line with the second line buffer unit, first video input control unit to the first row buffer unit,
Then when data are while the first row buffer unit reads into pushup storage FIFO, video input control unit now to
Second line buffer unit caches the second row data；With data reading into pushup storage FIFO from the second line buffer unit
While, video input control unit caches the third line data to pushup storage FIFO the most again, by that analogy；When
When data volume in FIFO exceedes threshold value a, send write data requests to storage address computation with administrative unit, store address computation
Respond this write data requests with administrative unit, start data transmission and data are stored in chip external memory, in chip external memory
Amount to and open up the memory space of three BANK for carrying out frame buffer, make reading and writing BANK address difference away from the beginning by rotation storage
Eventually more than 1；Another pushup storage FIFO data volume therein less than threshold value b time, will to storage address computation with
Administrative unit sends read data request, reads caching pixel data after meeting with a response from chip external memory, and described another first enters elder generation
Going out memorizer FIFO drives module to be connected with output, by video frequency output driver element according to certain video formats output video data.
Same according to video input apparatus of data volume is entered to two row cache RAM write of first, second line buffer unit of soldier's pang structure
Step signal and reference signal determine, in the horizontal direction, when reading the data in row cache RAM, by reading RAM
The control of address, it is ensured that reading the concordance of data volume, the reading address i.e. controlling RAM at most reads fixed threshold, give up after
Unnecessary junk data, thus form window and intercept fixing consistent effective row data；In the vertical direction, controls at Xiang Hanghuan
Deposit total line number that when writing data in RAM, general requirements write is fixing, i.e. require each time after field sync signal, only retain before solid
Fixed effective row synchronizes and the data in row reference signal, is realized by row counting, using each field system chronizing impulse signal as meter
The reset terminal of number device, and by horizontal synchronizing pulse signal is as cumulative enable each time, only head office's counter is in effective range
Just can write data into row cache RAM.
Data are after window selects control unit, then are input to chip external memory through pushup storage FIFO and cache,
Open up three memory spaces BANK0, BANK1, BANK2 in chip external memory, fill region for according to video image size institute really
Fixed valid data caching interval, it is big that the memory utilization mode in the region, upper left side of each BANK is applicable to multiple image resolution ratio
Little, and have only to revise corresponding address computation and changing method；First first frame data are stored in BANK0, when the first frame
Video data writes completely, i.e. writes BANK address when jumping in BANK1, begins to respond to another pushup storage FIFO's
Read request, and from BANK0, read view data, when running through BANK0 mono-frame, it is judged that currently the most write by BANK1
And start to write BANK2, if i.e. judging, currently writing BANK address arrives BANK2, then explanation BANK1 writes the most completely, Ke Yikai
Begin from BANK1, to read new one-frame video data, if otherwise another pushup storage FIFO has read data request, the most again
Repeat to read the data in a current BANK0, by that analogy, repeat above judge process after this and be circulated reading
Write.
During frame rate conversion, in order to ensure the correct and stable of video data stream, need respectively the address of read-write BANK to be referred to
Pin strictly controls, read BANK address need the relative position according to the pointer of current write address with reading address pointer judge be
No switch over new address, when the pointer position of write-read BANK differs more than 1, the most do not include 1, strictly larger than 1, then illustrate
Having had the DSR that a frame is new, reading BANK can switch over；Firstly the need of the elder generation judging read-write BANK address pointer
Rear problem, is reading after BANK if writing BANK, then explanation is write BANK ratio and read BANK multi cycle one circle, now judges to read
When writing BANK pointer position, it should to writing after BANK adds 3 operations, then write-read pointer being done difference, result is said more than 1
Bright current read-write BANK address pointer differs from a more than BANK, can switch over reading BANK pointer, i.e. add 1 operation, from
And read new frame data to another pushup storage FIFO from chip external memory；If writing BANK reading before BANK,
Both then can directly do difference, and result differs from a more than BANK more than 1 same explanation current read-write BANK address pointer,
Can switch over reading BANK pointer, i.e. add 1 operation；Do poor result of calculation more than whereas and if be not more than 1, then read BANK
Address pointer keeps the most constant, i.e. repeats to read current frame data to another pushup storage FIFO from chip external memory
In；
Carry out strict switching control equally to writing BANK address pointer, i.e. need to ensure that writing BANK address to be switched to next time
BANK interval run through, the most currently write the moment of BANK0, need to judge that BANK1 is the most run through, if
Running through, will write BANK pointer and be switched in BANK1 write new data into BANK1, otherwise write pointer keeps constant, new data weight
Make carbon copies into BANK0.
The feature of the present invention and providing the benefit that:
The present invention designs the apparatus and method of a kind of quick self-adapted frame rate conversion.In this programme, frame per second promotes and has phase identification merit
Can, there is certain adaptivity, input and output frame per second the most within the specific limits is interior than interval, can be according to current read-write number
Judge whether needs present frame is replicated according to amount, and function self-adaptive adjusting video image size can be selected based on window, it is ensured that be defeated
Go out stable, the loss of data in video transmitting procedure or spilling are effectively treated, thus there is the higher suitability.This side
Formula is simple, it is not necessary to too much buffer unit, it is not required that complicated control stream signal.Avoid and put into too much design
Energy, and circuit is simple, resources occupation rate is low, is very suitable for real time video processing and the display system quick reality on hardware
Existing.
Accompanying drawing explanation
The device of Fig. 1 quick self-adapted fast frame rate conversion.
Fig. 2 row cache replaces storage organization and window selected control system.
Read pointer switching in Fig. 3 frame rate conversion process chip external memory.
Write pointer switching in Fig. 4 frame rate conversion process chip external memory.
Fig. 5 frame rate conversion procedure pointer calculates.
Detailed description of the invention
The display device of the quick self-adapted frame rate conversion that the present invention proposes: as it is shown in figure 1,101 is video input control unit,
Line buffer unit 1 (RAM 1) 102 stores for row cache with line buffer unit 2 (RAM 1) 103, utilizes alternately storage
Mode, selects control unit 104 by window, respectively by line buffer unit 1 102 and the row cache data in line buffer unit 2 103
Screening adjusts the row data of formed objects.After this, effective row data are delivered in FIFO1 (FIFO) 105, when
When data volume in FIFO1 105 exceedes threshold value a, (threshold value a can custom-configure according to video image size, typically can join
It is set to a line of inputted video image size), send write data requests, storage ground to storage address computation and administrative unit 106
Location calculates after responding this write data requests with administrative unit 106, starts data transmission and data is stored in chip external memory 107,
Chip external memory 107 amounts to and opens up the memory space of three BANK for carrying out frame buffer, by rotation storage make reading,
Write BANK address difference away from all the time more than 1, it is ensured that video data correct and stable.Data after memory buffer, FIFO2
108 therein data volume less than threshold value b time (threshold value b can custom-configure according to video image size, the most configurable
A line for output video image), read data request will be sent with administrative unit, from storage after meeting with a response to storage address computation
Device reads caching pixel data, between FIFO2 108, drives module to be connected, finally by video frequency output driver element 109 with output
According to certain video formats output video data.
Such as Fig. 1, video input control unit 101 writes data into line buffer unit 1 102 and uses with line buffer unit 2 103
Be ping-pong buffer mode, first video input control unit 101 to line buffer unit 1 102 cache data line, then
When data are while line buffer unit 1 102 reads into FIFO1 105, and video input control unit 101 is now to row cache
Unit 2 103 caches the second row data.With should data while line buffer unit 2 103 reads into FIFO1 105, depending on
Frequency input control unit 101 caches the third line data to line buffer unit 1 102, by that analogy the most again.
As shown in Fig. 2 (a), two row cache RAM write of soldier's pang structure enter data volume mainly to be believed according to the synchronization of video input apparatus
Number and reference signal determine, but owing to there is unstability and error on hardware transport, so the data volume often gone
And write total line number all it is possible that the unmatched situation of data volume, then can Video processing below and display be caused huge
Impact.In the horizontal direction, as shown in Fig. 2 (b), this programme is when reading the data in row cache RAM, by reading RAM
The control of address, it is ensured that reading the concordance of data volume, the reading address i.e. controlling RAM at most reads fixed threshold, give up after
Unnecessary junk data, thus form window and intercept fixing consistent effective row data.In the vertical direction, this programme controls
Total line number that when writing data in row cache RAM, general requirements write is fixing, i.e. requires, each time after field sync signal, only to retain
Above fix effective row to synchronize and the data in row reference signal, realized by row counting, by each field system chronizing impulse signal
As the reset terminal of enumerator, and by horizontal synchronizing pulse signal is as cumulative enable each time, only head office's counter is effectively
In the range of just can write data into row cache RAM.Control by above two directions, it is ensured that obtain from video input control unit
Data become the video data of fixing and stable effective size through window selected from suitable solution.
Data are after window selects control unit 104, then are input to chip external memory 107 through FIFO1 105 and cache.For
Complete frame per second and promote PGC demodulation function, as shown in Figure 3 and Figure 5, in chip external memory, open up three memory space BANK0,
BANK1, BANK2.Fill region for interval, on a left side of each BANK according to valid data caching determined by video image size
The memory utilization mode of upper area goes for multiple image resolution ratio size, and has only to revise corresponding address computation
With changing method.First first frame data are stored in BANK0, when one-frame video data writes completely, i.e. write BANK ground
When location is jumped in BANK1, begin to respond to the read request of FIFO2 108, and from BANK0, read view data, run through BANK0
During one frame, it is judged that currently the most write by BANK1 and start to write BANK2, if i.e. judging, currently writing BANK address arrives BANK2,
Then explanation BANK1 writes the most completely, can start to read new one-frame video data from BANK1, if otherwise FIFO2 108
There is read data request, then repeat the data read in a current BANK0, by that analogy, repeat after this above to sentence
Disconnected process is also circulated read-write.
During frame rate conversion, in order to ensure the correct and stable of video data stream, need respectively the address of read-write BANK to be referred to
Pin strictly controls.Read BANK address need the relative position according to the pointer of current write address with reading address pointer judge be
No switch over new address.When the pointer position of write-read BANK differed for more than 1 (not including 1, strictly larger than 1), then illustrate
Having had the DSR that a frame is new, reading BANK can switch over.Firstly the need of the elder generation judging read-write BANK address pointer
Rear problem, is reading after BANK if writing BANK, then explanation is write BANK ratio and read BANK multi cycle one circle, now judges to read
When writing BANK pointer position, it should to writing after BANK adds 3 operations, then write-read pointer being done difference, result is said more than 1
Bright current read-write BANK address pointer differs from a more than BANK, can switch over (i.e. adding 1 operation) to reading BANK pointer,
Thus read new frame data to FIFO2 108 from chip external memory 107.If writing BANK reading before BANK, the most permissible
Both directly do difference, and result differs from a more than BANK more than 1 same explanation current read-write BANK address pointer, can be right
Read BANK pointer and switch over (i.e. adding 1 operation).Do poor result of calculation more than whereas and if be not more than 1, then read BANK ground
Location pointer keeps the most constant, i.e. repeats to read current frame data from chip external memory 107 in FIFO2 108.
On the other hand for writing BANK address pointer, iff supporting frame per second lifting operation, it is ensured that reading frame per second is consistently higher than to be write
Enter frame per second, then write BANK address and can directly carry out adding 1 operation after often writing a frame, repeat
The circulation of 0-1-2-0-1-2-0-1-2.In order to improve adaptivity and versatility, can support more during frame rate conversion
Input and output frame per second ratio, even reduce frame per second, this programme carries out strict switching control equally to writing BANK address pointer, as
Shown in Fig. 4 and Fig. 5.I.e. need to ensure that the BANK interval next time writing BANK address to be switched to is run through.Such as when
Before write moment of BANK0, need to judge that BANK1 is the most run through, if running through, BANK pointer will be write and be switched to
Writing new data into BANK1 in BANK1, otherwise write pointer keeps constant, and new data is repeatedly written BANK0.
This method can support the video input of multiple types, and a kind of video formats included but not limited to is 720*576@50Mpbs,
I.e. resolution is 720*576, and frame per second is that 50 frames are per second.The clock frequency of video input control unit is 27MHz.Sheet external memory
Device selects DDR, and clock is 133MHz, and inputoutput data width is 128bit.All may be used due to DDR rising edge and trailing edge again
To be written and read, therefore actual frequency reaches 266MHz.Final Output Display Unit requires that frame per second 60Hz, i.e. frame per second are 60 frames
Per second.Because the row number of pixels of every two field picture is 720, therefore row cache 1102, row cache 2 103, FIFO1 105
All being chosen as 1024 with the degree of depth of FIFO2 108, reserve certain redundant space to facilitate, threshold signal based on full sky is controlled
Data transmission procedure processed.Additionally, due to row cache 1102, row cache 2 103 is joined directly together with video input apparatus, due to video
The output data width of input control unit is 16bit, therefore row cache 1102, row cache 2 103, the input of FIFO1 105
Data width is equally chosen as 16bit.And in order to quickly by one-row pixels information from FIFO1 105 through DDR 204 the most again
It is transferred in FIFO2 108, selects the input data width with FIFO2108 also to define the output data width of FIFO1 105
For the 128bit consistent with DDR.Window selects the inputoutput data width of control unit 104 consistent with video input control unit,
And the output output width of FIFO2108 is identical with video frequency output driver element 109.For clock frequency, row cache 1102 He
The input clock frequency of row cache 2 103 is identical with the output frequency of video input control unit, for 27MHz.Clock frequency during output
Rate is identical with window control unit and video frequency output driver element frequency, for 65MHz.And the input clock frequency of FIFO1 105
The most consistent with the output clock frequency of FIFO2 108 is 65MHz.The output clock frequency of FIFO1 105 is defeated with FIFO2's 108
Enter frequency owing to being connected with DDR, use the 266MHz consistent with DDR.
First video image exports from video input control unit 101, and first the first row Pixel Information is buffered in row cache 1 102
In, the data volume of write is determined with reference signal by the synchronization of video input control unit.When the first row data are from video input control
In unit processed after output, video input apparatus enters blanking zone.Now row cache 1 102 writes a line signal effectively, logical
Know that window selects control unit 104 to start to receive data, and screen fixed size.And row cache 2 103 then begins to receive the second row
The data of video input apparatus transmission.After window selects control unit 104 to receive the first row data and passed to FIFO1 105,
Judging whether the second row data write in row cache 2 103, if writing, starting to receive new data line from which, otherwise etc.
Treat.Row cache 1 102 and row cache 2 103 repetitive cycling above Pingpang Memory process.
In frame per second lift portion, when the data volume in FIFO1 105 exceedes threshold value a, to storage address computation and administrative unit
106 send write data requests, after storage address computation responds this write data requests with administrative unit 106, start data and transmit also
Data are stored in sheet peripheral storage device 107, amount in sheet peripheral storage device 107 and open up three BANK spaces for carrying out
First frame buffer the first frame data are stored in BANK0, when one-frame video data writes completely, i.e. write BANK address and jump to BANK1
Time middle, begin to respond to the read request of FIFO2 108, and from BANK0, read view data, when running through BANK0 mono-frame, sentence
Breaking and currently the most write by BANK1 and start to write BANK2, if i.e. judging, currently writing BANK address arrives BANK2, then illustrate
BANK1 writes the most completely, can start to read new one-frame video data from BANK1, if otherwise FIFO2 108 has reading
Request of data, then repeat the data read in a current BANK0, by that analogy, repeats above to judge after this
Journey is also circulated read-write.Then the data of FIFO2 108 are transferred to video frequency output driver element, unify sequential thus real continuously
Time process and show video information.
Claims (7)
1. a device for quick self-adapted frame rate conversion, is characterized in that, structure is, video input control unit utilizes alternately storage
Data are stored in the first row buffer unit and the second line buffer unit by mode respectively；Window selects control unit the first row to be cached respectively
Row cache data screening in unit and the second line buffer unit adjusts effective row data of formed objects；Will be effectively after this
Row data are delivered in pushup storage FIFO, when the data volume in FIFO exceedes threshold value a, to storage address meter
Calculating and send write data requests with administrative unit, storage address computation responds this write data requests with administrative unit, starts data and passes
Defeated and data are stored in chip external memory, amount in chip external memory and open up the memory space of three BANK for carrying out
Frame buffer, makes reading and writing BANK address difference away from all the time more than 1 by rotation storage；Another pushup storage FIFO
When data volume is less than threshold value b therein, read data request will be sent to storage address computation with administrative unit, meet with a response
After from chip external memory read caching pixel data, described another pushup storage FIFO with output driving module phase
Even, by video frequency output driver element according to certain video formats output video data.
The device of quick self-adapted frame rate conversion the most as claimed in claim 1, is characterized in that, data are write by video input control unit
Enter the first row buffer unit and the second line buffer unit use ping-pong buffer mode, first video input control unit to
The first row buffer unit caching data line, then reads into pushup storage FIFO when data from the first row buffer unit
While, video input control unit now caches the second row data to the second line buffer unit；With should data from the second row
While buffer unit reads into pushup storage FIFO, video input control unit stores to FIFO the most again
Device FIFO caches the third line data, by that analogy.
3. a method for quick self-adapted frame rate conversion, is characterized in that, utilizes video input control unit to take ping-pong buffer mode to incite somebody to action
Data write the first row buffer unit and the second line buffer unit, first video input control unit is to the first row buffer unit
Caching data line, then when data are while the first row buffer unit reads into pushup storage FIFO, video
Input control unit now caches the second row data to the second line buffer unit；With should data read from the second line buffer unit
While pushup storage FIFO, video input control unit is the most again to pushup storage FIFO caching the
Three row data, by that analogy；When the data volume in FIFO exceedes threshold value a, send out with administrative unit to storage address computation
Send write data requests, storage address computation to respond this write data requests with administrative unit, start data transmission and data are stored in
In chip external memory, amount in chip external memory and open up the memory space of three BANK for carrying out frame buffer, by wheel
Changing storage makes reading and writing BANK address difference away from all the time more than 1；Another pushup storage FIFO data therein
When amount is less than threshold value b, read data request will be sent with administrative unit, from sheet external memory after meeting with a response to storage address computation
Reading caching pixel data in device, described another pushup storage FIFO drives module to be connected with output, defeated by video
Go out driver element according to certain video formats output video data.
The method of quick self-adapted frame rate conversion the most as claimed in claim 3, is characterized in that, to first, second row of soldier's pang structure
Two row cache RAM write of buffer unit enter data volume and determine according to synchronizing signal and the reference signal of video input apparatus,
In the horizontal direction, when reading the data in row cache RAM, by RAM being read the control of address, it is ensured that read data
The concordance of amount, the reading address i.e. controlling RAM at most reads fixed threshold, gives up the most unnecessary junk data, thus shape
Window is become to intercept fixing consistent effective row data；In the vertical direction, controls when writing data in row cache RAM total
Require total line number that write is fixing, i.e. require each time after field sync signal, only retain before fix effective row and synchronize and row
Data in reference signal, are realized by row counting, using each field system chronizing impulse signal as the reset terminal of enumerator, and
By horizontal synchronizing pulse signal is as cumulative enable each time, only head office's counter just can write data in effective range
Row cache RAM.
The method of quick self-adapted frame rate conversion the most as claimed in claim 4, is characterized in that, data after window selects control unit,
It is input to chip external memory through pushup storage FIFO again cache, in chip external memory, opens up three storages
Space B ANK0, BANK1, BANK2, filling region is interval for caching according to valid data determined by video image size,
Memory utilization mode in the region, upper left side of each BANK is applicable to multiple image resolution ratio size, and has only to amendment
Corresponding address computation and changing method；First first frame data are stored in BANK0, when one-frame video data writes completely,
I.e. write BANK address when jumping in BANK1, begin to respond to the read request of another pushup storage FIFO, and from BANK0
Middle reading view data, when running through BANK0 mono-frame, it is judged that is currently the most write by BANK1 and starts to write BANK2,
If i.e. judging, currently writing BANK address arrives BANK2, then explanation BANK1 writes the most completely, can start from BANK1
Read new one-frame video data, if otherwise another pushup storage FIFO has read data request, then repeat reading
Data in a time current BANK0, by that analogy, repeat above judge process and are circulated read-write after this.
The method of quick self-adapted frame rate conversion the most as claimed in claim 5, is characterized in that, during frame rate conversion, in order to protect
Demonstrate,prove the correct and stable of video data stream, need respectively the address pointer reading and writing BANK strictly to be controlled, read BANK ground
Location needs the pointer according to current write address to judge whether to switch new address, when writing with the relative position reading address pointer
Read the pointer position difference more than 1 of BANK, the most do not include 1, strictly larger than 1, then the data that a frame is new are described
Being ready to, reading BANK can switch over；Firstly the need of judging to read and write the priority problem of BANK address pointer, if writing BANK
After reading BANK, then BANK ratio reading BANK multi cycle one circle is write in explanation, now judges read-write BANK pointer position
Time, it should to writing after BANK adds 3 operations, then write-read pointer being done difference, result is more than 1 explanation current read-write BANK
Address pointer differs from a more than BANK, can switch over reading BANK pointer, i.e. add 1 operation, thus from sheet external memory
Device reads new frame data in another pushup storage FIFO；If writing BANK reading before BANK, then can be straight
Connecing and both do difference, result differs from a more than BANK more than 1 same explanation current read-write BANK address pointer, can be right
Read BANK pointer to switch over, i.e. add 1 operation；Do poor result of calculation more than whereas and if be not more than 1, then read BANK
Address pointer keeps the most constant, i.e. repeats to read current frame data to another pushup storage from chip external memory
In FIFO.
The method of quick self-adapted frame rate conversion the most as claimed in claim 6, is characterized in that, enters equally writing BANK address pointer
The switching control that row is strict, i.e. needs to ensure that the BANK interval next time writing BANK address to be switched to is run through, i.e.
Currently write the moment of BANK0, need to judge that BANK1 is the most run through, if running through, BANK pointer will be write and cut
Changing to write new data in BANK1 BANK1, otherwise write pointer keeps constant, and new data is repeatedly written BANK0.
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