CN105870178B - A kind of two-way IGBT device and its manufacturing method - Google Patents
A kind of two-way IGBT device and its manufacturing method Download PDFInfo
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Abstract
A kind of two-way IGBT device and its manufacturing method, belong to power semiconductor device technology field.The present invention passes through the dielectric layer between the bottom of gate electrode in the positive backside trench of device and the equipotential double Split Electrodes of lateral leadin and metal electrode and double Split Electrodes and gate electrode, in the case where not influencing IGBT device threshold voltage and opening, realize symmetrical forward and reverse characteristic, the forward and reverse switching speed of two-way IGBT device is improved, the switching loss of device is reduced；The carrier concentration profile for improving entire N-type drift region improves the compromise of forward conduction voltage drop and switching loss；The saturation current density for reducing device improves the short-circuit safety operation area of device, improves the concentration of channel bottom electric field, improve the breakdown voltage of device, further improves the reliability of device；Two-way IGBT production methods proposed by the invention need not increase additional processing step, compatible with the two-way production method of IGBT of tradition.
Description
Technical field
The invention belongs to power semiconductor device technology fields, are related to insulated gate bipolar transistor (IGBT), specifically relate to
And two-way trench gate insulated gate bipolar transistor (Bi-directional trench IGBT).
Background technology
Insulated gate bipolar transistor (IGBT) is a kind of MOS field-effects and the compound novel electric power electricity of bipolar transistor
Sub- device.Its existing MOSFET is easy to drive, and controls simple advantage, and has power transistor turns pressure drop low, on state current
Greatly, small advantage is lost, it has also become one of core electron component in modern power electronic circuit is widely used in such as
The every field of the national economy such as communication, the energy, traffic, industry, medicine, household electrical appliance and aerospace.The application pair of IGBT
The promotion of power electronic system performance plays particularly important effect.
Transformation of electrical energy is one of basic function of electric device, and according to the difference of load requirement, electric device can be completed
AC-to DC (AC-DC), direct current to exchange (DC-AC), the change of DC to DC (DC-DC) and AC to AC (AC-AC)
It changes.Indirect conversion i.e. AC-DC-AC modes may be used in the transformation of AC-AC, can also be in such a way that directly transformation is AC-AC.
In traditional AC-DC-AC indirect conversion systems, the connection capacitance (voltage-type transformation) of big capacitance or the company of big inductance value are needed
It connects inductance (current mode transformation) the relatively independent transformation system of two parts is connected, this kind of system bulk is big, of high cost.In addition,
The service life of capacitance and inductance is far below power device, this has seriously affected the reliability of system and service life.AC-AC is straight
It connects converting system and avoids the use connected in traditional AC-DC-AC systems inductively or capacitively, but it is two-way to require power switch to have
Switching capability.Only has the function of one-way conduction due to traditional IGBT and unidirectionally blocks have the function of bidirectional conduction two-way blocking-up
IGBT two-way switch be to be combined with the cascaded structure of fast recovery diode by the IGBT of two groups of reverse parallel connections and realized.It is this
Scheme needs a large amount of power chips, increases system cost.In addition, each chip chamber of internal system needs a large amount of lines, enhance
The ghost effect of internal system, influences system reliability.
In order to solve this problem, the integrated of product is realized, industry is by using bonding techniques by two identical ditches
Slot MOS structure is back-to-back, which to be bonded together, successfully realizes in one chip with bidirectional conduction and two-way blocking-up function
Two-way IGBT (Bi-directional IGBT), as shown in Figure 1.IGBT unidirectional compared to tradition, by controlling front and back grid
Voltage, the two-way IGBT can realize symmetrical forward and reverse IGBT conductings and turn-off characteristic.Although the structure realizes two-way switch
Function, but the structure is a kind of non-punch two-way IGBT structure.For non-punch through IGBT structure, in order to avoid device hinders
Punch-through breakdown when disconnected, it has to use thicker drift region length, this has seriously affected the performance of device.In order to solve this
Problem, industry further provide two-way IGBT structure as shown in Figure 2, and the structure is between p-type base area 7 and the drift regions N- 10
And one layer higher than 10 doping concentration of the drift region N- of 8 He of N-type layer is symmetrically used between p-type base area 27 and the drift regions N- 10
28, when either direction works, the two-way IGBT is the IGBT structure for storing layer and electric field trapping layer with carrier, significantly
Improve the performance of device.For structure shown in Fig. 2, when IGBT forward or backwards works, due to storing as carrier
The presence of the higher-doped concentration and certain thickness N-type layer 8 or 28 of layer keeps IGBT device dense close to the carrier of emitter terminal
Degree distribution is greatly improved, and improves the conductance modulation of N-type drift region, improves the carrier of entire N-type drift region
Concentration distribution makes IGBT obtain the compromise of low forward conduction voltage drop and improved forward conduction voltage drop and turn-off power loss.But
It is, for the two-way IGBT structure, when IGBT forward or backwards works since the higher-doped for storing layer as carrier is dense
The breakdown voltage of the presence of degree and certain thickness N-type layer 8 or 28, device significantly reduces, in order to effectively shield as carrier
The adverse effect for storing the N-type layer of layer obtains certain device pressure resistance, needs to use：1) deep trench gate depth, makes trench gate
Depth be more than N-type layer 8 or 28 junction depth, but when either direction work depth trench gate depth not only increase grid-hair
Emitter capacitance also increases grid-collector capacitance, thus, the switching speed of device is reduced, the switch damage of device is increased
Consumption, affects the conduction voltage drop of device and the compromise characteristic of switching loss；2) small cellular width, makes the spacing between trench gate
Reduce as far as possible, however, highdensity trench MOS structure not only increases the grid capacitance of device when either direction works,
The switching speed for reducing device increases the switching loss of device, affects the conduction voltage drop of device and the folding of switching loss
Middle characteristic makes the short-circuit trouble free service of device moreover, highdensity trench MOS structure increases the saturation current density of device
Area is deteriorated.In addition, for two-way IGBT structure as illustrated in fig. 1 and 2, gate oxide is by thermal oxide shape in the trench
At the thickness in order to ensure the entire gate oxide of certain threshold voltage is smaller, due to the thickness of mos capacitance size and oxide layer
Degree is inversely proportional, and small gate oxide thickness greatly increases the grid capacitance of device in the two-way IGBT structure of tradition.In addition, small
Gate oxide thickness so that the electric field of channel bottom is concentrated, keep the reliability of device poor.
Invention content
The present invention is for above-mentioned technical problem existing for existing two-way IGBT device, in order in certain device trench depth
In the case of trench MOS structure density, when two-way IGBT device either direction works, reduce the grid capacitance of device, it is special
It is not grid-collector capacitance, improves the switching speed of device, reduces switching loss, while the saturation current for reducing device is close
Degree improves the short-circuit safety operation area of device and improves the breakdown voltage of device, and further increases the current-carrying of device emitter terminal
Sub- enhancement effect improves the carrier concentration profile of entire N-type drift region, further improves forward conduction voltage drop and switching loss
Compromise, on the basis of traditional two-way IGBT device structure (as illustrated in fig. 1 and 2), a kind of two-way IGBT devices of present invention offer
Part (as shown in Figure 3) and preparation method thereof.To simplify the description, only illustrate by taking the two-way IGBT device of n-channel as an example below, but
The present disclosure applies equally to the two-way IGBT devices of p-channel.
The technical scheme is that：A kind of two-way IGBT device, structure cell including two as shown in figure 3, symmetrically set
It is placed in the N-channel MOS structure of 10 tow sides of N-type drift region；The front MOS structure includes front metal electrode 1, front Jie
Matter layer 2, front N+ emitter region 5, front P+ emitter region 6, positive p-type base area 71, positive N-type layer 8 and front trench gate structure；Institute
It includes back metal electrode 21, back side first medium layer 22, back side N+ emitter region 25, back side P+ emitter region to state back side MOS structure
26, back side p-type base area 271, back side N-type layer 28 and backside trench grid structure；It is characterized in that, front trench gate structure edge
Device vertical direction runs through positive N-type layer 8；The front p-type base area 71 is located at the positive N-type layer of front trench gate structure side
8 upper surfaces, positive N+ emitter region 5 and front P+ emitter region 6 are located at 71 upper surface of positive p-type base area side by side, wherein front N+ is sent out
Area 5 is penetrated to connect with front trench gate structure；The upper surface of positive N+ emitter region 5 and front P+ emitter region 6 and front metal electrode 1
Connection；The front trench gate structure include positive bottom Split Electrode 31, positive gate electrode 32, face side Split Electrode 33,
Front gate dielectric layer 41, positive second dielectric layer 42, positive third dielectric layer 43, positive 4th dielectric layer 44, front the 5th are situated between
Matter layer 45；It is connected by positive third dielectric layer 43 between the positive gate electrode 32 and positive side Split Electrode 33；It is described
Positive gate electrode 32 is connect by front gate dielectric layer 41 with front N+ emitter region 5 and positive p-type base area 71；The front MOS
Also there is positive floating p-type base area 72, the front floating p-type base area 72 to be located at the front trench gate structure other side in structure
8 upper surface of positive N-type layer；Face side Split Electrode 33 is connect by positive second dielectric layer 42 with positive floating p-type base area 72；
Front bottom Split Electrode 31 is located at the lower section of positive gate electrode 32 and face side Split Electrode 33, and positive bottom division
The upper surface depth of electrode 31 is less than the junction depth of positive N-type layer 8, and the lower surface depth of positive bottom Split Electrode 31 is more than front
The junction depth of N-type layer 8；The upper surface of the front bottom Split Electrode 31 and positive gate electrode 32, face side Split Electrode 33
It is connected by positive 4th dielectric layer 44 between lower surface；The lower surface and side of front bottom Split Electrode 31 and N-type
It is connected by positive 5th dielectric layer 45 between drift region 10 and positive N-type layer 8；The front floating p-type base area 72, front the
Second medium layer 42, face side Split Electrode 33, positive third dielectric layer 43, positive gate electrode 32 and front gate dielectric layer 41 it is upper
Surface is connect with front first medium layer 2；Front bottom Split Electrode 31, face side Split Electrode 33 and front metal electricity
1 equipotential of pole；The backside trench grid structure includes back bottom Split Electrode 231, back side gate electrode 232, back side division
Electrode 233, back side gate dielectric layer 241, back side second dielectric layer 242, back side third dielectric layer 243, the 4th dielectric layer of the back side
244, the 5th dielectric layer 245 of the back side；Also there is back side floating p-type base area 272 in the back side MOS structure；The back side MOS knots
The mirror symmetry above and below the transversal centerline of device N-type drift region 10 is arranged structure with positive MOS structure.
Further, as shown in figure 4, the width of the front bottom Split Electrode 31 be more than positive second dielectric layer 42,
The sum of the width of face side Split Electrode 33, positive third dielectric layer 43, positive gate electrode 32 and front gate dielectric layer 41, makes just
Face trench gate structure is in inverted " t " font；The back side MOS structure has with positive MOS structure above and below 10 center line of N-type drift region
The connection and setting of mirror symmetry.
Further, as shown in figure 5, the both sides of the front trench gate structure also have front N+ layers 9, the front N+
The side of layer 9 is connect with positive N-type layer 8, and the other side and bottom of positive N+ layers 9 are connect with front trench gate structure, front ditch
The upper surface of the positive N+ layers 9 of slot grid structure side is connect with the lower surface of positive floating p-type base area 72, front trench gate structure
The upper surface of the N+ layers 9 of the other side is connect with the lower surface of positive p-type base area 71；The both sides of the backside trench grid structure also have
There are a back side N+ layers 29, the back side MOS structure has with positive MOS structure the mirror symmetry above and below 10 center line of N-type drift region
Connection and setting.
Further, the N+ layers 9 of the front trench gate structure are only in the side of positive p-type base area 71；The back side ditch
The N+ layers 29 of the slot grid structure only overleaf side of p-type base area 271.
Further, as shown in fig. 6, the bottom of the face side Split Electrode 33 extends to and positive bottom Split Electrode
31 upper surface connection；The back side MOS structure have with positive MOS structure above and below 10 center line of N-type drift region mirror symmetry
Connection and setting.
Further, as shown in fig. 7, the N-type layer 8 exists only in the lower part of p-type base area 71, and the floating p-type
The junction depth of base area 72 is deeper than the depth of the 5th dielectric layer 45, and extends laterally to the lower part of the 5th dielectric layer 45；The back side MOS
Structure has the connection and setting with positive MOS structure mirror symmetry above and below 10 center line of N-type drift region.
Further, as shown in figure 8, the back side MOS structure has with positive MOS structure along 10 center of N-type drift region
The connection and setting of rotational symmetry.
Further, the thickness of the positive third dielectric layer 43, the 4th dielectric layer 44 and the 5th dielectric layer 45 is more than
The thickness of gate dielectric layer 41 and second dielectric layer 42；The back side third dielectric layer 243, the 4th dielectric layer 244 and the 5th are situated between
The thickness of matter layer 245 is more than the thickness of gate dielectric layer 241 and second dielectric layer 242.
A kind of manufacturing method of two-way IGBT device, which is characterized in that include the following steps：
The first step：It chooses two panels parameter N-type identical with specification and N-type drift region of the monocrystalline silicon piece as device is lightly doped
10, the silicon wafer thickness of selection is 300~600um, doping concentration 1013~1014A/cm3；Using same process respectively in two panels
Silicon chip surface is by pre-oxidation, photoetching, etching, ion implanting and high-temperature annealing process, in the terminal of front side of silicon wafer making devices
Structure；
Second step：One layer of field oxygen is grown in two panels silicon chip surface respectively using same process, makes active area, regrowth by lithography
First passing through the N-type layer 8/28 of ion implanting N-type impurity making devices after one layer of pre- oxygen, the energy of ion implanting is 200~
500keV, implantation dosage 1013~1014A/cm2；Then pass through ion implanting p type impurity and the p-type base for making devices of annealing
Area 71/271 and floating p-type base area 72/272, the p-type base area 71/271 and floating p-type base area 72/272 are located at groove
8/28 upper surface of N-type charge storage layer of both sides；The energy of ion implanting is 60~120keV, implantation dosage 1013~1014
A/cm2, annealing temperature are 1100-1150 DEG C, and annealing time is 10~30 minutes；
Third walks：One layer of TEOS is deposited in two panels silicon chip surface using same process respectively, thickness is 700~1000nm,
After making window by lithography, groove silicon etching is carried out, etches groove, the depth of groove is more than the junction depth of N-type layer 8/28；Etching groove
After the completion, by HF solution by the TEOS rinsed cleans on surface；
4th step：Using same process respectively in the groove of two panels silicon chip week under 1050 DEG C~1150 DEG C, the atmosphere of O2
It encloses to form oxide layer；Then accumulation fills polysilicon in the trench at 750 DEG C~950 DEG C；
5th step：Using same process, formed respectively in the photoetching of two panels silicon chip surface and in groove in the 4th step of etching
Oxide layer and polysilicon make the upper surface of oxide layer and polysilicon be slightly below the junction depth of p-type base area 71/271；In channel bottom shape
At the 5th dielectric layer 45/245 and the bottom Split Electrode 31/231 in the 5th dielectric layer 45/245；
6th step：Using same process, in two panels silicon chip surface, by thermal oxide, wall grows thin oxidation in the trench again
The oxidated layer thickness of layer, formation is less than 120nm；In trenched side-wall gate dielectric layer 41/ is formed close to 71/271 side of p-type base area
241, in trenched side-wall second dielectric layer 42/242 is formed close to 72/272 side of floating p-type base area；
7th step：Using same process, accumulation filling is more in the groove of two panels silicon chip surface at 750 DEG C~950 DEG C
Crystal silicon, the lower surface depth of the polysilicon of formation are more than the junction depth in the areas PXing Ti 71/271；
8th step：It is more to be etched in two panels silicon chip surface photoetching using same process for the part filled in groove in 7th step
Crystal silicon forms gate electrode 32/232 and side Split Electrode 33/233；The gate electrode 32/232 is located at close to p-type base area 71/
271 side, side Split Electrode 33/233 are located at the side close to floating p-type base area 72/272；
9th step：Using same process, deposited in two panels silicon chip surface, the gate electrode 32/232 formed in the 8th step and side
Filled media forms third dielectric layer 43/243 in groove between face Split Electrode 33/233；
Tenth step：The N of ion implanting N-type impurity making devices is passed through in two panels silicon chip surface photoetching using same process
The energy of+emitter region 5/25, ion implanting is 30~60keV, implantation dosage 1015~1016A/cm2；The N+ emitter region
5/25 is located at 71/271 upper surface of p-type base area and is connect with trench gate；
11st step：Ion implanting p type impurity and the system of annealing are passed through in two panels silicon chip surface photoetching using same process
Make the P+ emitter region 6/26 of device, the energy of ion implanting is 60~80keV, implantation dosage 1015~1016A/cm2, annealing
Temperature is 900 DEG C, and the time is 20~30 minutes；The P+ emitter region 6/26 is located at p-type base area 71/ side by side with N+ emitter region 5/25
271 upper surfaces；
12nd step：Using same process, in two panels silicon chip surface dielectric layer deposited, and photoetching, etching form first and are situated between
Matter layer 2/22；The first medium layer 2/22 is located at floating p-type base area 72/272, second dielectric layer 42/242, side division electricity
Pole 33/233, third dielectric layer 43/243, gate electrode 32/232 and gate dielectric layer 41/241 upper surface；
13rd step：Using same process, metal is deposited in two panels silicon chip surface, and photoetching, etching are in N+ emitter region 5/
25 and P+ emitter region, 6/26 upper surface forms metal electrode 1/21；
14th step：Two panels silicon chip is overturn, silicon wafer thickness is thinned using same process, it is then identical by this two pieces
The two is bonded together to form two-way IGBT device by the silicon chip back side after being thinned to the back side using bonding technology.
Further, in the second step, it can be respectively formed 71/271 He of p-type base area at twice by increasing lithography step
Floating p-type base area 72/272.
It further, can be by the control of etch process parameters, to be formed in trench etch process in the third step
The lower trench groove structure wider than top.
Further, in the second step in the forming process of N-type layer 8/28, by increasing a step photoetching and ion implanting
Technique formed high-dopant concentration N+ layers 9/29 or in the 6th step it is miscellaneous by the ion implanting N-type with angle before oxidation technology
Matter forms the N+ layers 9/29 of high-dopant concentration；The upper surface of the N+ layers 9/29 and p-type base area 71/271 and floating p-type base area
72/272 lower surface connection.
Beneficial effects of the present invention are to realize symmetrical forward and reverse characteristic, and it is forward and reverse to improve two-way IGBT device
Switching speed, reduce the switching loss of device；The carrier concentration profile for improving entire N-type drift region, improves forward direction
The compromise of conduction voltage drop and switching loss；The saturation current density for reducing device improves the short-circuit safety operation area of device,
Improve reliability；The breakdown voltage for improving device improves the concentration of channel bottom electric field, further improves device
Reliability；Two-way IGBT production methods proposed by the invention need not increase additional processing step, with the two-way IGBT of tradition
Production method compatibility.
Description of the drawings
Fig. 1 is traditional groove-shaped two-way IGBT device structure cell schematic diagram 1；
Fig. 2 is traditional groove-shaped two-way IGBT device structure cell schematic diagram 2；
In Fig. 1-2,1/21 is front/back metal electrode, and 2/22 is front/back dielectric layer, and 3/23 is front/back
Gate electrode, 4/24 is front/back gate dielectric layer, and 5/25 is front/back N+ emitter region, and 6/26 is front/back P+ transmittings
Area, 7/27 is front/back p-type base area, and 8/28 is front/back N-type layer, and 10 be the drift regions N-；
Fig. 3 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 1；
Fig. 4 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 2；
Fig. 5 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 3；
Fig. 6 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 4；
Fig. 7 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 5；
Fig. 8 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 6；
In Fig. 3 to Fig. 8,1/21 is front/back metal electrode, and 2/22 is front/back dielectric layer, and 31/231 is just
Face/back bottom Split Electrode, 32/232 be front/back gate electrode, 33/233 be front/back side Split Electrode, 41/
241 be front/back gate dielectric layer, 42/242 be front/back dielectric layer, 43/243 be front/back dielectric layer, 44/244
For front/back dielectric layer, 45/245 is front/back dielectric layer, and 5/25 is front/back N+ emitter region, 6/26 for front/
Back side P+ emitter region, 71/271 is front/back p-type base area, and 72/272 is front/back floating p-type base area, and 8/28 is just
Face/back side N-type layer, 9/29 is N+ layers of front/back, and 10 be the drift regions N-；
Fig. 9 is that etching forms the device architecture schematic diagram after groove in the manufacturing method of the present invention；
Figure 10 is the device architecture signal after thick oxide layer and polysilicon in the manufacturing method of the present invention in etching groove
Figure；
Figure 11 is the device architecture formed in the trench in the manufacturing method of the present invention after gate electrode and side Split Electrode
Schematic diagram；
Figure 12 is the device architecture schematic diagram after surface forms metal electrode in the manufacturing method of the present invention；
Figure 13 is finally formed device structural schematic diagram after wafer bonding in the manufacturing method of the present invention.
Specific implementation mode
Below in conjunction with the accompanying drawings, detailed description of the present invention technical solution：
Embodiment 1
A kind of two-way IGBT device, structure cell is as shown in figure 3, to be symmetrically disposed on N-type drift region 10 including two positive and negative
The N-channel MOS structure on two sides；The front MOS structure includes front metal electrode 1, front dielectric layer 2, front N+ emitter region
5, front P+ emitter region 6, positive p-type base area 71, positive N-type layer 8 and front trench gate structure；The back side MOS structure includes
Back metal electrode 21, back side first medium layer 22, back side N+ emitter region 25, back side P+ emitter region 26, back side p-type base area 271,
Back side N-type layer 28 and backside trench grid structure；It is characterized in that, the front trench gate structure runs through just along device vertical direction
Face N-type layer 8；The front p-type base area 71 is located at 8 upper surface of positive N-type layer of front trench gate structure side, positive N+ transmittings
Area 5 and front P+ emitter region 6 are located at 71 upper surface of positive p-type base area side by side, wherein front N+ emitter region 5 and positive trench gate knot
Structure connects；The upper surface of positive N+ emitter region 5 and front P+ emitter region 6 is connect with front metal electrode 1；The front trench gate
Structure includes positive bottom Split Electrode 31, positive gate electrode 32, face side Split Electrode 33, front gate dielectric layer 41, front
Second dielectric layer 42, positive third dielectric layer 43, positive 4th dielectric layer 44, positive 5th dielectric layer 45；The front grid electricity
It is connected by positive third dielectric layer 43 between pole 32 and positive side Split Electrode 33；The positive gate electrode 32 passes through front
Gate dielectric layer 41 is connect with front N+ emitter region 5 and positive p-type base area 71；Also there is positive floating P in the front MOS structure
Type base area 72, the front floating p-type base area 72 are located at 8 upper surface of positive N-type layer of the front trench gate structure other side；Front
Side Split Electrode 33 is connect by positive second dielectric layer 42 with positive floating p-type base area 72；Front bottom Split Electrode
31 are located at the lower section of positive gate electrode 32 and face side Split Electrode 33, and the upper surface depth of positive bottom Split Electrode 31 is small
In the junction depth of positive N-type layer 8, the lower surface depth of positive bottom Split Electrode 31 is more than the junction depth of positive N-type layer 8；It is described just
The upper surface of face bottom Split Electrode 31 and positive gate electrode 32, face side Split Electrode 33 lower surface between pass through front the
Four dielectric layers 44 connect；Lower surface and side and the N-type drift region 10 and positive N-type layer 8 of front bottom Split Electrode 31
Between pass through positive 5th dielectric layer 45 connection；The front floating p-type base area 72, positive second dielectric layer 42, face side point
Split upper surface and the front first medium of electrode 33, positive third dielectric layer 43, positive gate electrode 32 and front gate dielectric layer 41
Layer 2 connects；Front bottom Split Electrode 31, face side Split Electrode 33 and 1 equipotential of front metal electrode.The institute of formation
The depth for stating front trench gate electrode 32 is more than 0.1~0.2 micron of the junction depth of p-type base area 71, the thickness of the N-type layer 8 of formation
Degree is 1~2 micron；The junction depth 0.5~1.5 that the depth of 31 upper surface of bottom Split Electrode formed is less than N-type layer 8 is micro-
Rice, the depth of lower surface are more than 0.5~1 micron of the junction depth of N-type layer 8；The thickness of the dielectric layer 41 and 42 formed is less than 120
Nanometer, the width of the dielectric layer 43 of formation are 0.5~1 micron, the thickness of the dielectric layer 44 and 45 of formation is 0.2~
0.5 micron.The backside trench grid structure includes back bottom Split Electrode 231, back side gate electrode 232, back side division electricity
Pole 233, back side gate dielectric layer 241, back side second dielectric layer 242, back side third dielectric layer 243, the 4th dielectric layer 244 of the back side,
The 5th dielectric layer 245 of the back side；Also there is back side floating p-type base area 272 in the back side MOS structure；The back side MOS structure with
Positive MOS structure mirror symmetry above and below the transversal centerline of device N-type drift region 10 is arranged.
Above-mentioned two-way IGBT device by controlling the grids of two symmetrical N-channel MOSs, i.e. positive gate electrode 32 and the back of the body respectively
Face gate electrode 232 is operable with the full symmetric two-way IGBT patterns of characteristic.Therefore, for convenience of description, below mainly with
Electric current illustrates that the operation principle of other direction is complete to the direction that front metal electrode 1 flows by back metal electrode 21 in Fig. 3
It is exactly the same, it is only necessary to which that corresponding content in explanation is interchangeable.Make the ditch of back side MOS structure by controlling back side gate electrode 232
Road ends, and such back side MOS structure work is similar to the collector of the unidirectional IGBT device of tradition；And positive MOS structure work class
It is similar to the emitter of traditional unidirectional IGBT device, being switched on and off for IGBT can be realized by controlling positive gate electrode 32.
In the present embodiment：Pass through the bottom of positive gate electrode 32 in device trenches and lateral leadin and front metal electrode
Thick dielectric layer between the equipotential double Split Electrodes 31 and 33 of 1 (emitter) and double Split Electrodes and gate electrode, in not shadow
In the case of ringing IGBT device threshold voltage and opening:1) depth for reducing gate electrode in groove, substantially reduces including grid
Grid capacitance including pole-collector capacitance, gate-emitter capacitance；2) it by the shielding action of double Split Electrodes, shields
Grid-collector capacitance is converted to gate-emitter capacitance, substantially reduces grid-current collection by the coupling of grid and collector
Electrode capacitance, while being made from the increased gate-emitter of grid-collector capacitance conversion by the effect of thick dielectric layer 43 and 44
Capacitance be far smaller than due to side Split Electrode 33 introduce and reduce gate-emitter capacitance, to substantially reduce including
Grid capacitance including grid-collector capacitance, gate-emitter capacitance.Therefore, structure of the invention substantially reduces device
Grid capacitance, especially grid-collector capacitance, improve the switching speed of device, reduce the switching loss of device.In addition,
The density of MOS raceway grooves is reduced in the introducing of certain trench MOS structure density downside Split Electrode 33, and by making side
72 floating of p-type base area at Split Electrode 33 further reduces the extraction area in hole, improves the carrier of emitter terminal
Enhancement effect further improves the carrier concentration profile of entire N-type drift region, further improves forward conduction voltage drop and opens
Close the compromise of loss；The MOS gully densities reduced at the Split Electrode of side, reduce the saturation current density of device, improve
The short-circuit safety operation area of device, improves reliability；Further, since side Split Electrode 33 and bottom Split Electrode 31 with
Emitter equipotential passes through dielectric layer and side Split Electrode 33 and bottom Split Electrode 31 in device opens dynamic process
The semiconductor surface of contact will not form transoid (floating p-type base area 72) and electron accumulation (N-type layer 8 and N-type drift region 10), because
This will not form negative differential capacity effect, avoid electric current, voltage oscillation and the EMI problems opened in dynamic process, improve
Reliability；Meanwhile it is close in certain device trench depth and trench MOS structure by the thick dielectric layer around the Split Electrode of bottom
The breakdown voltage that device is further improved in the case of degree improves the concentration of channel bottom electric field, further improves device
The reliability of part.Meanwhile the width of gate electrode 32 can make the present invention with small grid more than the thickness of the 5th dielectric layer 45
In the case of resistance and high reliability, bottom Split Electrode 31 is set to make the electron screening that gate electrode 32 has had in channel bottom
With.Composite Double provided by the invention divides groove structure, and the depth of trench gate electrode 32 is more than the depth and ditch of p-type base area 71
The depth of slot gate electrode 32 be less than N-type layer 8 depth, this aspect in the case where not influencing IGBT device and opening as far as possible
Grid capacitance is reduced, especially grid-collector capacitance, on the other hand the presence compensation of certain thickness high concentration N-type layer 8
Since the introducing with the equipotential bottom Split Electrode of emitter 31 is so that near bottom Split Electrode under carrier concentration
Drop, avoids device property caused by making the forward conduction voltage drop of device increased dramatically due to the introducing of bottom Split Electrode 31
It is deteriorated.
In addition, the present invention may also be operated in bi-directional MOS pattern：Make back side MOS structure by controlling back side gate electrode 232
Raceway groove is opened, and such back side MOS structure work is similar to the drain electrode of the unidirectional MOS device of tradition；And front MOS structure work is similar
In the source electrode of traditional unidirectional MOS device, being switched on and off for MOS is realized by controlling positive gate electrode 32.It is two-way when working in
When MOS patterns, operation principle and advantageous effect when the present invention also has similar to two-way IGBT operating modes.
Embodiment 2
A kind of two-way IGBT device of this example, structure cell as shown in figure 4, on the basis of embodiment 1 front
The width of bottom Split Electrode 31 is more than positive second dielectric layer 42, face side Split Electrode 33, positive third dielectric layer 43, just
The sum of the width of face gate electrode 32 and front gate dielectric layer 41, make front composite trench grid structure be in inverted " t " font, i.e., it is described just
The width of the understructure of face composite trench structure is more than the width of superstructure and extends into N-type layer 8；The back side
MOS structure has the connection and setting with positive MOS structure mirror symmetry above and below 10 center line of N-type drift region.Extend into N-type
The width of composite trench structure bottom structure in layer 8/28 is about 72/272 width of p-type base area 71/271 and floating p-type base area
1/4-3/4.The understructure extended into N-type layer 8/28 further reduces the extraction area of minority carrier,
The carrier injection enhancement effect for further improving emitter terminal, can get better device forward conduction voltage drop and switch damages
The compromise of consumption, while adverse effect of the N-type layer to device electric breakdown strength is further shielded, obtain higher device breakdown electricity
Pressure and reliability.In addition, the understructure extended into N-type layer 8/28 further shields the coupling of grid and collector
It closes, reduces grid-collector capacitance, can further improve the switching speed of device, reduce the switching loss of device.
Embodiment 3
A kind of two-way IGBT device of this example, structure cell as shown in figure 5, on the basis of embodiment 2 it is described just/
Subregion between the understructure of back side composite trench structure and p-type base area 71/271 and floating p-type base area 72/272 is also
With one layer of N+ layer 9/29, the concentration of the N+ layers 9/29 is more than the concentration of N-type layer 8/28 and its side wall and composite trench knot
Structure is connected；The side of the N+ layers 9/29 is connect with positive N-type layer 8/28, the other side and bottom and the trench gate knot of N+ layers 9/29
Structure connects, and the upper surface of the N+ layers 9/29 of trench gate structure side is connect with the lower surface of floating p-type base area 72/272, trench gate
The upper surface of the N+ layers 9/29 of the structure other side is connect with the lower surface of p-type base area 71/271；The N+ layers 9/29 formed
Width is less than the width for extending into the composite trench structure bottom structure in N-type layer 8/28.Formed the N+ layers 9/29 into
One step reduces the resistance in region between the composite trench structure bottom structure and p-type base area 71/271, further improves
The carrier of emitter terminal injects enhancement effect, can get the compromise of better device forward conduction voltage drop and switching loss.
Embodiment 4
A kind of two-way IGBT device of this example, structure cell is as shown in fig. 6, as different from Example 1, face side is divided
The lower part for splitting electrode 33 extends directly into the upper surface of bottom Split Electrode 31, makes side Split Electrode 33 and bottom Split Electrode
31 are connected directly the grid capacitance for further decreasing device；The back side MOS structure, which has, drifts about with positive MOS structure along N-type
The connection and setting of mirror symmetry above and below 10 center line of area.
Embodiment 5
A kind of two-way IGBT device of this example, structure cell as shown in fig. 7, unlike embodiment 1-4, it is described just
Face N-type layer 8 exists only in the lower part of p-type base area 71, and the junction depth of the p-type base area 72 is deeper than the depth of the 5th dielectric layer 45
Degree, and the lower part for extending laterally to the 5th dielectric layer 45 further improves the concentration of channel bottom electric field, improves the breakdown of device
Voltage and reliability；The back side MOS structure have with positive MOS structure above and below 10 center line of N-type drift region mirror symmetry
Connection and setting.
Embodiment 6
A kind of two-way IGBT device of this example, structure cell is as shown in figure 8, unlike embodiment 1-5, the back of the body
Face MOS structure has with positive MOS structure along the connection and setting of 10 center rotational symmetry of N-type drift region.
The specific embodiment of present invention process production method is carried out by taking the two-way IGBT device of 1200V voltage class as an example
It illustrates, concrete technology production method is as follows：
The first step：It chooses two panels parameter N-type identical with specification and N-type drift region of the monocrystalline silicon piece as device is lightly doped
10, the silicon wafer thickness of selection is 300~600um, and doping concentration is 7 × 1013A/cm3；Using same process respectively in two panels silicon
Piece surface is by pre-oxidation, photoetching, etching, ion implanting and high-temperature annealing process, in the terminal knot of front side of silicon wafer making devices
Structure；
Second step：Same process is used to grow a layer thickness in two panels silicon chip surface for 0.3~0.5 micron of field respectively
Oxygen makes active area by lithography, the N-type of ion implanting N-type impurity making devices is first passed through after one layer~0.05 micron pre- oxygen of regrowth
The energy of layer 8/28, ion implanting is 500keV, and implantation dosage is 5 × 1013A/cm2；Then pass through ion implanting p type impurity
And p-type base area 71/271 and the floating p-type base area 72/272 for making devices of annealing, the p-type base area 71/271 and floating p-type base
Area 72/272 is located at 8/28 upper surface of N-type charge storage layer of groove both sides；The energy of ion implanting is 120keV, injection
Dosage is 1 × 1014A/cm2, annealing temperature is 1100-1150 DEG C, and annealing time is 10~30 minutes；The junction depth of N-type layer 8/28
It is 1~2 micron deeper than the junction depth of p-type base area 71/271；
Third walks：One layer of TEOS is deposited in two panels silicon chip surface using same process respectively, thickness 800nm makes by lithography
After window, groove (trench) silicon etching is carried out, etches groove, the depth of groove is more than the junction depth 0.5~1 of N-type layer 8/28
Micron；After the completion of etching groove, by HF solution by the TEOS rinsed cleans on surface；
4th step：At 1050 DEG C~1150 DEG C, O2Atmosphere under using same process respectively around two panels silicon chip groove
Form the oxide layer that thickness is 0.2~0.5 micron；Then accumulation fills polysilicon in the trench at 750 DEG C~950 DEG C；
5th step：Using same process, formed respectively in the photoetching of two panels silicon chip surface and in groove in the 4th step of etching
Oxide layer and polysilicon make the upper surface of oxide layer and polysilicon be less than 0.2~0.3 micron of the upper surface of N-type layer 8/28；
6th step：Using same process, in two panels silicon chip surface, by thermal oxide, wall grows thin oxidation in the trench again
The oxidated layer thickness of layer, formation is less than 120nm；
7th step：Using same process, accumulation filling is more in the groove of two panels silicon chip surface at 750 DEG C~950 DEG C
Crystal silicon, the lower surface depth of the polysilicon of formation are more than 0.1~0.2 micron of the junction depth of p-type base area 71/271；
8th step：It is more to be etched in two panels silicon chip surface photoetching using same process for the part filled in groove in 7th step
Crystal silicon forms gate electrode 32/232 and side Split Electrode 33/233；
9th step：Using same process, deposited in two panels silicon chip surface, the gate electrode 32/232 formed in the 8th step and side
Filled media forms third dielectric layer 43/243 in groove between face Split Electrode 33/233；
Tenth step：The N of ion implanting N-type impurity making devices is passed through in two panels silicon chip surface photoetching using same process
The energy of+emitter region 5/25, ion implanting is 40keV, and implantation dosage is 1 × 1015A/cm2；
11st step：Ion implanting p type impurity and the system of annealing are passed through in two panels silicon chip surface photoetching using same process
Make the P+ emitter region 6/26 of device, the energy of ion implanting is 60keV, and implantation dosage is 5 × 1015A/cm2, annealing temperature is
900 DEG C, the time is 30 minutes；
12nd step：Using same process, in two panels silicon chip surface dielectric layer deposited, and photoetching, etching form first and are situated between
Matter layer 2/22；
13rd step：Using same process, metal is deposited in two panels silicon chip surface, and photoetching, etching form metal electrode
1/21；
14th step：Two panels silicon chip is overturn, the thickness of silicon wafer thickness to 60~70 microns is thinned using same process, then
By this two pieces it is identical be thinned after silicon chip back side to the back side, the two is bonded together to form into two-way IGBT devices using bonding technology
Part.
It is prepared into two-way IGBT device.
It further, can be by the control of etch process parameters, to be formed in trench etch process in the third step
The lower trench groove structure wider than top, that is, form device architecture as shown in Figure 4.
Further, in the second step in the forming process of N-type layer 8/28, by increasing a step photoetching and ion implanting
Technique formed high-dopant concentration N+ layers 9/29 or in the 6th step it is miscellaneous by the ion implanting N-type with angle before oxidation technology
Matter forms the N+ layers 9/29 of high-dopant concentration；The upper surface of the N+ layers 9/29 and p-type base area 71/271 and floating p-type base area
72/272 lower surface connection, that is, form device architecture as shown in Figure 5.
Further, a step etching technics, etching removal side Split Electrode 33/ can be increased before the 7th step polycrystalline silicon deposit
Oxide layer under 233 forms device architecture as shown in FIG. 6.
Further, in the second step, N-type layer only can be formed under p-type base area 71/271 by increasing lithography step
8, and be respectively formed p-type base area 71/271 and floating p-type base area 72/272 at twice by increasing lithography step, that is, it is formed as schemed
Device architecture shown in 7.
Further, the material of the dielectric layer 41/241,42/242,43/243,44/244 and 45/245 can be identical
It can also be different.
Fig. 3-Fig. 8 only gives several specific implementations based on core ideas of the present invention, those skilled in the art's root
According to general knowledge known in this field it should be known that in two-way IGBT device provided by the invention, semi-conducting material used in device can be used
Silicon (Si), silicon carbide (SiC), GaAs (GaAs) or gallium nitride (GaN) etc. are achieved, and dielectric material used can be used
Silica (SiO2), hafnium oxide (HfO2) or silicon nitride (Si3N4) etc. are achieved, and manufacturing technology steps also can basis
Actual needs is adjusted.
Claims (7)
1. a kind of two-way IGBT device, including two N-channel MOS structures for being symmetrically disposed on N-type drift region (10) tow sides；
The front MOS structure includes front metal electrode (1), front dielectric layer (2), front N+ emitter region (5), front P+ emitter region
(6), positive p-type base area (71), positive N-type layer (8) and front trench gate structure；The back side MOS structure includes back metal
Electrode (21), back side dielectric layer (22), back side N+ emitter region (25), back side P+ emitter region (26), back side p-type base area (271), the back of the body
Face N-type layer (28) and backside trench grid structure；It is characterized in that, the front trench gate structure runs through just along device vertical direction
Face N-type layer (8)；The front p-type base area (71) is located at positive N-type layer (8) upper surface of front trench gate structure side, front
N+ emitter region (5) and front P+ emitter region (6) are located at positive p-type base area (71) upper surface side by side, wherein front N+ emitter region (5)
It is connect with front trench gate structure；The upper surface of positive N+ emitter region (5) and front P+ emitter region (6) and front metal electrode
(1) it connects；The front trench gate structure includes positive bottom Split Electrode (31), positive gate electrode (32), face side division
Electrode (33), front gate dielectric layer (41), positive second dielectric layer (42), positive third dielectric layer (43), positive 4th medium
Layer (44), positive 5th dielectric layer (45)；By just between the positive gate electrode (32) and positive side Split Electrode (33)
Face third dielectric layer (43) connects；The positive gate electrode (32) passes through front gate dielectric layer (41) and front N+ emitter region (5)
It is connected with positive p-type base area (71)；Also there is positive floating p-type base area (72), the front floating in the front MOS structure
P-type base area (72) is located at positive N-type layer (8) upper surface of the front trench gate structure other side；Face side Split Electrode (33) is logical
Positive second dielectric layer (42) is crossed to connect with positive floating p-type base area (72)；The front bottom Split Electrode (31) is located at just
The lower section of face gate electrode (32) and face side Split Electrode (33), and the upper surface depth of positive bottom Split Electrode (31) is less than
The junction depth of positive N-type layer (8), the lower surface depth of positive bottom Split Electrode (31) are more than the junction depth of positive N-type layer (8)；Institute
State positive bottom Split Electrode (31) upper surface and positive gate electrode (32), face side Split Electrode (33) lower surface between
It is connected by positive 4th dielectric layer (44)；The lower surface and side of the front bottom Split Electrode (31) and N-type drift region
(10) it is connected by positive 5th dielectric layer (45) between positive N-type layer (8)；The front floating p-type base area (72), front
Second dielectric layer (42), face side Split Electrode (33), positive third dielectric layer (43), positive gate electrode (32) and front grid are situated between
The upper surface of matter layer (41) is connect with front first medium layer (2)；The front bottom Split Electrode (31), face side division electricity
Pole (33) and front metal electrode (1) equipotential；The backside trench grid structure includes back bottom Split Electrode (231), the back of the body
Face gate electrode (232), back side Split Electrode (233), back side gate dielectric layer (241), back side second dielectric layer (242), the back side
Third dielectric layer (243), the 4th dielectric layer (244) of the back side, the 5th dielectric layer (245) of the back side；Also have in the back side MOS structure
There is back side floating p-type base area (272)；The back side MOS structure is with positive MOS structure along the transverse direction of device N-type drift region (10)
Center line setting symmetrical above and below.
2. a kind of two-way IGBT device according to claim 1, which is characterized in that the front bottom Split Electrode (31)
Width be more than positive second dielectric layer (42), face side Split Electrode (33), positive third dielectric layer (43), positive gate electrode
(32) and the sum of the width of front gate dielectric layer (41) it is in inverted " t " font, to make front trench gate structure；The back side MOS structure
With positive MOS structure along the transversal centerline setting symmetrical above and below of N-type drift region (10).
3. a kind of two-way IGBT device according to claim 2, which is characterized in that the both sides of the front trench gate structure
Also there are front N+ layers (9), the side of front N+ layers (9) is connect with positive N-type layer (8), the other side and bottom of N+ layers (9)
Portion is connect with front trench gate structure, upper surface and the floating p-type base area (72) of the N+ layers (9) of front trench gate structure side
Lower surface connects, and the upper surface of the N+ layers (9) of the front trench gate structure other side is connect with the lower surface of p-type base area (71)；Institute
The both sides for stating backside trench grid structure also have back side N+ layers (29), and the back side MOS structure is with positive MOS structure along device N
The transversal centerline setting symmetrical above and below of type drift region (10).
4. a kind of two-way IGBT device according to claim 1,2 and 3 any one, which is characterized in that the front is floating
Empty p-type base area (72) extends downward into the junction depth that its junction depth is deeper than positive 5th dielectric layer (45), front along device vertical direction
The part covering that floating p-type base area (72) extends downwardly is located at the positive N-type layer (8) below positive floating p-type base area (72), just
Face floating p-type base area (72) is more than that the parts transversely of positive 5th dielectric layer (45) junction depth extends to positive five dielectric layers (45)
Lower part, the back side floating p-type base area (272) in the back side MOS structure and the positive floating p-type base in positive MOS structure
Transversal centerline up and down mirror symmetry setting of the area (72) along device N-type drift region (10).
5. a kind of two-way IGBT device according to claim 4, which is characterized in that the face side Split Electrode (33)
Bottom is extended to be connect with the upper surface of positive bottom Split Electrode (31)；The back side MOS structure is with positive MOS structure along device
The transversal centerline setting symmetrical above and below of part N-type drift region (10).
6. a kind of manufacturing method of two-way IGBT device, which is characterized in that include the following steps：
The first step：It chooses two panels parameter N-type identical with specification and N-type drift region of the monocrystalline silicon piece as device is lightly doped, choose
Silicon wafer thickness be 300~600um, doping concentration 1013~1014A/cm3；Using same process respectively in two panels silicon chip table
Face is by pre-oxidation, photoetching, etching, ion implanting and high-temperature annealing process, in the terminal structure of front side of silicon wafer making devices；
Second step：One layer of field oxygen is grown in two panels silicon chip surface respectively using same process, makes active area, one layer of regrowth by lithography
The N-type layer of ion implanting N-type impurity making devices is first passed through after pre- oxygen, the energy of ion implanting is 200~500keV, injectant
Amount is 1013~1014A/cm2；Then pass through the p-type base area and floating p-type base of ion implanting p type impurity and making devices of annealing
Area, the p-type base area and floating p-type base area are located at the N-type charge storage layer upper surface of groove both sides；The energy of ion implanting
Amount is 60~120keV, implantation dosage 1013~1014A/cm2, annealing temperature be 1100-1150 DEG C, annealing time be 10~
30 minutes；
Third walks：One layer of TEOS is deposited in two panels silicon chip surface using same process respectively, thickness is 700~1000nm, photoetching
After going out window, groove silicon etching is carried out, etches groove, the depth of groove is more than the junction depth of N-type layer；After the completion of etching groove,
By HF solution by the TEOS rinsed cleans on surface；
4th step：At 1050 DEG C~1150 DEG C, O2Atmosphere under using the same process shape around the groove of two panels silicon chip respectively
At thick oxide layer；Then accumulation fills polysilicon in the trench at 750 DEG C~950 DEG C；
5th step：Using same process, the oxidation formed in groove in the 4th step is etched in the photoetching of two panels silicon chip surface and respectively
Layer and polysilicon make the upper surface of oxide layer and polysilicon be less than the junction depth of p-type base area；The 5th dielectric layer is formed in channel bottom
With the bottom Split Electrode in the 5th dielectric layer；
6th step：Using same process, in two panels silicon chip surface, by thermal oxide, wall grows thin oxide layer, shape in the trench again
At oxidated layer thickness be less than 120nm；Gate dielectric layer is formed close to p-type base area side in trenched side-wall, it is close in trenched side-wall
Floating p-type base area side forms second dielectric layer；
7th step：Using same process, accumulation fills polysilicon in the groove of two panels silicon chip surface at 750 DEG C~950 DEG C,
The lower surface depth of the polysilicon of formation is more than the junction depth in the areas PXing Ti；
8th step：The part polycrystalline filled in groove in 7th step is etched in two panels silicon chip surface photoetching using same process
Silicon forms gate electrode and side Split Electrode；The gate electrode is located at close to the side of p-type base area, and side Split Electrode is located at
Side close to floating p-type base area；
9th step：It using same process, is deposited in two panels silicon chip surface, the gate electrode and side Split Electrode formed in the 8th step
Between in groove filled media form third dielectric layer；
Tenth step：It is sent out by the N+ of ion implanting N-type impurity making devices in two panels silicon chip surface photoetching using same process
Area is penetrated, the energy of ion implanting is 30~60keV, implantation dosage 1015~1016A/cm2；The N+ emitter region is located at p-type base
Area upper surface is simultaneously connect with trench gate；
11st step：Ion implanting p type impurity and maker of annealing are passed through in two panels silicon chip surface photoetching using same process
The energy of the P+ emitter region of part, ion implanting is 60~80keV, implantation dosage 1015~1016A/cm2, annealing temperature 900
DEG C, the time is 20~30 minutes；The P+ emitter region is located at p-type base area upper surface side by side with N+ emitter region；
12nd step：Using same process, in two panels silicon chip surface dielectric layer deposited, and photoetching, etching form first medium layer；
The first medium is located at floating p-type base area, second dielectric layer, side Split Electrode, third dielectric layer, gate electrode and gate medium
The upper surface of layer；
13rd step：Using same process, metal is deposited in two panels silicon chip surface, and photoetching, etching are sent out in N+ emitter region and P+
The upper surfaces She Qu form metal electrode；
14th step：Two panels silicon chip is overturn, silicon wafer thickness is thinned using same process, it is then identical thinned by this two pieces
The two is bonded together to form two-way IGBT device by silicon chip back side afterwards to the back side, using bonding technology.
7. a kind of manufacturing method of two-way IGBT device according to claim 6, which is characterized in that in the third step,
It can be by the control by etch process parameters in trench etch process, to form the lower trench groove knot wider than top
Structure.
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| CN107768435A (en) * | 2017-10-20 | 2018-03-06 | 电子科技大学 | A kind of two-way IGBT and its manufacture method |
| CN107731901B (en) * | 2017-11-20 | 2024-02-23 | 电子科技大学 | Reverse resistance type IGBT |
| CN108122962B (en) * | 2017-12-04 | 2020-07-31 | 西南交通大学 | Insulated gate bipolar transistor |
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| CN114388613B (en) * | 2021-12-30 | 2023-09-01 | 电子科技大学 | Bidirectional blocking power MOS device and manufacturing method thereof |
| CN116153991B (en) * | 2023-04-21 | 2023-06-23 | 上海陆芯电子科技有限公司 | Dual-trench-gate RC-IGBT and preparation method thereof |
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