CN105868507A - Multipath signal multichannel output device and output method thereof - Google Patents
Multipath signal multichannel output device and output method thereof Download PDFInfo
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- CN105868507A CN105868507A CN201610270232.8A CN201610270232A CN105868507A CN 105868507 A CN105868507 A CN 105868507A CN 201610270232 A CN201610270232 A CN 201610270232A CN 105868507 A CN105868507 A CN 105868507A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The invention belongs to the field of signal input and output and particularly relates to a multipath signal multichannel output device and an output method thereof. The device comprises a microprocessor unit and an FPGA (field programmable gate array) logic unit, wherein the microprocessor unit is used for receiving and analyzing channel configuration instructions and storing analyzed data in an inner cache region; an output end of the microprocessor unit is connected with an input end of the FPGA logic unit; the FPGA logic unit is used for receiving the analyzed data from the microprocessor unit, an input end of the FPGA logic unit is connected with all input signals, and an output end of the FPGA logic unit is connected with output channels. Therefore, a corresponding input signal of each output channel can be flexibly changed by changing the channel configuration instructions; the number of output channels and the number of input signals are changed by changing the number of output channel modules; the multipath signal multichannel output device has the advantages of simple structure, low cost, stability, reliability and convenience in popularization and use.
Description
Technical field
The invention belongs to signal input and output field, particularly to a kind of multiple signals multi-channel output device
And output intent.
Background technology
Multiple signals input/output unit is widely used in various I/O channel test neck at present
In territory, signal input/output unit is when testing, and the kind of the input signal that output channel is corresponding needs
The most changeable, just can make the comparatively perfect that test result becomes.
Multiple signals multi-channel output device of the prior art mostly uses hardware circuit to build or FPGA
Logical block, the way of input signal and the way of output channel all can not be changed flexibly, and output channel
Corresponding input signal kind can not change neatly, and complex circuit designs, relatively costly.
Therefore a kind of way that can change input signal of proposition and the way of output channel, and output are needed badly
The multiple signals multi-channel output device that the input signal kind that passage is corresponding can change neatly.
Summary of the invention
The present invention is in order to overcome above-mentioned the deficiencies in the prior art, it is provided that a kind of multiple signals multichannel output
Device, this device is possible not only to change input signal and the way of output channel, it is also possible to change neatly
The input signal kind that output channel is corresponding, and possess simple in construction, feature with low cost.
For achieving the above object, present invention employs techniques below measure:
A kind of multiple signals multi-channel output device, this device includes microprocessor unit and fpga logic
Unit, wherein,
Microprocessor unit is used for receiving and parsing through the passage configuration-direct from passage dispensing unit, and will
Data after parsing are stored in the buffer area of inside, and the outfan of described microprocessor unit connects FPGA
The input of logical block；
FPGA logic cell is for receiving from the data after the parsing of microprocessor unit, described FPGA
The input of logical block connects all of input signal, and it is logical that the outfan of FPGA logic cell connects output
Road；
Described microprocessor unit, the input end of clock of FPGA logic cell are all connected with clock signal.
Preferably, described FPGA logic cell includes data reception module and signal selection module, described
The input of data reception module connects the outfan of microprocessor unit, and the data of data reception module are defeated
Going out end and connect the data input pin of signal selection module, the input end of clock of described data reception module connects
Clock signal；The input of described signal selection module connects all of input signal, signal selection module
Outfan connect output channel.
Preferably, described signal selection module includes independent of one another and identical output channel module, each
The input of described output channel module is all connected with all of input signal, the number of each output channel module
Be all connected with the data output end of data reception module according to input, the outfan of each output channel module is equal
Connect a road output channel.
Further, the figure place of described passage configuration-direct is come certainly by the way of input signal Yu output channel
Fixed.
Further, the input of described data reception module connects the defeated of microprocessor unit by bus
Go out end.
Further, described microprocessor unit, FPGA logic cell are integrated in same double-core chip,
The model of described double-core chip is the SmartFusion2 chip that Microsemi company of the U.S. produces.
The present invention provides the output intent of above-mentioned a kind of multiple signals multi-channel output device the most simultaneously.
The output intent of a kind of multiple signals multi-channel output device, comprises the following steps:
S1, described microprocessor unit receive the passage configuration-direct post analysis from passage dispensing unit
Passage configuration-direct, it is corresponding that microprocessor unit parses each road output channel according to passage configuration-direct
Input signal, and will resolve after data be stored in inside buffer area in；
Data after S2, described microprocessor unit will resolve again are passed by bus by its internal buffer area
Deliver to data reception module；
S3, data transmission after the data output end of described data reception module will resolve are logical to each output
The data input pin of road module, the input of each described output channel module is all connected with all of input letter
Number, the outfan of each described output channel module is all connected with a road output channel；
Corresponding input signal can be sent into defeated according to the data after resolving by S4, described output channel module
Go out in passage.
Preferably, the number by changing output channel module changes the road of output channel and input signal
Number.
Preferably, change input corresponding to each road output channel by change passage configuration-direct to believe
Number.
The beneficial effects of the present invention is:
1), the present invention microprocessor unit and FPGA logic cell are combined use, utilize micro-process
Device unit receives and parses through the passage configuration-direct from passage dispensing unit, and the data after resolving
Transmit the data input pin to each output channel module, change flexibly by changing passage configuration-direct
Become the input signal that each road output channel is corresponding；Change defeated by the number changing output channel module
Go out the way of passage and input signal, and the present invention be also equipped with simple in construction, with low cost, stably may be used
Lean on, be easy to the advantage promoted the use of.
2), described microprocessor unit, FPGA logic cell be integrated in same double-core chip, described
The model of double-core chip is the SmartFusion2 chip that Microsemi company of the U.S. produces, and improves
The operational efficiency of the present invention and processing speed, enhance program portability, it is simple to secondary development.
Accompanying drawing explanation
Fig. 1 is the structural representation of the present invention；
Fig. 2 is the RTL schematic diagram of the present invention；
Fig. 3 is the RTL view of the signal selection module of the present invention.
In figure, the implication of label symbol is as follows:
10 microprocessor unit 20 FPGA logic cell
21 data reception module 22 signal selection module
30 passage dispensing units
221～228 first output channel module～the 8th output channel modules
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the present invention, and
It is not all, of embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art are not doing
Go out the every other embodiment obtained under creative work premise, broadly fall into the scope of protection of the invention.
As it is shown in figure 1, a kind of multiple signals multi-channel output device receives from passage dispensing unit 30
Passage configuration-direct, by change passage configuration-direct, it is achieved that this device outfan connect each
Road output channel is corresponding with input signal flexibly.
As in figure 2 it is shown, this device includes microprocessor unit 10 and FPGA logic cell 20, described micro-
Processor unit 10 is used for receiving and parsing through the passage configuration-direct from passage dispensing unit 30, and will
Data after parsing are stored in the buffer area of inside, and the outfan of described microprocessor unit 10 connects
The input of FPGA logic cell 20；Described FPGA logic cell 20 is for receiving from microprocessor
Data after the parsing of unit 10, the input of described FPGA logic cell 20 connects all of input
Signal, the outfan of FPGA logic cell 20 connects output channel；Described microprocessor unit 10, FPGA
The input end of clock of logical block 20 is all connected with clock signal.
Described FPGA logic cell 20 includes data reception module 21 and signal selection module 22, described
The input of data reception module 21 connects the outfan of microprocessor unit 10, data reception module 21
Data output end connect signal selection module 22 data input pin, described data reception module 21
Input end of clock connects clock signal；The input of described signal selection module 22 connects all of input
Signal, the outfan of signal selection module 22 connects output channel.
As it is shown on figure 3, described signal selection module 22 includes that 8 independent of one another and identical outputs are led to
Road module, respectively first output channel module the 221, second output channel module the 222, the 3rd output
The output of channel module the 223, the 4th output channel module the 224, the 5th output channel module the 225, the 6th is logical
Road module the 226, the 7th output channel module the 227, the 8th output channel module 228, each described output
The input of channel module is all connected with all of input signal, the data input pin of each output channel module
Being all connected with the data output end of data reception module 21, the outfan of each output channel module is all connected with
One tunnel output channel.
Described passage configuration-direct is made up of 32 bit binary data.
Described microprocessor unit 10, FPGA logic cell 20 are integrated in same double-core chip, described
The model of double-core chip is the SmartFusion2 chip that Microsemi company of the U.S. produces.
As shown in Figures 1 to 3, the output intent of a kind of multiple signals multi-channel output device, its feature exists
In comprising the following steps:
S1, described microprocessor unit 10 receive the passage configuration-direct from passage dispensing unit 30
Post analysis passage configuration-direct, if described passage configuration-direct is by 00,000,000 00,000,000 00000001
The 32 bit binary data compositions of 01000100, the 100 of the 0th to the 2nd of binary data are
1st group, expression for output channel Output0, corresponding input signal is Signal4, binary system
The 000 of the 3rd to the 5th of data is the 2nd group, expression for output channel Output1, corresponding
Input signal is Signal0 ..., the 000 of the 21st to the 23rd is the 8th group, expression for defeated
Going out passage Output7, corresponding input signal is Signal0, microprocessor unit 10 will resolve after number
According in the buffer area being stored in inside；
Data after S2, described microprocessor unit 10 will resolve again are passed through total by its internal buffer area
Line is sent to data reception module 21；
S3, described data reception module 21 data output end will resolve after data transmission defeated to each
Going out the data input pin of channel module, the input of each described output channel module is all connected with all of defeated
Enter signal, be Input0～Input5；The outfan of each described output channel module is all connected with a road
Output channel, the outfan such as the first output channel module 221 connects Output0；First output channel
The outfan of module 221 connects Output0；The outfan of the second output channel module 222 connects
Output1；
Corresponding input signal can be sent into defeated according to the data after resolving by S4, described output channel module
Go out in passage.As the input of the first output channel module 221 connects all of input signal it is
Input0～Input5, exports according to described first output channel module 221 corresponding in the data after resolving
The binary data of passage is 100, corresponding input signal Input4 i.e. Signal4 delivers to output logical
In road Output0；Logical according to described second output channel module 222 output corresponding in the data after resolving
The binary data in road is 000, and corresponding input signal Input0 i.e. Signal0 is delivered to output channel
In Output1.
Accordingly, for remaining output channel module, according to each output channel in the data after resolving
The binary data of module is 000, is sent into by the i.e. Signal0 of corresponding input signal Input0 corresponding
Output channel Outputi, non-Output2 and Output0 of described Outputi.
The input signal that each road output channel is corresponding is changed flexibly by changing passage configuration-direct；
The way of output channel and input signal is changed by the number changing output channel module.And this
Bright be also equipped with simple in construction, with low cost, reliable and stable, be easy to the advantage promoted the use of, quilt of the present invention
It is widely used in various I/O channel field tests.
Claims (9)
1. a multiple signals multi-channel output device, it is characterised in that: this device includes microprocessor
Unit (10) and FPGA logic cell (20), wherein,
Microprocessor unit (10) is used for receiving and parsing through the passage from passage dispensing unit (30) and joins
Put instruction, and the data after resolving are stored in the buffer area of inside, described microprocessor unit (10)
Outfan connect FPGA logic cell (20) input；
FPGA logic cell (20) is used for receiving from the data after the parsing of microprocessor unit (10),
The input of described FPGA logic cell (20) connects all of input signal, FPGA logic cell (20)
Outfan connect output channel；
When described microprocessor unit (10), the input end of clock of FPGA logic cell (20) are all connected with
Clock signal.
2. a kind of multiple signals multi-channel output device as claimed in claim 1, it is characterised in that:
Described FPGA logic cell (20) includes data reception module (21) and signal selection module (22),
The input of described data reception module (21) connects the outfan of microprocessor unit (10), data
The data output end of receiver module (21) connects the data input pin of signal selection module (22), described
The input end of clock of data reception module (21) connects clock signal；Described signal selection module (22)
Input connect all of input signal, the outfan of signal selection module (22) connects output channel.
3. a kind of multiple signals multi-channel output device as claimed in claim 2, it is characterised in that:
Described signal selection module (22) includes independent of one another and identical output channel module, each described defeated
The input going out channel module is all connected with all of input signal, the data input of each output channel module
End is all connected with the data output end of data reception module (21), and the outfan of each output channel module is equal
Connect a road output channel.
4. a kind of multiple signals multi-channel output device as claimed in claim 3, it is characterised in that:
The figure place of described passage configuration-direct is determined by the way of input signal with output channel.
5. a kind of multiple signals multi-channel output device as claimed in claim 3, it is characterised in that:
The input of described data reception module (21) connects the output of microprocessor unit (10) by bus
End.
6. a kind of multiple signals multi-channel output device as described in any one of claims 1 to 3, it is special
Levy and be: described microprocessor unit (10), FPGA logic cell (20) are integrated in same double-core core
In sheet, the model of described double-core chip is the SmartFusion2 core that Microsemi company of the U.S. produces
Sheet.
7. an output intent for a kind of multiple signals multi-channel output device as claimed in claim 5,
It is characterized in that comprising the following steps:
The passage that S1, described microprocessor unit (10) receive from passage dispensing unit (30) is joined
Putting instruction post analysis passage configuration-direct, microprocessor unit (10) parses according to passage configuration-direct
The input signal that each road output channel is corresponding, and will resolve after data be stored in inside buffer area in；
Data after S2, described microprocessor unit (10) will resolve again are passed through by its internal buffer area
Bus is sent to data reception module (21)；
S3, described data reception module (21) data output end will resolve after data transmit to each
The data input pin of output channel module, the input of each described output channel module is all connected with all of
Input signal, the outfan of each described output channel module is all connected with a road output channel；
Corresponding input signal can be sent into defeated according to the data after resolving by S4, described output channel module
Go out in passage.
The output intent of a kind of multiple signals multi-channel output device the most as claimed in claim 7, its
It is characterized by changing the number of output channel module to change the road of output channel and input signal
Number.
The output intent of a kind of multiple signals multi-channel output device the most as claimed in claim 7, its
It is characterized by changing passage configuration-direct to change the input signal that each road output channel is corresponding.
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| CN201610270232.8A CN105868507A (en) | 2016-04-26 | 2016-04-26 | Multipath signal multichannel output device and output method thereof |
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| CN201610270232.8A CN105868507A (en) | 2016-04-26 | 2016-04-26 | Multipath signal multichannel output device and output method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112836463A (en) * | 2020-12-31 | 2021-05-25 | 北京百瑞互联技术有限公司 | Device, method, storage medium and equipment for integrated circuit IO port multiplexing |
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| CN112836463A (en) * | 2020-12-31 | 2021-05-25 | 北京百瑞互联技术有限公司 | Device, method, storage medium and equipment for integrated circuit IO port multiplexing |
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