CN105867880B - It is a kind of towards the branch target buffer and design method that jump branch prediction indirectly - Google Patents
It is a kind of towards the branch target buffer and design method that jump branch prediction indirectly Download PDFInfo
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30061—Multi-way branch instructions, e.g. CASE
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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Abstract
The present invention proposes a kind of towards the branch target buffer and design method that jump branch prediction indirectly, this method is included in branch target buffer, for the branch instruction jumped indirectly, if jumping destination address derives from the value for being prestored to register or memory, the index that second level hardware list Indirect_BTB is directed toward in addition in destination address is jumped in branch target buffer respective items；After the completion of a branch instruction executes, two-stage branch target buffer padding is executed if being to jump the branch instruction jumped indirectly of the destination address dependent on the value of register or memory if the branch instruction, otherwise executes the padding of Conventional branch target buffer；Obtain the branch instruction needed to be implemented, two-stage branch target buffer branch prediction operations are executed if being to jump the branch instruction jumped indirectly of the destination address dependent on the value of register or memory if the branch instruction, otherwise execute Conventional branch target buffer predicted operation.
Description
Technical field
It is the present invention relates to processor design field, in particular to a kind of slow towards the branch target for jumping branch prediction indirectly
Rush device and design method.
Background technique
The execution of computer program be presented as processor to instruction fetch, analysis instruction, execute instruction and to modify memory several
A step repeats, and in the classification of processor instruction, has a kind of instruction that can change instruction flow direction to be known as branch and refers to
It enables, branch instruction has vital influence for the execution efficiency of instruction stream on a processor, and non-branch instruction is come
It says, instruction execution is sequence, i.e., next instruction to be executed is just stored in an instruction after present instruction；It is right
For branch instruction, due to the change that may cause entirely to instruct flow direction, after only current branch instruction executes completion,
It just can determine that the storage address of next instruction to be executed.
Branch instruction, which is divided into, directly to be jumped and jumps two kinds indirectly, and the branch instruction directly jumped jumps direction and defines, can
Destination address is jumped directly to calculate according to command content；The branch instruction jumped indirectly then needs to be implemented a series of operations,
Condition judgement is carried out according to operation result, determines the next step flow direction of instruction, that is, needs to select in multiple destination addresses correct
Jump destination address.
In order to improve processor execution performance, modern processor design all uses branch prediction techniques, and this technology exists
Before branch instruction executes completion, predicted this address that will be jumped, to refer to branch according to the historical record that it is jumped
For order, branch prediction techniques can effectively reduce branch instruction to the obstruction of assembly line, improve processor pipeline feasibility
Energy.
It the use of BTB (Branch Target Buffer, branch target buffer) is to assist commonly using for branch instruction predictions
Method, common BTB structure are as shown in Figure 1.The historical record that several branch instructions jump is stored in BTB table, each history note
Record includes two parts, i.e. label (TAG) S101 and branch instruction jumps destination address historical record (referred to as jumping destination address)
S102 indexes BTB table by the low level of present instruction PC (Program Counter), finds continuous item in branch prediction
Afterwards, whether the high position for comparing present instruction PC is equal with TAG, indicates that present instruction is branch instruction and BTB table if equal
In have the historical record for jumping destination address, then use this to jump the historical record of destination address as the conjecture mesh of present instruction
Address；It indicates not record present instruction in BTB table if unequal, which may be to hold the first time of branch instruction
Row, is not yet recorded in BTB, needs that branch instruction conditions is waited to calculate and completes, determines after actually jumping destination address, this is referred to
The relative recording of order is filled up in BTB.
In conventional BTB design, retain the destination address that branch instruction finally uses only to assist current branch instruction
Destination address prediction is jumped, however, register can usually be relied on by jumping destination address in the branch instruction jumped indirectly
Value in value even memory, this feelings for jumping destination address and being derived partly from the value being prestored in register or memory
Condition often leads to jump every time between destination address there is no apparent dependence, if still using the jump of routine BTB at this time
Turn historical branch prediction technique, precision of prediction just will be greatly reduced, so as to cause the reduction of processor pipeline execution efficiency, directly
Influence processor performance.
The intuitive idea of one to solve the above problems is simply to store the multiple of branch instruction in BTB to jump destination
Location, this will lead to same branch instruction PC may correspond to it is multiple jump destination address, faced when also implying that branch prediction more
A destination address that jumps is available, how to select suitably to jump destination address as predicted address as a problem, and
The problem does not have very good solution method still at present.
In conclusion current BTB branch prediction method when executing the branch prediction jumped indirectly there are limitation, for
The case where jumping the value that destination address is derived partly from register or memory of branch instruction, BTB can not accurately execute branch
Prediction.
Summary of the invention
In view of the deficiencies of the prior art, the present invention proposes a kind of towards the branch target buffer for jumping branch prediction indirectly
And design method.
The present invention proposes a kind of towards the branch target buffer design method for jumping branch prediction indirectly, comprising: branch
Target buffer improves step, second level hardware list Indirect_BTB is constructed, for recording the more of the branch instruction jumped indirectly
It is a to jump destination address, in branch target buffer, for the branch instruction jumped indirectly, if jumping destination address source
In the value for being prestored to register or memory, then addition in destination address is jumped in branch target buffer respective items and be directed toward two
The index of grade hardware list Indirect_BTB；
Branch target buffer updates step, after the completion of a branch instruction executes, if the branch instruction is to jump
Destination address then executes two-stage branch target buffer dependent on the branch instruction of the value of register or memory jumped indirectly and fills out
Operation is filled, the padding of Conventional branch target buffer is otherwise executed；
Branch target buffer prediction steps obtain the branch instruction needed to be implemented, if the branch instruction is to jump
The branch instruction jumped indirectly for turning destination address dependent on the value of register or memory then executes two-stage branch target buffer
Otherwise branch prediction operations execute Conventional branch target buffer predicted operation.
Second level hardware list Indirect_BTB includes multiple items, each include three parts: label, jump destination address and
The saturated counters of destination address frequency of occurrence are jumped described in record.
If it includes according to institute that the branch target buffer, which updates Conventional branch target buffer padding in step,
The PC index for stating branch instruction has found respective items in branch target buffer, then update the branch instruction jumps purpose
Address；
If the respective items in branch target buffer are not found according to the PC index of the branch instruction, in branch's mesh
The respective items are redistributed in mark buffer, and that fills corresponding label and the branch instruction jumps destination address；
If two-stage branch target buffer padding includes having found branch according to the PC index of the branch instruction
Respective items in target buffer are then looked for according to the index in destination address domain that jumps of the respective items in branch target buffer
To second level hardware list Indirect_BTB, the register for jumping destination address dependence or memory further according to the branch instruction
Value searches second level hardware list Indirect_BTB, will if having found respective items in second level hardware list Indirect_BTB
The branch instruction is practical to be jumped destination address and is filled into the jumping in destination address domain of second level hardware list Indirect_BTB,
The saturated counters of the respective items found in second level hardware list Indirect_BTB add 1, if in second level hardware list Indirect_
Respective items are not found in BTB, then sequentially add new item in second level hardware list Indirect_BTB, by the jump of the branch instruction
The value of the register or memory that turn destination address and its dependence is filled in respectively in the corresponding domain of new item, respective items saturated counters
It is set as 1；
If the respective items in branch target buffer are not found according to the PC index of the branch instruction, in branch's mesh
Respective items are redistributed in mark buffer, fill corresponding label, and fill direction in destination address domain in jumping for respective items
The index of second level hardware list Indirect_BTB sequentially adds new item in second level hardware list Indirect_BTB, will be described point
The register for jumping destination address and its dependence of Zhi Zhiling or the value of memory are filled in respectively in the corresponding domain of new item, respective items
Saturated counters are set as 1.
If Conventional branch target buffer branch prediction operations include root in the branch target buffer prediction steps
The respective items in branch target buffer are had found according to the PC index of the branch instruction, then obtain jumping for the branch instruction
Prediction destination address of the destination address as the branch instruction；
It is normal to execute if not finding the respective items in branch target buffer according to the PC index of the branch instruction
The branch instruction is updated the item in branch target buffer after the completion of branch instruction execution.
If two-stage branch target buffer branch prediction operations include root in the branch target buffer prediction steps
The respective items in branch target buffer are had found according to the PC index of the branch instruction, then according to pair of branch target buffer
It answers the index of item jumped in destination address domain to find second level hardware list Indirect_BTB, jumps mesh further according to branch instruction
Address rely on register or memory value search second level hardware list Indirect_BTB, if in second level hardware list
Respective items are had found in Indirect_BTB, then take the branch instruction jumps destination address as the pre- of the branch instruction
It surveys destination address and normally executes the branch instruction if not finding respective items in second level hardware list Indirect_BTB, to
The branch instruction is updated the item in second level hardware list Indirect_BTB after the completion of executing；
It is normal to execute if not finding the respective items in branch target buffer according to the PC index of the branch instruction
The branch instruction updates branch target buffer and second level hardware list Indirect_ after the completion of the branch instruction executes
Item in BTB.
The present invention also proposes a kind of towards the branch target buffer for jumping branch prediction indirectly, comprising: branch target is slow
It rushes device and improves module, for constructing second level hardware list Indirect_BTB, for recording the multiple of the branch instruction jumped indirectly
Destination address is jumped, in branch target buffer, for the branch instruction jumped indirectly, is derived from if jumping destination address
It is prestored to the value of register or memory, then jumps addition in destination address in branch target buffer respective items and is directed toward second level
The index of hardware list Indirect_BTB；
Branch target buffer update module, after the completion of working as a branch instruction execution, if the branch instruction is
It jumps destination address and then executes two-stage branch target buffering dependent on the branch instruction of the value of register or memory jumped indirectly
Otherwise device padding executes the padding of Conventional branch target buffer；
Branch target buffer prediction module, for obtaining the branch instruction needed to be implemented, if the branch instruction
It is to jump destination address dependent on the branch instruction of the value of register or memory jumped indirectly then to execute two-stage branch target slow
Device branch prediction operations are rushed, Conventional branch target buffer predicted operation is otherwise executed.
Second level hardware list Indirect_BTB includes multiple items, each include three parts: label, jump destination address and
The saturated counters of destination address frequency of occurrence are jumped described in record.
If Conventional branch target buffer padding includes according to institute in the branch target buffer update module
The PC index for stating branch instruction has found respective items in branch target buffer, then update the branch instruction jumps purpose
Address；
If the respective items in branch target buffer are not found according to the PC index of the branch instruction, in branch's mesh
The respective items are redistributed in mark buffer, and that fills corresponding label and the branch instruction jumps destination address；
If two-stage branch target buffer padding includes having found branch according to the PC index of the branch instruction
Respective items in target buffer are then looked for according to the index in destination address domain that jumps of the respective items in branch target buffer
To second level hardware list Indirect_BTB, the register for jumping destination address dependence or memory further according to the branch instruction
Value searches second level hardware list Indirect_BTB, will if having found respective items in second level hardware list Indirect_BTB
The branch instruction is practical to be jumped destination address and is filled into the jumping in destination address domain of second level hardware list Indirect_BTB,
The saturated counters of the respective items found in second level hardware list Indirect_BTB add 1, if in second level hardware list Indirect_
Respective items are not found in BTB, then sequentially add new item in second level hardware list Indirect_BTB, by the jump of the branch instruction
The value of the register or memory that turn destination address and its dependence is filled in respectively in the corresponding domain of new item, respective items saturated counters
It is set as 1；
If the respective items in branch target buffer are not found according to the PC index of the branch instruction, in branch's mesh
Respective items are redistributed in mark buffer, fill corresponding label, and fill direction in destination address domain in jumping for respective items
The index of second level hardware list Indirect_BTB sequentially adds new item in second level hardware list Indirect_BTB, will be described point
The register for jumping destination address and its dependence of Zhi Zhiling or the value of memory are filled in respectively in the corresponding domain of new item, respective items
Saturated counters are set as 1.
If Conventional branch target buffer branch prediction operations include root in the branch target buffer prediction module
The respective items in branch target buffer are had found according to the PC index of the branch instruction, then obtain jumping for the branch instruction
Prediction destination address of the destination address as the branch instruction；
It is normal to execute if not finding the respective items in branch target buffer according to the PC index of the branch instruction
The branch instruction is updated the item in branch target buffer after the completion of branch instruction execution.
If two-stage branch target buffer branch prediction operations include root in the branch target buffer prediction module
The respective items in branch target buffer are had found according to the PC index of the branch instruction, then according to pair of branch target buffer
It answers the index of item jumped in destination address domain to find second level hardware list Indirect_BTB, jumps mesh further according to branch instruction
Address rely on register or memory value search second level hardware list Indirect_BTB, if in second level hardware list
Respective items are had found in Indirect_BTB, then take the branch instruction jumps destination address as the pre- of the branch instruction
It surveys destination address and normally executes the branch instruction if not finding respective items in second level hardware list Indirect_BTB, to
The branch instruction is updated the item in second level hardware list Indirect_BTB after the completion of executing；
It is normal to execute if not finding the respective items in branch target buffer according to the PC index of the branch instruction
The branch instruction updates branch target buffer and second level hardware list Indirect_ after the completion of the branch instruction executes
Item in BTB.
As it can be seen from the above scheme the present invention has the advantages that
The present invention indexes branch instruction and jumps destination address table by increasing two-stage register and memory value, establishes two-stage mesh
Allocation index mechanism, solve the problems, such as of the existing technology, effectively increase the branch prediction accuracies jumped indirectly, improve
Processor pipeline execution performance.
Detailed description of the invention
Fig. 1 is routine BTB structural schematic diagram；
Fig. 2 is the BTB modified flow for jumping branch prediction indirectly for supporting that there is register or memory to rely in the present invention
Schematic diagram；
Fig. 3 is to increase the BTB two-stage destination address Indexing Mechanism schematic diagram after Indirect_BTB in the present invention；
Fig. 4 is that the BTB item for jumping branch prediction indirectly that there is register or memory to rely on is supported to update stream in the present invention
Journey schematic diagram；
Fig. 5 is the pre- flow gauge of BTB for jumping branch prediction indirectly for supporting that there is register or memory to rely in the present invention
Schematic diagram.
Specific embodiment
It is existing when executing the branch prediction jumped indirectly that present invention aim to address current BTB branch prediction methods
Limitation jumps the case where destination address is dependent on value in register or memory for the branch instruction that jumps indirectly,
BTB can not accurately execute the problem of branch prediction.
In order to solve the above technical problems, it is of the invention it is a kind of towards the branch target buffer for jumping branch prediction indirectly and
Design method, including supporting the BTB improved method for jumping branch prediction indirectly that there is register or memory to rely on, supporting have
There is the BTB item update method for jumping branch prediction indirectly and support that register or memory rely on register or memory to rely on
The BTB prediction technique three parts of branch prediction are jumped indirectly.
It supports the BTB improved method for jumping branch prediction indirectly that there is register or memory to rely on, passes through following technology
Scheme is realized:
1.1 in BTB structure, for the branch instruction jumped indirectly, is derived partly from advance if jumping destination address
The value of register or memory is stored, then jumps addition in destination address in BTB respective items and is directed toward second level hardware list Indirect_
The index of BTB；
1.2 construction second level hardware list Indirect_BTB, jump mesh for recording the multiple of the branch instruction jumped indirectly
Address.Indirect_BTB structure includes several items, each include three parts: TAG, branch instruction jump destination address and
Record two saturated counters for jumping destination address frequency of occurrence.Wherein, the storage of the domain TAG jumps destination with branch instruction
The value of the relevant register in location or memory；Two saturated counters records accordingly jump the frequency (the saturation meter of destination address appearance
Number device value is between 0~3, initial value 0)；
1.3 in BTB structure, for the branch instruction directly jumped, and jumps destination address independent of register
Or the branch instruction of the value of memory jumped indirectly, BTB still keep traditional structure constant.
It supports the BTB item update method for jumping branch prediction indirectly that there is register or memory to rely on, passes through following skill
Art scheme is realized:
2.1 after the completion of a branch instruction executes, if the branch instruction is the branch instruction directly jumped, or jump
The branch instruction that indirectly jumps of the destination address independent of the value of register or memory, then execute conventional BTB padding not
Become, operating method is as follows:
If 2.11 compare the respective items having found in BTB according to the PC index of the branch instruction, its jump is directly updated
Turn destination address；
If 2.12 do not find the respective items in BTB according to the PC index of the branch instruction, divide again in BTB
With this, and fill corresponding TAG and branch instruction jumps destination address.
2.2 after the completion of branch instruction executes, if the branch instruction be jump destination address dependent on register or
The branch instruction of the value of memory jumped indirectly then executes two-stage BTB padding, and operating method is as follows:
If 2.21 compare the respective items having found in BTB according to the PC index of the branch instruction, according to BTB respective items
The index jumped in destination address domain find second level hardware list Indirect_BTB；Destination address is jumped further according to branch instruction
The value of the register of dependence or memory searches second level hardware list Indirect_BTB, if had found in Indirect_BTB pair
The practical destination address that jumps of the branch instruction is then filled into the jumping in destination address domain of Indirect_BTB by Ying Xiang, corresponding
Item saturated counters add 1；If not finding respective items in Indirect_BTB, sequentially addition is new in Indirect_BTB
, the value of register or memory that branch instruction jumps destination address and its dependence is filled in respectively in the corresponding domain of new item,
Respective items saturated counters are set as 1；
If 2.22 do not find the respective items in BTB according to the PC index of the branch instruction, divide again in BTB
With this, corresponding TAG is filled, and is directed toward second level hardware list Indirect_BTB in the filling in destination address domain that jumps of this
Index.New item is sequentially added in Indirect_BTB, by branch instruction jump destination address and its dependence register or
The value of memory is filled in respectively in the corresponding domain of new item, and respective items saturated counters are set as 1.
It supports the BTB prediction technique for jumping branch prediction indirectly that there is register or memory to rely on, passes through following technology
Scheme is realized:
3.1 processor value components complete instruction fetch operation；
3.2 decoding units judge whether the instruction taken out is branch instruction, are to search BTB to carry out branch prediction；Otherwise
Normally execute this instruction；
When 3.3 lookup BTB carry out branch prediction, if the branch instruction is the branch instruction directly jumped, or mesh is jumped
Address independent of register or memory value the branch instruction jumped indirectly, then execute conventional BTB branch prediction operations
Constant, operating method is as follows:
If 3.31 compare the respective items having found in BTB according to the PC index of the branch instruction, directly it is taken to jump
Prediction destination address of the destination address as the branch instruction；
If 3.32 do not find the respective items in BTB according to the PC index of the branch instruction, which is not referred to
It enables destination address be predicted, normally executes the branch instruction, BTB updates are carried out after the completion of the branch instruction executes.
When 3.4 lookup BTB carry out branch prediction, if the branch instruction is to jump destination address dependent on register or memory
Value the branch instruction jumped indirectly, then execute two-stage BTB branch prediction operations, operating method is as follows:
If 3.41 compare the respective items having found in BTB according to the PC index of the branch instruction, according to BTB respective items
The index jumped in destination address domain find second level hardware list Indirect_BTB；Destination address is jumped further according to branch instruction
The value of the register of dependence or memory searches second level hardware list Indirect_BTB, if had found in Indirect_BTB pair
Ying Xiang, then the prediction destination address for taking it to jump destination address as the branch instruction；If do not looked in Indirect_BTB
To respective items, then the branch instruction destination address is not predicted, normally execute the branch instruction, executed to the branch instruction
Indirect_BTB updates are carried out after the completion；
If 3.42 do not find the respective items in BTB according to the PC index of the branch instruction, which is not referred to
Enable destination address be predicted, normally execute the branch instruction, after the branch instruction execute after the completion of update BTB and
Indirect_BTB.
The invention will be described in further detail with reference to the accompanying drawings and detailed description, as follows:
Of the invention is a kind of towards the branch target buffer design method for jumping branch prediction indirectly, and process is embodied
Including support the BTB modified flow for jumping branch prediction indirectly that there is register or memory to rely on, support with register or
The BTB item more new technological process for jumping branch prediction indirectly and support what there is register or memory to rely on to jump indirectly that memory relies on
The pre- flow gauge three parts of the BTB of branch prediction.
Support the BTB modified flow for jumping branch prediction indirectly that there is register or memory to rely on, as shown in Figure 2:
Step S201, in BTB structure, for the branch instruction jumped indirectly, if jumping destination address part source
In the value for being prestored to register or memory, then addition in destination address is jumped in BTB respective items and be directed toward second level hardware list
The index of Indirect_BTB；
Step S202 constructs second level hardware list Indirect_BTB, for recording the multiple of the branch instruction jumped indirectly
Jump destination address.Indirect_BTB structure includes several items, each includes three parts: TAG, branch instruction jump destination
Location and record two saturated counters for jumping destination address frequency of occurrence.Wherein, the domain TAG storage is jumped with branch instruction
The value of the relevant register of destination address or memory；Two saturated counters records accordingly jump the frequency of destination address appearance
(saturated counters value between 0~3, initial value 0)；
Step S203, in BTB structure, for the branch instruction directly jumped, and jump destination address independent of
The branch instruction of the value of register or memory jumped indirectly, BTB keep traditional structure constant.
Fig. 3 gives increase Indirect_BTB after BTB two-stage destination address Indexing Mechanism example.
Support the BTB item more new technological process for jumping branch prediction indirectly that there is register or memory to rely on, as shown in Figure 4:
Step S401 judges whether the branch instruction is the branch directly jumped after the completion of a branch instruction executes
Instruction, or the branch instruction that indirectly jumps of the destination address independent of the value of register or memory is jumped, it is to go to step
S402；Otherwise S403 is gone to step.
Step S402 when branch instruction is the branch instruction directly jumped, or jumps destination address independent of deposit
The branch instruction of the value of device or memory jumped indirectly, then it is constant to execute conventional BTB padding, executes that steps are as follows:
Step S402-1 compares the respective items searched in BTB according to the PC index of the branch instruction, finds respective items and then hold
Row step S402-2 does not find respective items and thens follow the steps S402-3.
Step S402-2, if the PC index according to the branch instruction compares the respective items having found in BTB, directly more
New its jumps destination address.
Step S402-3, if the respective items in BTB are not found according to the PC index of the branch instruction, in BTB
In redistribute this, and fill corresponding TAG and branch instruction jumps destination address.
Step S403, when branch instruction is point of the value for jumping destination address dependent on register or memory jumped indirectly
Zhi Zhiling then executes two-stage BTB padding, and steps are as follows for execution:
Step S403-1 compares the respective items searched in BTB according to the PC index of the branch instruction, finds respective items and then hold
Row step S403-2 does not find respective items and thens follow the steps S403-6.
Step S403-2, if the PC index according to the branch instruction compares the respective items having found in BTB, basis
The index of BTB respective items jumped in destination address domain finds second level hardware list Indirect_BTB.
The value of step S403-3, the register or memory that jump destination address dependence according to branch instruction search second level hardware
The respective items of Table I ndirect_BTB find respective items and then follow the steps S403-4, do not find respective items and then follow the steps S403-
5。
Step S403-4 jumps mesh for the branch instruction is practical if having found respective items in Indirect_BTB
Address be filled into the jumping in destination address domain of Indirect_BTB, respective items saturated counters add 1.
Step S403-5 sequentially adds in Indirect_BTB if not finding respective items in Indirect_BTB
Add new item, the value of register or memory that branch instruction jumps destination address and its dependence is filled in the corresponding domain of new item respectively
In, respective items saturated counters are set as 1.
Step S403-6, if the respective items in BTB are not found according to the PC index of the branch instruction, in BTB
In redistribute this, fill corresponding TAG, and be directed toward second level hardware list in the filling in destination address domain that jumps of this
The index of Indirect_BTB.
Step S403-7 sequentially adds new item in Indirect_BTB, by branch instruction jump destination address and its according to
The value of bad register or memory is filled in respectively in the corresponding domain of new item, and respective items saturated counters are set as 1.
Support the pre- flow gauge of BTB for jumping branch prediction indirectly that there is register or memory to rely on, as shown in Figure 5:
Step S501, processor value component complete instruction fetch operation.
Step S502, decoding unit judge whether the instruction taken out is branch instruction, is to then follow the steps S503；Otherwise just
Often execute this instruction.
Step S503 judges whether the branch instruction is the branch instruction directly jumped, or jumps destination address and disobey
Rely in the branch instruction of the value of register or memory jumped indirectly, is to go to step S504；Otherwise S505 is gone to step.
Step S504, when searching BTB progress branch prediction, if the branch instruction is the branch instruction directly jumped, or
The branch instruction that indirectly jumps of the destination address independent of the value of register or memory is jumped, then it is pre- to execute conventional BTB branch
It is constant to survey operation, steps are as follows for execution:
Step S504-1 compares the respective items searched in BTB according to the PC index of the branch instruction, finds respective items and then hold
Row step S504-2 does not find respective items and thens follow the steps S504-3.
Step S504-2 directly takes if the PC index according to the branch instruction compares the respective items having found in BTB
It jumps prediction destination address of the destination address as the branch instruction.
Step S504-3, if the respective items in BTB are not found according to the PC index of the branch instruction, not to this
Branch instruction destination address is predicted, the branch instruction is normally executed, and BTB are carried out after the completion of the branch instruction executes more
Newly.
Step S505, when searching BTB progress branch prediction, if the branch instruction is to jump destination address dependent on register
Or the branch instruction of the value of memory jumped indirectly, then two-stage BTB branch prediction operations are executed, steps are as follows for execution:
Step S505-1 compares the respective items searched in BTB according to the PC index of the branch instruction, finds respective items and then hold
Row step S505-2 does not find respective items and thens follow the steps S505-6.
Step S505-2, if the PC index according to the branch instruction compares the respective items having found in BTB, basis
The index of BTB respective items jumped in destination address domain finds second level hardware list Indirect_BTB.
The value of step S505-3, the register or memory that jump destination address dependence according to branch instruction search second level hardware
The respective items of Table I ndirect_BTB find respective items and then follow the steps S505-4, do not find respective items and then follow the steps S505-
5。
Step S505-4, if having found respective items in Indirect_BTB, taking it to jump destination address conduct should
The prediction destination address of branch instruction.
Step S505-5, if not finding respective items in Indirect_BTB, not to the branch instruction destination address
It is predicted, normally executes the branch instruction, Indirect_BTB updates are carried out after the completion of the branch instruction executes.
If not finding the respective items in BTB according to the PC index of the branch instruction, not to the branch instruction mesh
Address predicted, normally execute the branch instruction, after the branch instruction execute after the completion of update BTB and Indirect_BTB
?.
The present invention also proposes a kind of towards the branch target buffer for jumping branch prediction indirectly, comprising: branch target is slow
It rushes device and improves module, for constructing second level hardware list Indirect_BTB, for recording the multiple of the branch instruction jumped indirectly
Destination address is jumped, in branch target buffer, for the branch instruction jumped indirectly, is derived from if jumping destination address
It is prestored to the value of register or memory, then jumps addition in destination address in branch target buffer respective items and is directed toward second level
The index of hardware list Indirect_BTB；
Branch target buffer update module, after the completion of working as a branch instruction execution, if the branch instruction is
It jumps destination address and then executes two-stage branch target buffering dependent on the branch instruction of the value of register or memory jumped indirectly
Otherwise device padding executes the padding of Conventional branch target buffer；
Branch target buffer prediction module, for obtaining the branch instruction needed to be implemented, if the branch instruction
It is to jump destination address dependent on the branch instruction of the value of register or memory jumped indirectly then to execute two-stage branch target slow
Device branch prediction operations are rushed, Conventional branch target buffer predicted operation is otherwise executed.
Second level hardware list Indirect_BTB includes multiple items, each include three parts: label, jump destination address and
The saturated counters of destination address frequency of occurrence are jumped described in record.
If Conventional branch target buffer padding includes according to institute in the branch target buffer update module
The PC index for stating branch instruction has found respective items in branch target buffer, then update the branch instruction jumps purpose
Address；
If the respective items in branch target buffer are not found according to the PC index of the branch instruction, in branch's mesh
The respective items are redistributed in mark buffer, and that fills corresponding label and the branch instruction jumps destination address；
If two-stage branch target buffer padding includes having found branch according to the PC index of the branch instruction
Respective items in target buffer are then looked for according to the index in destination address domain that jumps of the respective items in branch target buffer
To second level hardware list Indirect_BTB, the register for jumping destination address dependence or memory further according to the branch instruction
Value searches second level hardware list Indirect_BTB, will if having found respective items in second level hardware list Indirect_BTB
The branch instruction is practical to be jumped destination address and is filled into the jumping in destination address domain of second level hardware list Indirect_BTB,
The saturated counters of the respective items found in second level hardware list Indirect_BTB add 1, if in second level hardware list Indirect_
Respective items are not found in BTB, then sequentially add new item in second level hardware list Indirect_BTB, by the jump of the branch instruction
The value of the register or memory that turn destination address and its dependence is filled in respectively in the corresponding domain of new item, respective items saturated counters
It is set as 1；
If the respective items in branch target buffer are not found according to the PC index of the branch instruction, in branch's mesh
Respective items are redistributed in mark buffer, fill corresponding label, and fill direction in destination address domain in jumping for respective items
The index of second level hardware list Indirect_BTB sequentially adds new item in second level hardware list Indirect_BTB, will be described point
The register for jumping destination address and its dependence of Zhi Zhiling or the value of memory are filled in respectively in the corresponding domain of new item, respective items
Saturated counters are set as 1.
If Conventional branch target buffer branch prediction operations include root in the branch target buffer prediction module
The respective items in branch target buffer are had found according to the PC index of the branch instruction, then obtain jumping for the branch instruction
Prediction destination address of the destination address as the branch instruction；
It is normal to execute if not finding the respective items in branch target buffer according to the PC index of the branch instruction
The branch instruction is updated the item in branch target buffer after the completion of branch instruction execution.
If two-stage branch target buffer branch prediction operations include root in the branch target buffer prediction module
The respective items in branch target buffer are had found according to the PC index of the branch instruction, then according to pair of branch target buffer
It answers the index of item jumped in destination address domain to find second level hardware list Indirect_BTB, jumps mesh further according to branch instruction
Address rely on register or memory value search second level hardware list Indirect_BTB, if in second level hardware list
Respective items are had found in Indirect_BTB, then take the branch instruction jumps destination address as the pre- of the branch instruction
It surveys destination address and normally executes the branch instruction if not finding respective items in second level hardware list Indirect_BTB, to
The branch instruction is updated the item in second level hardware list Indirect_BTB after the completion of executing；
It is normal to execute if not finding the respective items in branch target buffer according to the PC index of the branch instruction
The branch instruction updates branch target buffer and second level hardware list Indirect_ after the completion of the branch instruction executes
Item in BTB.
Claims (10)
1. a kind of towards the branch target buffer design method for jumping branch prediction indirectly characterized by comprising branch's mesh
It marks buffer and improves step, second level hardware list Indirect_BTB is constructed, for recording the multiple of the branch instruction jumped indirectly
Destination address is jumped, in branch target buffer, for the branch instruction jumped indirectly, is derived from if jumping destination address
It is prestored to the value of register or memory, then jumps addition in destination address in branch target buffer respective items and is directed toward second level
The index of hardware list Indirect_BTB；
Branch target buffer updates step, after the completion of a branch instruction executes, if the branch instruction is to jump purpose
The branch instruction that indirectly jumps of the address dependent on the value of register or memory then executes two-stage branch target buffer filling behaviour
Make, if the branch instruction is the branch instruction directly jumped, or jumps value of the destination address independent of register or memory
The branch instruction jumped indirectly, then execute Conventional branch target buffer padding；
Branch target buffer prediction steps obtain the branch instruction needed to be implemented, if the branch instruction is to jump mesh
Address dependent on register or memory value the branch instruction jumped indirectly, then execute two-stage branch target buffer branch
Predicted operation, if the branch instruction is the branch instruction directly jumped or the branch instruction is to jump destination address not depending on
In the branch instruction of the value of register or memory jumped indirectly, then Conventional branch target buffer predicted operation is executed.
2. as described in claim 1 towards the branch target buffer design method for jumping branch prediction indirectly, feature exists
In second level hardware list Indirect_BTB includes multiple items, each includes three parts: label jumps destination address and record
The saturated counters for jumping destination address frequency of occurrence.
3. as claimed in claim 1 or 2 towards the branch target buffer design method for jumping branch prediction indirectly, feature
It is, if it includes according to described point that the branch target buffer, which updates Conventional branch target buffer padding in step,
The PC index of Zhi Zhiling has found the respective items in branch target buffer, then update the branch instruction jumps destination
Location；
It is slow in branch target if not finding the respective items in branch target buffer according to the PC index of the branch instruction
It rushes in device and redistributes the respective items, and that fills corresponding label and the branch instruction jumps destination address；
If two-stage branch target buffer padding includes having found branch target according to the PC index of the branch instruction
Respective items in buffer then find two according to the index in destination address domain that jumps of the respective items in branch target buffer
The value of grade hardware list Indirect_BTB, the register for jumping destination address dependence or memory further according to the branch instruction are looked into
Second level hardware list Indirect_BTB is looked for, it, will be described if having found respective items in second level hardware list Indirect_BTB
Branch instruction is practical to be jumped destination address and is filled into the jumping in destination address domain of second level hardware list Indirect_BTB, in second level
The saturated counters of the respective items found in hardware list Indirect_BTB add 1, if in second level hardware list Indirect_BTB
In do not find respective items, then new item is sequentially added in second level hardware list Indirect_BTB, by jumping for the branch instruction
The value of the register or memory of destination address and its dependence is filled in respectively in the corresponding domain of new item, and respective items saturated counters are set
It is set to 1；
It is slow in branch target if not finding the respective items in branch target buffer according to the PC index of the branch instruction
It rushes and redistributes respective items in device, fill corresponding label, and be directed toward second level in the filling in destination address domain that jumps of respective items
The index of hardware list Indirect_BTB sequentially adds new item in second level hardware list Indirect_BTB, the branch is referred to
The value of the register for jumping destination address and its dependence or memory that enable is filled in respectively in the corresponding domain of new item, respective items saturation
Counter is set as 1.
4. as described in claim 1 towards the branch target buffer design method for jumping branch prediction indirectly, feature exists
In if Conventional branch target buffer branch prediction operations include according to described in the branch target buffer prediction steps
The PC index of branch instruction has found the respective items in branch target buffer, then obtain the branch instruction jumps destination
Prediction destination address of the location as the branch instruction；
If not finding the respective items in branch target buffer according to the PC index of the branch instruction, described in normal execution
Branch instruction is updated the item in branch target buffer after the completion of branch instruction execution.
5. as described in claim 1 towards the branch target buffer design method for jumping branch prediction indirectly, feature exists
In if two-stage branch target buffer branch prediction operations include according to described in the branch target buffer prediction steps
The PC index of branch instruction has found the respective items in branch target buffer, then according to the respective items of branch target buffer
It jumps the index in destination address domain and finds second level hardware list Indirect_BTB, jump destination address further according to branch instruction
The register of dependence or the value of memory search second level hardware list Indirect_BTB, if in second level hardware list Indirect_BTB
In have found respective items, then take the prediction destination address for jumping destination address as the branch instruction of the branch instruction,
If not finding respective items in second level hardware list Indirect_BTB, the branch instruction is normally executed, is referred to the branch
It enables and the item in second level hardware list Indirect_BTB being updated after the completion of executing；
If not finding the respective items in branch target buffer according to the PC index of the branch instruction, described in normal execution
Branch instruction updates in branch target buffer and second level hardware list Indirect_BTB after the completion of the branch instruction executes
Item.
6. a kind of towards the branch target buffer for jumping branch prediction indirectly characterized by comprising branch target buffer
Module is improved to jump for constructing second level hardware list Indirect_BTB for recording the multiple of the branch instruction jumped indirectly
Destination address, in branch target buffer, for the branch instruction jumped indirectly, if jumping destination address from preparatory
The value of register or memory is stored, then jumps addition in destination address in branch target buffer respective items and is directed toward second level hardware
The index of Table I ndirect_BTB；
Branch target buffer update module, after the completion of working as a branch instruction execution, if the branch instruction is to jump
Destination address then executes two-stage branch target buffer dependent on the branch instruction of the value of register or memory jumped indirectly and fills out
Fill operation, if the branch instruction be the branch instruction directly jumped or the branch instruction be jump destination address independent of
The branch instruction of the value of register or memory jumped indirectly then executes Conventional branch target buffer padding；
Branch target buffer prediction module, for obtaining the branch instruction needed to be implemented, if the branch instruction is to jump
The branch instruction jumped indirectly for turning destination address dependent on the value of register or memory then executes two-stage branch target buffer
Branch prediction operations if the branch instruction is the branch instruction directly jumped, or jump destination address independent of register
Or the branch instruction of the value of memory jumped indirectly, then execute Conventional branch target buffer predicted operation.
7. as claimed in claim 6 towards the branch target buffer for jumping branch prediction indirectly, which is characterized in that second level is hard
Part Table I ndirect_BTB includes multiple items, each include three parts: label, jump destination address and record described in jump mesh
Address frequency of occurrence saturated counters.
8. as claimed in claims 6 or 7 towards the branch target buffer for jumping branch prediction indirectly, which is characterized in that institute
If stating Conventional branch target buffer padding in branch target buffer update module includes according to the branch instruction
PC index have found the respective items in branch target buffer, then update the branch instruction jumps destination address；
It is slow in branch target if not finding the respective items in branch target buffer according to the PC index of the branch instruction
It rushes in device and redistributes the respective items, and that fills corresponding label and the branch instruction jumps destination address；
If two-stage branch target buffer padding includes having found branch target according to the PC index of the branch instruction
Respective items in buffer then find two according to the index in destination address domain that jumps of the respective items in branch target buffer
The value of grade hardware list Indirect_BTB, the register for jumping destination address dependence or memory further according to the branch instruction are looked into
Second level hardware list Indirect_BTB is looked for, it, will be described if having found respective items in second level hardware list Indirect_BTB
Branch instruction is practical to be jumped destination address and is filled into the jumping in destination address domain of second level hardware list Indirect_BTB, in second level
The saturated counters of the respective items found in hardware list Indirect_BTB add 1, if in second level hardware list Indirect_BTB
In do not find respective items, then new item is sequentially added in second level hardware list Indirect_BTB, by jumping for the branch instruction
The value of the register or memory of destination address and its dependence is filled in respectively in the corresponding domain of new item, and respective items saturated counters are set
It is set to 1；
It is slow in branch target if not finding the respective items in branch target buffer according to the PC index of the branch instruction
It rushes and redistributes respective items in device, fill corresponding label, and be directed toward second level in the filling in destination address domain that jumps of respective items
The index of hardware list Indirect_BTB sequentially adds new item in second level hardware list Indirect_BTB, the branch is referred to
The value of the register for jumping destination address and its dependence or memory that enable is filled in respectively in the corresponding domain of new item, respective items saturation
Counter is set as 1.
9. as claimed in claim 6 towards the branch target buffer for jumping branch prediction indirectly, which is characterized in that described point
If Conventional branch target buffer branch prediction operations include according to the branch instruction in branch target buffer prediction module
PC index have found the respective items in branch target buffer, then obtain the branch instruction jumps destination address as institute
State the prediction destination address of branch instruction；
If not finding the respective items in branch target buffer according to the PC index of the branch instruction, described in normal execution
Branch instruction is updated the item in branch target buffer after the completion of branch instruction execution.
10. as claimed in claim 6 towards the branch target buffer for jumping branch prediction indirectly, which is characterized in that described
If two-stage branch target buffer branch prediction operations include being referred to according to the branch in branch target buffer prediction module
The PC index of order has found the respective items in branch target buffer, then jumps mesh according to the respective items of branch target buffer
Address field in index find second level hardware list Indirect_BTB, further according to branch instruction jump destination address dependence
The value of register or memory searches second level hardware list Indirect_BTB, if found in second level hardware list Indirect_BTB
Respective items, then take the prediction destination address for jumping destination address as the branch instruction of the branch instruction, if
Respective items are not found in second level hardware list Indirect_BTB, normally execute the branch instruction, are executed to the branch instruction
The item in second level hardware list Indirect_BTB is updated after the completion；
If not finding the respective items in branch target buffer according to the PC index of the branch instruction, described in normal execution
Branch instruction updates in branch target buffer and second level hardware list Indirect_BTB after the completion of the branch instruction executes
Item.
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| US10592248B2 (en) * | 2016-08-30 | 2020-03-17 | Advanced Micro Devices, Inc. | Branch target buffer compression |
| CN111176729A (en) * | 2018-11-13 | 2020-05-19 | 深圳市中兴微电子技术有限公司 | Information processing method and device and computer readable storage medium |
| WO2020199058A1 (en) * | 2019-03-30 | 2020-10-08 | 华为技术有限公司 | Branch instruction processing method, branch predictor, and processor |
| US11182166B2 (en) * | 2019-05-23 | 2021-11-23 | Samsung Electronics Co., Ltd. | Branch prediction throughput by skipping over cachelines without branches |
| CN111061512B (en) * | 2019-12-06 | 2022-11-15 | 湖北文理学院 | Method, device and equipment for processing branch instruction and storage medium |
| CN111898130B (en) * | 2020-06-28 | 2024-01-19 | 中国科学院信息工程研究所 | Method and system for realizing integrity protection of fine-grained control flow |
| CN117093267B (en) * | 2023-10-17 | 2023-12-22 | 北京开源芯片研究院 | Storage method, device, equipment and storage medium for branch instruction jump address |
| CN118012632B (en) * | 2024-04-10 | 2024-07-05 | 山东浪潮科学研究院有限公司 | GPGPU (graphics processing Unit) branch instruction scheduling method based on multistage redistribution mechanism |
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| CN1397886A (en) * | 2001-05-04 | 2003-02-19 | 智慧第一公司 | Imaginary branch target address high speed buffer storage |
| CN103150142A (en) * | 2011-12-07 | 2013-06-12 | 苹果公司 | Next fetch predictor training with hysteresis |
| CN104423929A (en) * | 2013-08-21 | 2015-03-18 | 华为技术有限公司 | Branch prediction method and related device |
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| CN1397886A (en) * | 2001-05-04 | 2003-02-19 | 智慧第一公司 | Imaginary branch target address high speed buffer storage |
| CN103150142A (en) * | 2011-12-07 | 2013-06-12 | 苹果公司 | Next fetch predictor training with hysteresis |
| CN104423929A (en) * | 2013-08-21 | 2015-03-18 | 华为技术有限公司 | Branch prediction method and related device |
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