CN105849905A - 高迁移率晶体管 - Google Patents
高迁移率晶体管 Download PDFInfo
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- CN105849905A CN105849905A CN201480071542.6A CN201480071542A CN105849905A CN 105849905 A CN105849905 A CN 105849905A CN 201480071542 A CN201480071542 A CN 201480071542A CN 105849905 A CN105849905 A CN 105849905A
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- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 74
- 239000000872 buffer Substances 0.000 claims abstract description 65
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 61
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 31
- 239000010703 silicon Substances 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 45
- 229910052732 germanium Inorganic materials 0.000 claims description 29
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 29
- 230000004888 barrier function Effects 0.000 claims description 21
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 4
- 230000003139 buffering effect Effects 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
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- 235000007164 Oryza sativa Nutrition 0.000 claims 1
- 235000009566 rice Nutrition 0.000 claims 1
- 239000002210 silicon-based material Substances 0.000 claims 1
- 230000037230 mobility Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 4
- 229910000078 germane Inorganic materials 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910000070 arsenic hydride Inorganic materials 0.000 description 2
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- 229910052796 boron Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
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- 238000005530 etching Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
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- 239000000203 mixture Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 2
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- VUGMARFZKDASCX-UHFFFAOYSA-N 2-methyl-N-silylpropan-2-amine Chemical compound CC(C)(C)N[SiH3] VUGMARFZKDASCX-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000005859 coupling reaction Methods 0.000 description 1
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- 239000013024 dilution buffer Substances 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229960002050 hydrofluoric acid Drugs 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
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Classifications
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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Abstract
包含n沟道finFET(106)和p沟道finFET(110)的集成电路(100)具有在硅衬底(102)上方的介电层(112)。所述finFET(106、110)的所述鳍具有半导体材料,该半导体材料具有与硅相比更高的迁移率。n沟道finFET(106)的鳍是在穿过所述衬底(102)上的所述介电层(112)的第一沟槽(114)中的第一硅锗缓冲层(118)上。p沟道finFET(110)的鳍是在穿过所述衬底(102)上的介电层(112)的第二沟槽(116)中的第二硅锗缓冲层(132)上。鳍在所述介电层(112)上方延伸至少10纳米。通过在所述介电层(112)中的所述沟槽(114、116)中的所述硅锗缓冲层(118、132)上外延生长形成所述鳍,接着通过CMP平面化,将所述鳍下降至所述介电层(112)。使所述介电层(112)凹陷以暴露所述鳍。可以同时地或单独地形成所述鳍。
Description
背景技术
本申请通常涉及集成电路,并且特别地涉及集成电路中的MOS晶体管。
具有鳍式场效应晶体管(finFET)的集成电路达到了高栅极密度,但是缺乏由使用高迁移率材料(诸如III-V族材料或锗)的平面晶体管提供的晶体管性能。在高密度集成电路中集成高迁移率材料一直存在问题。
发明内容
可以通过在硅衬底上方形成介电层形成包含n沟道finFET和p沟道finFET的集成电路。穿过所述介电层形成用于n沟道finFET的第一沟槽。在所述第一沟槽中的所述衬底上形成第一硅锗缓冲层,以及通过在所述第一硅锗缓冲层上外延生长形成所述n沟道finFET的所述n沟道鳍。穿过所述介电层形成用于所述p沟道finFET的p沟道鳍的第二沟槽。在所述第二沟槽中的衬底上形成第二硅锗缓冲层,以及通过在所述第二硅锗缓冲层上外延生长形成所述p沟道鳍。随后,使所述介电层凹陷以暴露所述鳍。
附图说明
图1是包含n沟道finFET和p沟道finFET的一个示例集成电路的横截面。
图2A至图2M是在示例制造顺序的连续阶段中描述的图1的集成电路的横截面。
图3A至图3G是在另一个示例制造顺序的连续阶段中描述的图1的集成电路的横截面。
具体实施方式
可以通过两个加工顺序中的任一个形成包含n沟道finFET和p沟道finFET的集成电路。在第一个顺序中,在硅衬底上方形成介电层。穿过介电层形成用于n沟道finFET的n沟道鳍的第一沟槽以暴露衬底。在第一沟槽中的衬底上形成第一硅锗缓冲层,并且在第一硅锗缓冲层上通过高电子迁移率材料的外延生长形成n沟道鳍,该n沟道鳍在介电层上方延伸。在介电层和n沟道鳍上方形成外延阻挡层。穿过覆盖层(cap layer)和介电层形成用于p沟道finFET的p沟道鳍的第二沟槽以暴露衬底。在第二沟槽中的衬底上形成第二硅锗缓冲层,并且在第二硅锗缓冲层上通过高空穴迁移率材料的外延生长形成p沟道鳍,该p沟道鳍在介电层上方延伸。n沟道鳍和p沟道鳍可以在生长期间各自被掺杂。在外延阻挡层和p沟道鳍上方形成覆盖层。CMP过程移除覆盖层和外延阻挡层,并且平坦化n沟道鳍和p沟道鳍,使其下降至介电层。随后,使介电层凹陷以暴露n沟道鳍和p沟道鳍。随后,在n沟道鳍和p沟道鳍上形成栅极介电层,并且在栅极介电层上形成栅极。
在第二顺序中,在硅衬底上方形成介电层,并且穿过介电层同时形成用于n沟道鳍的第一沟槽和用于p沟道鳍的第二沟槽,以暴露衬底。在第一沟槽和在第二沟槽中的衬底上分别同时形成第一硅锗缓冲层和第二硅锗缓冲层。通过在第一硅锗缓冲层和在第二硅锗缓冲层上外延生长高迁移率材料分别同时形成n沟道鳍和p沟道鳍,该n沟道鳍和p沟道鳍在介电层上方延伸。n沟道鳍和p沟道鳍可能在形成期间被掺杂,并且一个鳍注入掺杂剂以反掺杂原位(in-situ)掺杂剂。另选地,可以将掺杂剂注入n沟道鳍和p沟道鳍,以提供所需掺杂密度。在介电层和n沟道鳍与p沟道鳍上方形成覆盖层。CMP过程移除覆盖层,并且平坦化n沟道鳍和p沟道鳍,使其下降至介电层。随后,使介电层凹陷以暴露n沟道鳍和p沟道鳍。随后,在n沟道鳍和p沟道鳍上方形成栅极介电层,并且在栅极介电层上形成栅极。
图1是包含n沟道finFET和p沟道finFET的示例集成电路的横截面。在单晶硅衬底102上形成集成电路100,该单晶硅衬底102包括用于n沟槽finFET106的区域中的p型区104,并且该单晶硅衬底102包括用于p沟槽finFET 110的区域中的n型区108。衬底102可以是块状硅晶片,或在硅晶片上的外延层。在衬底102上方沉积介电层112。介电层112可以包括一层或更多层的二氧化硅,以及可能包括诸如氮氧化硅和/或硼磷硅酸盐玻璃(BPSG)的其它介电材料。介电层112可以是20纳米至40纳米厚。在n沟道finFET 106的区域中穿过介电层112沉积第一沟槽114。在p沟道finFET 110的区域中穿过介电层112沉积第二沟槽116。
n沟道finFET 106包括在第一沟槽114中的沉积在衬底102的p型区104上的第一硅锗缓冲层118。第一硅锗缓冲层118可以是1纳米至5纳米厚,并且可以具有分级组分,使得第一硅锗缓冲层118在衬底102处具有小于百分之20的锗原子分数以及在第一硅锗缓冲层118的顶面处具有超过百分之80的锗原子分数。n沟道finFET 106包括在第一硅锗缓冲层118上的n沟道鳍120,通过至少10纳米的暴露高度124在介电层112的顶面122上方延伸。暴露高度124可以是20纳米至40纳米。在介电层112的顶面122上方的n沟道鳍120的平均宽度126可以小于30纳米(诸如10纳米至20纳米)。n沟道鳍120大体上填充在介电层112的顶面122处的第一沟槽114。将n沟道鳍120掺杂p型以提供用于n沟道finFET 106的所需阈值电压。n沟道鳍120主要是不同于硅的半导体材料,其可能具有与比硅更高的电子迁移率。例如,半导体材料可以是III-V族化合物半导体材料,诸如可能具有铟镓比为50∶50至57∶43的砷化镓、砷化铟镓,或磷化铟。另选地,半导体材料可以是具有锗原子分数大于百分之80的锗或硅锗。利用具有比硅更高的电子迁移率的半导体材料形成n沟道鳍120有利地提供在n沟道finFET 106中的所需的开态电流。n沟道finFET 106包括在n沟道鳍120上方配置的第一栅极介电层128,并且该第一栅极介电层128沿n沟道鳍120的侧面延伸。n沟槽finFET 106包括在第一栅极介电层128上方配置的第一栅极130,该第一栅极130至少部分向下延伸至介电层112的顶面122。第一栅极130可以包括被称为多晶硅的多晶的硅,第一栅极130可以包括金属硅化物,或者第一栅极130可以是金属栅极。
p沟道finFET 110包括在第二沟槽116中的沉积在衬底102的n型区108的第二硅锗缓冲层132。第二硅锗缓冲层132还可以是1纳米至5纳米厚,并且还可以具有与第一硅锗缓冲层118相似的分级组分。p沟道finFET 110包括在第二硅锗缓冲132上的p沟道鳍134,通过至少10纳米的暴露高度136在介电层112的顶面122上部延伸。p沟道鳍134的暴露高度136可以大体上等于n沟道鳍120的暴露高度124。在介电层112的顶面122上部的p沟道鳍134的平均宽度138还可以是小于30纳米(诸如10纳米至20纳米)。p沟道鳍134大体上填充在介电层112的顶面122处的第二沟槽116。将p沟道鳍134掺杂n型以提供用于p沟道finFET 110的所需阈值电压。p沟道鳍134主要是不同于硅的半导体材料,其可能具有比硅更高的空穴迁移率。例如,半导体材料可以是诸如砷化镓的III-V族化合物半导体材料,或可以是具有锗原子分数大于百分之80的锗或硅锗。在实例示例的一个版本中,n沟道鳍120和p沟道鳍134可以主要地由相同的半导体材料形成。利用具有比硅更高的空穴迁移率的半导体材料形成p沟道鳍134有利地提供在p沟道finFET 110中的所需的开态电流。p沟道finFET 110包括在p沟道鳍134上方配置的第二栅极介电层140,并且该第二栅极介电层140沿p沟道鳍134的侧面延伸。p沟槽finFET 110包括在第二栅极介电层140上方配置的第二栅极142,该第二栅极142至少部分向下延伸至介电层112的顶面122。第二栅极142可以包括多晶硅,第二栅极142可以包括金属硅化物,或者第二栅极142可以是金属栅极。
图2A至图2M是图1的描述在示例制造顺序连续阶段中的集成电路的横截面。参照图2A,硅衬底102被提供用于形成集成电路100。在具有50纳米至100纳米的初始厚度的衬底102上方形成介电层112。在衬底102中介电层112可以由硅的热氧化形成,或者可以使用原硅酸四乙酯(还被称为四乙氧基硅烷(TEOS))由诸如等离子体增强化学气相沉积(PECVD)过程的沉积过程形成。介电层112可以包括诸如氮氧化硅或BPSG的其它介电层材料的一层或更多层。
第一沟槽掩膜144被形成在介电层112上方以便暴露用于图1的第一沟槽114的区域,并且以便覆盖用于p沟道的finFET 110的区域。第一沟槽掩膜144可以包括减反射层和通过光刻过程形成的光阻模式。
参照图2B,穿过介电层112形成第一沟槽114,以在由第一沟槽掩膜144暴露的区域中通过刻蚀介电层112暴露衬底102。可以使用反应离子刻蚀(RIE)过程刻蚀介电层112。在形成第一沟槽114之后,诸如通过灰化,接着通过湿法清洗过程移除第一沟槽掩膜144。
参照图2C,在第一沟槽114中的衬底102上形成第一硅锗缓冲层118。在形成第一硅锗缓冲层118之前可以先进行在750℃至850℃处的氢气烘焙。通过在750℃至850℃的温度处使用硅烷或二氯甲硅烷和混合氯化氢的锗烷的外延过程生长第一硅锗缓冲层118。可以变化硅烷或二氯甲硅烷与锗烷的比率,使得在衬底102处的锗的原子分数是小于百分之20,以及在第一硅锗缓冲层118的顶部处的锗的原子分数是大于百分之80,以有利地提供与衬底102匹配的良好的晶格并且以使n沟道鳍120形成。用于形成第一硅锗缓冲层118的外延过程没有在第一沟槽114的侧壁上沉积硅锗,以便显著地减小第一沟槽114的宽度。
参照图2D,可以通过气相外延过程在第一硅锗缓冲层118上形成n沟道鳍120,该n沟道鳍120延伸越过介电层112的顶面122。第一硅锗缓冲层118有利地促进n沟道鳍120的半导体材料的外延生长,其直接地生长在硅衬底102上将会是有问题的。在其中n沟道鳍120主要是砷化铟镓的实例示例的版本中,外延过程可以在150托的压强下和750℃至850℃的温度处使用三甲基铟、三甲基镓或三乙基镓、和砷化氢。可以变化三甲基铟与三甲基镓的比率,以获得n沟道鳍120中的铟与镓的所需比率。在其中n沟道鳍120主要是砷化镓的实例示例的版本中,外延过程可以使用三甲基镓或三乙基镓和砷化氢。在其中n沟道鳍120主要是磷化铟的实例示例的版本中,外延过程可以使用三甲基铟和磷化氢。在其中n沟道鳍120主要是锗的实例示例的版本中,外延过程可以使用锗烷。在其中n沟道鳍120主要是硅锗的实例示例的版本中,外延过程可以使用硅烷或二氯甲硅烷和锗烷。另选地,可以由分子束外延(MBE)过程形成n沟道鳍120。
参照图2E,在介电层112上方形成外延阻挡层146,该外延阻挡层146覆盖n沟道鳍120。外延阻挡层146可以包括20纳米至30纳米厚的氮化硅或氧氮化硅。可以通过在650℃至750℃处使用二氯甲硅烷和氨的低压化学气相沉积(LPCVD)过程形成外延阻挡层146。
参照图2F,在外延阻挡层146上方形成第二沟槽掩膜148,以便暴露用于图1的第二沟槽116的区域,并且以便覆盖用于n沟槽的finFET 106的区域。第二沟槽掩膜148可以包括减反射层和通过光刻过程形成的光阻模式。
参照图2G,穿过外延阻挡层146和介电层112形成第二沟槽116,以在由第二沟槽掩膜148暴露的区域中通过刻蚀外延阻挡层146和介电层112暴露衬底102。可以使用RIE过程刻蚀外延阻挡层146和介电层112。在形成第二沟槽116之后,诸如通过灰化,接着通过湿法清洗过程移除第二沟槽掩膜148。
参照图2H,在第二沟槽116中的衬底102上形成第二硅锗缓冲层132。形成第二硅锗缓冲层132可以使用与用于形成第一硅锗缓冲层118的相同或相似的过程。在衬底102处的锗的原子分数可以是小于百分之20,以及在第二硅锗缓冲层132的顶部处的锗的原子分数可以是大于百分之80,以有利地提供与衬底102匹配的良好的晶格并且以使p沟道鳍134形成。
参照图2I,在第二硅锗缓冲层132上形成p沟道鳍134,该p沟道鳍134延伸越过介电层112的顶面122,并且如图2H所示可能延伸越过外延阻挡层146的顶面。第二硅锗缓冲层132有利地促进p沟道鳍134的半导体材料的外延生长,其直接地生长在硅衬底102上将会是有问题的。p沟道鳍134可以主要是锗或主要是硅锗,并且可以如参照图2D描述的通过气相外延过程形成。另选地,可以通过MBE过程形成p沟道鳍134。
参照图2J,在外延阻挡层146上方形成覆盖层150,该覆盖层150覆盖p沟道鳍134。覆盖层150可以包括20纳米至30纳米厚的二氧化硅、氮化硅、和/或氧氮化硅。可以通过使用针对二氧化硅的TEOS的PECVD过程和/或针对氮化硅的双(叔丁基氨基)硅烷(BTBAS)在500℃至600℃形成覆盖层150。
参照图2K,示意性描述为CMP衬垫152的CMP过程152移除图2J的覆盖层150和外延阻挡层146,并且平坦化n沟道鳍120和p沟道鳍134,使其下降至介电层112。由于外延阻挡层146包括氮化硅或氧氮化硅,并且介电层112包括二氧化硅,所以可以通过外延阻挡层146和介电层112之间的抛光阻力方面的变化提供用于CMP过程152的端点(endpoint)。
图2L描述在完成图2K的CMP过程152之后的集成电路100。n沟道鳍120和p沟道鳍134可以是大体上与介电层112的顶面122共面。
参照图2M,在没有从n沟道鳍120和p沟道鳍134显著地移除半导体材料的情况下使介电层112凹陷,使得n沟道鳍120和p沟道鳍134在所凹陷的介电层112上部延伸至少10纳米。可以通过等离子体刻蚀使介电层112凹陷,该等离子刻蚀对相对于n沟道鳍120和p沟道鳍134的半导体材料的介电层112的介电材料(诸如二氧化硅)有选择性。另选地,可以通过诸如氢氟酸的稀释缓冲水溶液的湿法刻蚀使介电层112凹陷,该等离子刻蚀对相对于n沟道鳍120和p沟道鳍134的半导体材料的介电层112的介电材料(诸如二氧化硅)有选择性。在使介电层122凹陷之后,在n沟道鳍120和p沟道鳍134上方形成栅极介电层和栅极以提供图1的结构。还可以通过另选的示例制造顺序获得图2M的结构,其中p沟道鳍134在n沟道鳍120之前形成。
图3A至图3G是图1的描述在另一个示例的制造顺序连续阶段中的集成电路的横截面。参照图3A,硅衬底102被提供用于形成集成电路100。在具有50纳米至100纳米的初始厚度的衬底102上方形成介电层112。在介电层112上方形成沟槽掩膜154,以便暴露用于图1的第一沟槽114和第二沟槽116的区域。穿过介电层112形成第一沟槽114和第二沟槽116,以在由沟槽掩膜154暴露的区域中通过刻蚀介电层112暴露衬底102。在形成第一沟槽114和第二沟槽116之后,移除沟槽掩膜154。
参照图3B,如参照图2C和图2H所描述,第一硅锗缓冲层118和第二硅锗缓冲层132被同时地分别形成在第一沟槽114和第二沟槽116中的衬底102上。在实例示例中,第一硅锗缓冲层118和第二硅锗缓冲层132具有锗原子分数的相同组分和相同剖面。
同时在第一硅锗缓冲层118和第二硅锗缓冲层132上分别形成n沟道鳍120和p沟道鳍134,该n沟道鳍120和p沟道鳍134如参照图2D和图2I所描述延伸越过介电层112的顶面122。在实例示例中,n沟道鳍120和p沟道鳍134具有相同组分。n沟道鳍120和p沟道鳍134的半导体材料具有比硅更高的电子迁移率和更高的空穴迁移率。n沟道鳍120和p沟道鳍134的半导体材料可以大体上不掺杂或轻掺杂,可以在外延生长过程期间将n沟道鳍120和p沟道鳍134掺杂n型,或可以在外延生长过程期间将n沟道鳍120和p沟道鳍134掺杂p型。同时形成n沟道鳍120和p沟道鳍134有利地降低制造成本和集成电路100的复杂度。
参照图3C,可以在介电层112上形成可选的第一注入掩膜156,以便暴露p沟道鳍134并且覆盖n沟道鳍120。如果需要,则可以以提供用于p沟道finFET 110的所需阈值电压的剂量将诸如磷和可能的砷的n型掺杂剂158注入p沟道鳍134中。剂量将取决于所需阈值电压和取决于p沟道鳍134的高度。在注入n型掺杂剂158之后移除第一注入掩膜156。随后执行退火操作,以激活所注入的n型掺杂剂158。
参照图3D,可以在介电层112上方形成可选的第二注入掩膜160,以便暴露n沟道鳍120并且覆盖p沟道鳍134。如果需要,则可以以提供用于n沟道finFET 106的所需阈值电压的剂量将诸如硼的p型掺杂剂162注入n沟道鳍120中。剂量将取决于所需阈值电压和取决于n沟道鳍120的高度。在注入p型掺杂剂162之后移除第二注入掩膜160。随后执行退火操作,以激活所注入的p型掺杂剂162。
参照图3E,在外延阻挡层112上方形成覆盖层150,该覆盖层150覆盖n沟道鳍120和p沟道鳍134。在实例示例中,覆盖层150可以包括20纳米至30纳米厚的氮化硅,和/或氧氮化硅。可以如参照图2J所描述形成覆盖层150。
参照图3F,示意性描述为CMP衬垫152的CMP过程152移除盖层150,并且平坦化n沟道鳍120和p沟道鳍134,使其下降至介电层112。由于覆盖层150包括氮化硅或氧氮化硅,并且介电层112包括二氧化硅,所以可以通过覆盖层150和介电层112之间的抛光阻力方面的变化提供用于CMP过程152的端点。
参照图3G,如参照图2M所描述,在没有从n沟道鳍120和p沟道鳍134显著地移除半导体材料的情况下使介电层112凹陷,使得n沟道鳍120和p沟道鳍134在所凹陷的介电层112上部延伸至少10纳米。在使介电层112凹陷之后,在n沟道鳍120和p沟道鳍134上方形成栅极介电层和栅极以提供图1的结构。
在所描述的实施例中,修改是可能的,并且其它实施例在权利要求范围内是可能的。
Claims (20)
1.一种集成电路,所述集成电路包括:
衬底,所述衬底包括硅,所述衬底具有在用于n沟道鳍式场效应晶体管即finFET的区域中的p型区,和具有在用于p沟道finFET的区域中的n型区;
介电层,所述介电层在所述衬底上方配置,所述介电层具有下降至用于所述n沟道finFET的区域中的所述衬底的第一沟槽并且具有下降至用于所述p沟道finFET的区域中的所述衬底的第二沟槽;
第一硅锗缓冲层,所述第一硅锗缓冲层在所述第一沟槽中的所述衬底的所述p型区上配置;
第二硅锗缓冲层,所述第二硅锗缓冲层在所述第二沟槽中的所述衬底的所述n型区上配置;
所述n沟道finFET的n沟道鳍,所述n沟道finFET的所述n沟道鳍在所述第一硅锗缓冲层上配置,所述n沟道鳍在所述介电层的顶面上方延伸至少10纳米,所述n沟道鳍具有p型掺杂,所述n沟道鳍包括与硅不同的半导体材料;以及
所述p沟道finFET的p沟道鳍,所述p沟道finFET的所述p沟道鳍在所述第二硅锗缓冲层上配置,所述p沟道鳍在所述介电层的所述顶面上方延伸至少10纳米,所述p沟道鳍具有n型掺杂,所述p沟道鳍包括与硅不同的半导体材料。
2.根据权利要求1所述的集成电路,其中:
所述第一硅锗缓冲层具有少于百分之20的在所述衬底处的锗原子分数,并且具有超过百分之80的在所述第一硅锗缓冲层的顶面处的锗原子分数;以及
所述第二硅锗缓冲层具有少于百分之20的在所述衬底处的锗原子分数,并且具有超过百分之80的在所述第二硅锗缓冲层的顶面处的锗原子分数。
3.根据权利要求1所述的集成电路,其中,所述n沟道鳍包括砷化镓。
4.根据权利要求1所述的集成电路,其中,所述n沟道鳍包括砷化铟镓。
5.根据权利要求4所述的集成电路,其中,所述n沟道鳍具有50∶50至57∶43的铟与镓的比例。
6.根据权利要求1所述的集成电路,其中,所述n沟道鳍包括磷化铟。
7.根据权利要求1所述的集成电路,其中,所述n沟道鳍包括锗。
8.根据权利要求1所述的集成电路,其中,所述p沟道鳍包括硅锗。
9.根据权利要求1所述的集成电路,其中,所述p沟道鳍包括锗。
10.一种形成集成电路的方法,所述方法包括:
提供包括硅的衬底,所述衬底具有在用于第一极性finFET的区域中的第一导电类型的第一区和具有在用于第二相反极性finFET的区域中的第二相反导电类型的第二区;
在所述衬底上方形成50纳米至100纳米厚的介电层50;
在所述介电层中形成第一沟槽,所述第一沟槽下降至用于所述第一极性finFET的所述区域中的所述衬底;
在所述第一沟槽中的所述衬底上形成1纳米至5纳米厚的第一硅锗缓冲层;
在所述第一硅锗缓冲层上形成所述第一极性finFET的第一极性鳍,使得所述第一极性鳍在所述介电层的顶面上方延伸;
在所述介电层上方形成外延阻挡层,以便覆盖所述第一极性鳍;
在所述外延阻挡层和所述介电层中形成第二沟槽,所述第二沟槽下降至用于所述第二极性finFET的所述区域中的所述衬底;
在所述第二沟槽中的所述衬底上形成1纳米至5纳米厚的第二硅锗缓冲层;
在所述第二硅锗缓冲层上形成所述第二极性finFET的第二极性鳍,使得所述第二极性鳍在所述介电层的顶面上方延伸;
在所述外延阻挡层上方形成介电材料的覆盖层,以便覆盖所述第二极性鳍;
通过化学机械抛光即CMP过程移除所述覆盖层和所述外延阻挡层,以便平坦化所述第一极性鳍和所述第二极性鳍,使所述第一极性鳍和所述第二极性鳍下降至所述介电层;以及
使所述介电层凹陷,使得所述第一极性鳍和所述第二极性鳍在所述介电层上方延伸至少10纳米。
11.根据权利要求10所述的方法,其中:
形成所述第一硅锗缓冲层,以具有少于百分之20的在所述衬底处的锗原子分数,和超过百分之80的在所述第一硅锗缓冲层的顶面处的锗原子分数;以及
形成所述第二硅锗缓冲层,以具有少于百分之20的在所述衬底处的锗原子分数,和超过百分之80的在所述第二硅锗缓冲层的顶面处的锗原子分数。
12.根据权利要求10所述的方法,其中,所述n沟道鳍包括砷化镓。
13.根据权利要求10所述的方法,其中,所述n沟道鳍包括砷化铟镓。
14.根据权利要求13所述的方法,其中,所述n沟道鳍具有50∶50至57∶43的铟与镓的比例。
15.根据权利要求10所述的方法,其中,所述n沟道鳍包括磷化铟。
16.根据权利要求10所述的方法,其中,所述n沟道鳍包括锗。
17.根据权利要求10所述的方法,其中,所述p沟道鳍包括锗。
18.一种形成集成电路的方法,所述方法包括:
提供包括硅的衬底,所述衬底具有在用于第一极性finFET的区域中的第一导电类型的第一区和具有在用于第二相反极性finFET的区域中的第二相反导电类型的第二区;
形成在所述衬底上方的50纳米至100纳米厚的介电层;
同时形成在所述介电层中的下降至用于所述第一极性finFET的所述区域中的所述衬底的第一沟槽和在所述介电层中的下降至用于所述第二极性finFET的所述区域中的所述衬底的第二沟槽;
同时形成在所述第一沟槽中的所述衬底上的1纳米至5纳米厚的第一硅锗缓冲层和在所述第二沟槽中的所述衬底上的1纳米至5纳米厚的第二硅锗缓冲层;
同时形成在所述第一硅锗缓冲层上的所述第一极性finFET的第一极性鳍和在所述第二硅锗缓冲层上的所述第二极性finFET的第二极性鳍,使得所述第一极性鳍和所述第二极性鳍在所述介电层的顶面上方延伸;
在所述介电层上方形成介电材料的覆盖层,以便覆盖所述第一极性鳍和所述第二极性鳍;
通过CMP过程移除所述覆盖层,以便平坦化所述第一极性鳍和所述第二极性鳍,使所述第一极性鳍和所述第二极性鳍下降至所述介电层;以及
使所述介电层凹陷,使得所述第一极性鳍和所述第二极性鳍在所述介电层上方延伸至少10纳米。
19.根据权利要求18所述的方法,其中,形成所述第一硅锗缓冲层和所述第二硅锗缓冲层,以具有少于百分之20的在所述衬底处的硅原子分数,和超过百分之80的在所述第一硅锗缓冲层和所述第二硅锗缓冲层的顶面处的锗原子分数。
20.根据权利要求18所述的方法,其中,所述第一极性鳍和所述第二极性鳍包括锗。
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