CN105845084A - Grid driving unit, line grid scanning driver and driving method - Google Patents
Grid driving unit, line grid scanning driver and driving method Download PDFInfo
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- CN105845084A CN105845084A CN201610362978.1A CN201610362978A CN105845084A CN 105845084 A CN105845084 A CN 105845084A CN 201610362978 A CN201610362978 A CN 201610362978A CN 105845084 A CN105845084 A CN 105845084A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Shift Register Type Memory (AREA)
Abstract
The invention discloses a grid driving unit, a line grid scanning driver and a driving method. The grid driving unit is composed of a signal acquisition module, a step-up module, an inverter module, a negative voltage module, an internal output module and a scanning output module. Through the negative voltage module, the grid scanning unit can operate normally by requiring only a single negative power supply, thereby reducing the clock hopping amplitude and lowering the circuit power consumption while simplifying the circuit structure and reducing the circuit area. In addition, the output module adopts a direct-current driving mode, thereby being capable of reducing the dynamic power consumption, and improving the response speed. Multiple stages of grid driving units are connected in series and then connected with a corresponding power supply and a time sequence control module so as to form the line grid scanning driver. The driver can realize shift output of grid driving signals by requiring only three driving clocks, and all of the driving clocks are assembly-line type driving time sequences with the duty ratio being 33.3%, thereby being simple and independent in time sequence, avoiding occurrence of competition and adventure, and improving the circuit stability.
Description
Technical field
The present invention relates to the row gated sweep field of active matrix light-emitting flat faced display, be specifically related to a kind of grid
Pole driver element and row gated sweep driver and driving method thereof.
Background technology
Traditional display floater row gate driver circuit needs special driving chip, by technique by chip pressure
Connect and drive image element circuit on the glass substrate.In recent years, along with the development of technology, thin film transistor (TFT) is utilized to exist
Display floater is directly integrated row gate driver circuit to replace the row integrated technology of driving chip to become current
The hot topic of research.Row integrated technology make gate driver circuit and image element circuit are integrated in same an array, permissible
The sequential avoiding signal lead difference in length to cause by placement-and-routing is chaotic, improves signal quality；All right
Reduce substrate area, reduce processing step to reduce cost.Additionally, for small-medium size display screen, row collection
One-tenth technology can greatly shorten frame distance, it is achieved narrow frame is to meet people's aesthetic requirement.Hangzhoupro integrated technology
Can also well solve traditional die and may not apply to a difficult problem for Flexible Displays.
Novel oxide thin film transistor device becomes closely because of its excellent performance, simple manufacturing process
Popular object of study over Nian, but oxide thin film transistor is N-type device, has the characteristic of negative threshold voltage,
If using the line-scan circuit for the exploitation of positive threshold voltage characteristic transistor, then can be because of sull crystal
Pipe can not thoroughly be closed and be caused circuit power consumption to increase severely and even cannot normally work.In order to thoroughly turn off oxide
Thin film transistor (TFT), can use inside most of novel line-scanning drive circuits two the most plural negative
Power supply, but many negative supplies can allow circuit structure become complicated, interconnector increases, and circuit area increases,
Requirement to each power supply is the most harsh simultaneously.Additionally, most of line scanners are all to make use of exchange clock
Signal goes to provide output electric current, and the parasitic capacitance of output transistor not only can consume considerable power consumption, and
Circuit switching speeds also can be reduced because of discharge and recharge.
Summary of the invention
In order to overcome shortcoming that prior art exists with not enough, primary and foremost purpose of the present invention is to provide a kind of grid and drives
Moving cell and row gated sweep driver.
The driving method and the row gated sweep that it is a further object to provide a kind of drive element of the grid drive
The driving method of dynamic device.
The present invention adopts the following technical scheme that
A kind of drive element of the grid, by signal acquisition module, boost module, inverter modules, negative pressure module,
Internal output module and scanning output module are constituted, when the control signal of described drive element of the grid includes first
Clock input port IN_EN, second clock input port OUT_EN, the 3rd clock input port CLR, the first power port
VDD, second source mouth VSS, signals collecting mouth Cin, the first delivery outlet COUT and the second delivery outlet GOUT；
Described signal acquisition module is made up of first and second transistor, and the first transistor M1 drain electrode is adopted with signal
Collection mouth Cin be connected, its source electrode is connected with the drain electrode of transistor seconds M2, its grid respectively with transistor seconds
The grid of M2 and the first clock input port IN_EN are connected；
Described boost module is made up of the 6th transistor M6 and first storage electric capacity C1, the 6th transistor M6's
The source electrode of grid and the other end of the first storage electric capacity C1 and transistor seconds M2 is connected, and stores as signal
Node Q, the drain electrode of the 6th transistor M6 is connected with second clock input port OUT_EN, the 6th transistor M6
Source electrode and first storage electric capacity C1 one end connect；
Described inverter modules is made up of third transistor M3 and the 9th transistor M9, and third transistor M3 is leaked
Pole is connected with the first power port VDD, and the grid of third transistor M3 and the 3rd clock input port CLR are connected,
The source electrode of third transistor M3 and the grid of the 9th transistor M9 are connected, and the output as inverter modules saves
Point QB；The drain electrode of the 9th transistor M9 is connected with signal memory node Q, the source electrode of the 9th transistor M9 with
Second source mouth VSS is connected.
Negative pressure module is by the 4th transistor M4, the 5th transistor M5, the 7th transistor M7, the 8th transistor
M8 and second storage electric capacity C2 is constituted；The drain electrode of described 4th transistor M4 and the one of the second storage electric capacity C2
End is all connected with phase inverter output node QB, the source electrode of described 4th transistor M4 and the 5th transistor M5's
Drain electrode is connected, the grid of described 4th transistor M4 and the grid of the 5th transistor M5, the 7th transistor M7
Grid be all connected with signals collecting mouth Cin；The source electrode of the 5th transistor M5 is connected with second source mouth VSS；
The drain electrode of the 7th transistor M7 is connected with the first power port VDD, and the source electrode of the 7th transistor M7 is respectively with
The other end of the drain electrode of eight transistor M8 and the second storage electric capacity C2 is connected；The grid of the 8th transistor M8 with
Second clock input port OUT_EN is connected, and the source electrode of the 8th transistor M8 is connected with second source mouth VSS
Internal output module is made up of the tenth transistor M10 and the 11st transistor M11, described tenth crystal
The drain electrode of pipe M10 is connected with the first power port VDD, and the grid of described tenth transistor M10 stores with signal
Node Q is connected, and the source electrode of the tenth transistor M10 and the drain electrode of the 11st transistor M11 all export with first
Mouth COUT is connected；The grid of the 11st transistor M11 is connected with phase inverter output node QB, and the 11st is brilliant
The source electrode of body pipe M11 is connected with second source mouth VSS
Scanning output module is made up of the tenth two-transistor M12 and the 13rd transistor M13, and the described 12nd
The drain electrode of transistor M12 is connected with the first power port VDD, and the grid of the tenth two-transistor M12 is deposited with signal
Storage node Q is connected, and the source electrode of the tenth two-transistor M12 and the drain electrode of the 13rd transistor M13 are all with second
Delivery outlet GOUT is connected；The grid of the 13rd transistor M13 is connected with output node QB, the 13rd crystal
The source electrode of pipe M13 is connected with second source mouth VDD.
The transistor of drive element of the grid is N-type TFT.
A kind of row gated sweep driver, including power supply and time-sequence control mode and row raster data model array, its
The output signal of middle power supply and time-sequence control mode is high voltage VD, low-voltage VS, the first clock CK1, the
Two clock CK2, the 3rd clock CK3, triggering clock VI；
The row raster data model group that described row raster data model array is connected by N level is constituted, each row raster data model group by
First grid driver element, second grid driver element and the 3rd drive element of the grid are constituted, described first,
The control signal of second and third drive element of the grid all includes that the first clock input port IN_EN, second clock are defeated
Entrance OUT_EN, the 3rd clock input port CLR, the first power port VDD, second source mouth VSS, signal are adopted
Collection mouth Cin, the first delivery outlet COUT and the second delivery outlet GOUT.
In row raster data model array, the signal of the first grid driver element in first order row raster data model group is adopted
Collection mouth Cin is connected with the triggering clock VI of time-sequence control mode with power supply；
The signals collecting mouth Cin of first grid driver element and K-1 level row in K level row raster data model group
In raster data model group, the first delivery outlet COUT of the 3rd drive element of the grid is connected, second grid driver element
Signals collecting mouth Cin be connected with the first delivery outlet COUT of first grid driver element, the 3rd grid drives
The signals collecting mouth Cin of moving cell is connected with the first delivery outlet COUT of second grid driver element；
Every first clock input port IN_EN of first grid driver element of one-level row raster data model group, second
Clock input port OUT_EN, the 3rd clock input port CLR respectively with the first of power supply and time-sequence control mode
Clock CK1, second clock CK2, the 3rd clock CK3 are connected；
First clock input port IN_EN, the second clock input port OUT_EN of second grid driver element and
3rd clock input port CLR respectively with power supply and the second clock CK2 of time-sequence control mode, the 3rd clock
CK3, the first clock CK1 are connected；
First clock input port IN_EN, the second clock input port OUT_EN of the 3rd drive element of the grid and
3rd clock input port CLR respectively with power supply and the 3rd clock CK3 of time-sequence control mode, the first clock
CK1, second clock CK2 are connected.
The high level of described first to the 3rd clock signal is equal with high voltage VD, told first the 3rd clock
The low level of signal is equal with low-voltage VS.
A kind of driving method of drive element of the grid, the first clock input port IN_EN, second clock input port
The clock-pulse width that OUT_EN and the 3rd clock input port CLR is inputted is identical, and dutycycle is
33.3%, and level pulse from the first clock input port IN_EN successively to second clock input port OUT_EN,
The streamline sequential of the 3rd clock input port CLR shifting flow；
Driving method specifically includes signals collecting memory phase, signal output stage and reset phase；
Signals collecting memory phase: flare IN_EN high input voltage when first, by the first transistor M1,
Transistor seconds M2 opens, signals collecting mouth Cin input high level signal, and is input to gather signal storage
In some Q, the grid of the 6th transistor M6 and the first storage electric capacity C1, the tenth transistor M10, the 12nd
Transistor M12 is opened, and is simultaneously entered high level signal by the 4th transistor M4, the 5th transistor M5
Opening, reverse output node QB is pulled low to low-voltage state, the 9th transistor M9, the 11st transistor
M11 and the 13rd transistor M13 is turned off, the first delivery outlet COUT, the second delivery outlet GOUT output
Positive voltage, but less than input high level VD.Additionally, the 7th transistor M7 is also turned on, electric current is from first
Power port VDD flow into, by the 7th transistor M7, second storage electric capacity C2, the 4th transistor M4,
Flowing out through second source mouth VSS after 5th transistor M5 and form loop, the second storage electric capacity C2 is electrically charged,
Now node N is high level, and output node QB is low level；During second clock mouth OUT_EN and the 3rd
Flare CLR all inputs low-voltage.Subsequently, the first clock signal IN_EN becomes low-voltage, by first crystal
Pipe M1, transistor seconds M2 turn off, and signals collecting mouth Cin input low-voltage turns off the 4th transistor M4
With, the 5th transistor M5 and the 7th transistor M7, signals collecting completes, and this stage continued for 1/3 clock week
Time phase；
Signal output the stage: second clock mouth OUT_EN high input voltage, due to the first electric capacity C1 from
Act effect, the high level of the level saltus step of signal memory node Q to about twice VD, the tenth transistor M10
And the tenth two-transistor M12 be fully opened, the first delivery outlet COUT, second delivery outlet GOUT output
Level is about the driving signal of VD；Meanwhile, the 8th transistor M8 is opened, now the current potential of node N
It is low level with the 9th transistor M9, the 11st transistor M11 and the 13rd transistor M13 source potential
VS；3rd clock input port CLR and signals collecting mouth Cin input low level signal simultaneously, the 3rd to the 5th
Transistor is closed, and reverse output point QB is in quick condition relative to arbitrary power port, and owing to second deposits
Storage electric capacity C2 storage effect, the 9th transistor M9, the 11st transistor M11 and the 13rd transistor M13
Gate-source voltage difference be negative, above-mentioned transistor is thoroughly closed, it is to avoid interference output signals, and this stage holds
Continuous 1/3 clock period time；
Reset phase: flare CLR input high level signal when the 3rd, third transistor M3 is opened, instead
High level is become, the 9th transistor M9, the 11st transistor M11 and the 13rd crystal to output node QB
Pipe M13 is opened, and gathers signal storage point Q and becomes low level, the tenth transistor M10, the 12nd crystal
Pipe M12 is turned off, and the first delivery outlet COUT and the second delivery outlet GOUT all exports low-voltage, circuit weight
Putting complete, this stage continues 1/3 clock period time.
A kind of driving method of row gated sweep driver, the first clock CK1, second clock CK2, the 3rd
The pulse width of clock CK3 is identical with the cycle, and dutycycle is 33.3%, and is that level pulse is from the first clock
CK1, successively to second clock CK2, the streamline sequential of the 3rd clock CK3 cyclic shift；
When clock VI produces the level pulse identical for clock CK1 with first upon activation, row gated sweep drives
Device enters initial phase, and after 1/3 clock cycle T, first order drive element of the grid produces gate drive signal,
Drive element of the grid the most at different levels are driven by clock and produce gate drive signal step by step, when afterbody grid drives
While moving cell produces gate drive signal, trigger clock VI and also produce identical with this gate drive signal
Level pulse, row gated sweep driver enters duplication stages, and after 1/3 clock cycle T, first order grid drives
Moving cell second time produces gate drive signal, and row gated sweep drives process to terminate.
Beneficial effects of the present invention:
(1) row driver circuits invented is by by built-in negative pressure module, reducing many
The circuit layout difficulty of power rows driver, saving circuit area, moreover it is possible to reduce the clock voltage amplitude of oscillation, raising
Circuit efficiency.
(2) DC control is utilized to scan output module, it is to avoid conventional AC control mode is posted because of output transistor
The dynamic power consumption giving birth to electric capacity and cause, produces after taking full advantage of the coupling bootstrapping of circuit internal capacitance meanwhile
High voltage drives large scale TFT, reduces delay effect, beneficially high frequency and shows.
(3) internal novel invertor module is utilized, it is to avoid occur that the direct current flowing to low-voltage from high voltage returns
Road, greatly reduces the power consumption of driver.
(4) driving method utilizes 33.3% dutycycle timing control signal acquisition module, boost module, anti-phase
Device module, negative pressure module and internal output module, it is possible to avoid inside that race hazard situation occurs, increase electricity
The stability on road and reliability, be advantageously implemented high frequency and show.
Accompanying drawing explanation
Fig. 1 is the circuit theory diagrams of the drive element of the grid in the embodiment of the present invention；
Fig. 2 is the structural representation of the row gated sweep driver in the embodiment of the present invention；
Fig. 3 is that the present invention implements driver element connection diagram in the row raster data model group in row；
Fig. 4 is the driver' s timing oscillogram of Fig. 1 drive element of the grid in the embodiment of the present invention；
Fig. 5 is Fig. 2 row gated sweep driver drives timing waveform in the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail, but the enforcement of the present invention
Mode is not limited to this.
Embodiment
As it is shown in figure 1, a kind of drive element of the grid, by signal acquisition module 11, boost module 12, anti-phase
Device module 13, negative pressure module 14, internal output module 15 and scanning output module 16 are constituted, described grid
The control signal of driver element include the first clock input port IN_EN, second clock input port OUT_EN,
Three clock input port CLR, the first power port VDD, second source mouth VSS, signals collecting mouth Cin, first
Delivery outlet COUT and the second delivery outlet GOUT；
Described signal acquisition module 11 is made up of first and second transistor, the first transistor M1 drain electrode and letter
Number acquisition port Cin is connected, and its source electrode is connected with the drain electrode of transistor seconds M2, its grid respectively with the second crystalline substance
The grid of body pipe M2 and the first clock input port IN_EN are connected；
Described boost module 12 is made up of the 6th transistor M6 and first storage electric capacity C1, the 6th transistor M6
Grid and the source electrode of the first storage other end of electric capacity C1 and transistor seconds M2 be connected, deposit as signal
Storage node Q, the drain electrode of the 6th transistor M6 is connected with second clock input port OUT_EN, the 6th transistor
One end of the source electrode of M6 and the first storage electric capacity C1 connects；
Described inverter modules 13 is made up of third transistor M3 and the 9th transistor M9, third transistor M3
Drain electrode is connected with the first power port VDD, and the grid of third transistor M3 and the 3rd clock input port CLR are connected,
The source electrode of third transistor M3 and the grid of the 9th transistor M9 are connected, and the output as inverter modules saves
Point QB；9th transistor M9 drain electrode is connected with signal memory node Q, the source electrode of the 9th transistor M9 and the
Two power port VSS are connected.
Negative pressure module 14 is by the 4th transistor M4, the 5th transistor M5, the 7th transistor M7, the 8th crystal
Pipe M8 and second storage electric capacity C2 is constituted；The drain electrode of described 4th transistor M4 and the second storage electric capacity C2
One end be all connected with phase inverter output node QB, the source electrode of described 4th transistor M4 and the 5th transistor
The drain electrode of M5 is connected, the grid of described 4th transistor M4 and the 5th transistor M5 grid, the 7th transistor
M7 grid is all connected with signals collecting mouth Cin；The source electrode of the 5th transistor M5 is connected with second source mouth VSS；
The drain electrode of the 7th transistor M7 is connected with the first power port VDD, and the source electrode of the 7th transistor M7 is respectively with
The other end of the drain electrode of eight transistor M8 and the second storage electric capacity C2 is connected；The grid of the 8th transistor M8 with
Second clock input port OUT_EN is connected, and the source electrode of the 8th transistor M8 is connected with second source mouth VSS
Internal output module 15 is made up of the tenth transistor M10 and the 11st transistor M11, and the described tenth is brilliant
The drain electrode of body pipe M10 is connected with the first power port VDD, and the grid of described tenth transistor M10 is believed with gathering
Number memory node Q is connected, and the source electrode of the tenth transistor M10 and the drain electrode of the 11st transistor M11 are all with the
One delivery outlet COUT is connected；The grid of the 11st transistor M11 is connected with phase inverter output node QB, the
The source electrode of 11 transistor M11 is connected with second source mouth VSS
Scanning output module 16 is made up of the tenth two-transistor M12 and the 13rd transistor M13, and the described tenth
The drain electrode of two-transistor M12 is connected with the first power port VDD, the grid of the tenth two-transistor M12 and collection
Signal memory node Q is connected, and the source electrode of the tenth two-transistor M12 and the drain electrode of the 13rd transistor M13 are equal
It is connected with the second delivery outlet GOUT；The grid of the 13rd transistor M13 is connected with phase inverter output node QB,
The source electrode of the 13rd transistor M13 is connected with second source mouth VDD.
All transistors of drive element of the grid are N-type TFT.
As in figure 2 it is shown, a kind of row gated sweep driver, including power supply and time-sequence control mode 20 and row grid
Pole drives array 30, and wherein power supply is high voltage VD, low-voltage with the output signal of time-sequence control mode 20
VS, the first clock CK1, second clock CK2, the 3rd clock CK3, triggering clock VI；
The row raster data model group that described row raster data model array 30 is connected by N level is constituted, each row raster data model
Group is made up of first grid driver element 31, second grid driver element 32 and the 3rd drive element of the grid 33,
The control signal of described first, second and third drive element of the grid all include the first clock input port IN_EN,
Second clock input port OUT_EN, the 3rd clock input port CLR, the first power port VDD, second source mouth
VSS, signals collecting mouth Cin, the first delivery outlet COUT and the second delivery outlet GOUT.
Described first, second and third drive element of the grid is the structure shown in Fig. 1.
Fig. 3 is the internal connection figure of all row raster data model groups, and its concrete connected mode is:
The signals collecting mouth Cin of the first grid driver element in first order row raster data model group and power supply and time
The triggering clock VI of sequence control module is connected；
The signals collecting mouth Cin of first grid driver element and K-1 level row in K level row raster data model group
In raster data model group, the first delivery outlet COUT of the 3rd drive element of the grid is connected, and described K is for being more than or equal to
The integer of 2；
The signals collecting mouth Cin of second grid driver element and the first delivery outlet of first grid driver element
COUT is connected, and the signals collecting mouth Cin of the 3rd drive element of the grid is defeated with the first of second grid driver element
Outlet COUT is connected；
Every first clock input port IN_EN of first grid driver element of one-level row raster data model group, second
Clock input port OUT_EN, the 3rd clock input port CLR respectively with the first of power supply and time-sequence control mode
Clock CK1, second clock CK2, the 3rd clock CK3 are connected；
First clock input port IN_EN, the second clock input port OUT_EN of second grid driver element and
3rd clock input port CLR respectively with power supply and the second clock CK2 of time-sequence control mode, the 3rd clock
CK3, the first clock CK1 are connected；
First clock input port IN_EN, the second clock input port OUT_EN of the 3rd drive element of the grid and
3rd clock input port CLR respectively with power supply and the 3rd clock CK3 of time-sequence control mode, the first clock
CK1, second clock CK2 are connected.`
Second delivery outlet GOUT of first grid driver element is lead-in wire GOUT1；The of second grid driver element
Two delivery outlet GOUT are lead-in wire GOUT2；Second delivery outlet GOUT of the 3rd drive element of the grid is lead-in wire
GOUT3。
The high level of described first to the 3rd clock signal is equal with high voltage VD, when described first to the 3rd
The low level of clock signal is equal with low-voltage VS.
As shown in Figure 4, the driving method of a kind of drive element of the grid, the first clock input port IN_EN,
The clock-pulse width that two clock input port OUT_EN and the 3rd clock input port CLR are inputted is identical,
Dutycycle is 33.3%, and level pulse from the first clock input port IN_EN successively to second clock input port
OUT_EN, the streamline sequential of the 3rd clock input port CLR shifting flow.
Including signals collecting memory phase, signal output stage and reset phase；
Signals collecting memory phase: flare IN_EN high input voltage when first, by the first transistor M1,
Transistor seconds M2 opens, signals collecting mouth Cin input high level signal, and is input to gather signal storage
In some Q, the grid of the 6th transistor M6 and the first storage electric capacity C1, the tenth transistor M10, the 12nd
Transistor M12 is opened, and is simultaneously entered high level signal by the 4th transistor M4, the 5th transistor M5
Opening, reverse output node QB is pulled low to low-voltage state, the 9th transistor M9, the 11st transistor
M11 and the 13rd transistor M13 is turned off, the first delivery outlet COUT, the second delivery outlet GOUT output
Positive voltage, but less than input high level VD.Additionally, the 7th transistor M7 is also turned on, electric current is from first
Power port VDD flow into, by the 7th transistor M7, second storage electric capacity C2, the 4th transistor M4,
Flowing out through second source mouth VSS after 5th transistor M5 and form loop, the second storage electric capacity C2 is electrically charged,
Now node N is high level, and output node QB is low level；During second clock mouth OUT_EN and the 3rd
Flare CLR all inputs low-voltage.Subsequently, the first clock signal IN_EN becomes low-voltage, by first crystal
Pipe M1, transistor seconds M2 turn off, and signals collecting mouth Cin input low-voltage turns off the 4th transistor M4
With, the 5th transistor M5 and the 7th transistor M7, signals collecting completes.This stage continued for 1/3 clock week
Time phase；
Signal output the stage: second clock mouth OUT_EN high input voltage, due to the first electric capacity C1 from
Act effect, the high level of the level saltus step of signal memory node Q to about twice VD, the tenth transistor M10
And the tenth two-transistor M12 be fully opened, the first delivery outlet COUT, second delivery outlet GOUT output
Level is about the driving signal of VD；Meanwhile, the 8th transistor M8 is opened, now the current potential of node N
It is low level with the 9th transistor M9, the 11st transistor M11 and the 13rd transistor M13 source potential
VS；3rd clock input port CLR and signals collecting mouth Cin input low level signal simultaneously, the 3rd to the 5th
Transistor is closed, and reverse output point QB is in quick condition relative to arbitrary power port, and owing to second deposits
Storage electric capacity C2 storage effect, the 9th transistor M9, the 11st transistor M11 and the 13rd transistor M13
Gate-source voltage difference be negative, above-mentioned transistor is thoroughly closed, it is to avoid interference output signals.This stage holds
Continuous 1/3 clock period time；
Reset phase: flare CLR input high level signal when the 3rd, third transistor M3 is opened, instead
High level is become, the 9th transistor M9, the 11st transistor M11 and the 13rd crystal to output node QB
Pipe M13 is opened, and gathers signal storage point Q and becomes low level, the tenth transistor M10, the 12nd crystal
Pipe M12 is turned off, and the first delivery outlet COUT and the second delivery outlet GOUT all exports low-voltage, circuit weight
Put complete.This stage continues 1/3 clock period time.
As described in Figure 5, the driving method of a kind of row gated sweep driver, it is characterised in that the first clock
CK1, second clock CK2, the 3rd clock CK3 pulse width identical with the cycle, dutycycle is 33.3%,
And be level pulse from the first clock CK1, to second clock CK2, the stream of the 3rd clock CK3 cyclic shift
Waterline sequential；
When clock VI produces the level pulse identical for clock CK1 with first upon activation, row gated sweep drives
Device enters initial phase, and after 1/3 clock cycle T, first order drive element of the grid produces gate drive signal,
Drive element of the grid the most at different levels are driven by clock and produce gate drive signal step by step.Particularly, when last
While level drive element of the grid produces gate drive signal, triggering clock VI also produces and believes with this raster data model
Number identical level pulse, row gated sweep driver enters duplication stages, after 1/3 clock cycle T, first
Level drive element of the grid second time produces gate drive signal, and now, a complete row gated sweep drives
Process terminates.
By negative pressure module, drive element of the grid only needs single negative supply just can normally work, and simplifies circuit knot
Structure, reduce circuit area while, moreover it is possible to reduce the clock transition amplitude of oscillation, reduce circuit power consumption, export in addition
Module uses DC driven mode, it is possible to reduce dynamic power consumption, improves response speed.Multistage raster data model list
It is connected after unit's series connection and with corresponding power supply and time-sequence control mode and just constitutes row gated sweep driver,
Driver only needs 3 drive clock just can realize grid and drives the displacement output of signal, and all clocks are and account for
The empty pipeline system driver' s timing than 33.3%, sequential is the most independent, it is to avoid race hazard occurs, promotes circuit
Stability.Meanwhile, row gate charges and discharge process are all taken full advantage of the high electricity after circuit internal bootstrap
Pressure drives large scale TFT, improves response speed, beneficially high frequency and shows.
Above-described embodiment is the present invention preferably embodiment, but embodiments of the present invention are not by described reality
Execute the restriction of example, the change made under other any spirit without departing from the present invention and principle, modification,
Substitute, combine, simplify, all should be the substitute mode of equivalence, within being included in protection scope of the present invention.
Claims (7)
1. a drive element of the grid, it is characterised in that by signal acquisition module, boost module, phase inverter
Module, negative pressure module, internal output module and scanning output module are constituted, the control of described drive element of the grid
Signal processed includes the first clock input port IN_EN, second clock input port OUT_EN, the 3rd clock input port
CLR, the first power port VDD, second source mouth VSS, signals collecting mouth Cin, the first delivery outlet COUT and
Second delivery outlet GOUT；
Described signal acquisition module is made up of first and second transistor, and the drain electrode of the first transistor is adopted with signal
Collection mouth Cin be connected, its source electrode is connected with the drain electrode of transistor seconds, its grid respectively with transistor seconds
Grid and the first clock input port IN_EN are connected；
Described boost module is made up of the 6th transistor and the first storage electric capacity, the grid of the 6th transistor and the
The other end of one storage electric capacity and the source electrode of transistor seconds are connected, and as signal memory node Q, the 6th is brilliant
The drain electrode of body pipe is connected with second clock input port OUT_EN, the source electrode of the 6th transistor and the first storage electric capacity
One end connect；
Described inverter modules is made up of third transistor and the 9th transistor, the drain electrode of third transistor and the
One power port VDD is connected, and the grid of third transistor and the 3rd clock input port CLR are connected, the 3rd crystal
The source electrode of pipe and the grid of the 9th transistor are connected, as the output node QB of inverter modules；9th crystal
The drain electrode of pipe is connected with signal memory node Q, and the source electrode of the 9th transistor is connected with second source mouth VSS；
Negative pressure module is deposited by the 4th transistor, the 5th transistor, the 7th transistor, the 8th transistor and second
Storage electric capacity is constituted；One end of the drain electrode of described 4th transistor and the second storage electric capacity is all saved with phase inverter output
Point QB connects, and the source electrode of described 4th transistor and the drain electrode of the 5th transistor are connected, described 4th transistor
Grid and the grid of the grid of the 5th transistor, the 7th transistor be all connected with signals collecting mouth Cin；The
The source electrode of five transistors is connected with second source mouth VSS；The drain electrode of the 7th transistor and the first power port VDD
Be connected, the source electrode of the 7th transistor respectively with the drain electrode of the 8th transistor and the other end phase of the second storage electric capacity
Even；The grid of the 8th transistor is connected with second clock input port OUT_EN, the source electrode of the 8th transistor and
Two power port VSS are connected；
Internal output module is made up of the tenth transistor and the 11st transistor, the drain electrode of described tenth transistor
Being connected with the first power port VDD, the grid of described tenth transistor is connected with signal memory node Q, and the tenth
The source electrode of transistor and the drain electrode of the 11st transistor are all connected with the first delivery outlet COUT；11st transistor
Grid be connected with phase inverter output node QB, the source electrode of the 11st transistor is connected with second source mouth VSS；
Scanning output module is made up of the tenth two-transistor and the 13rd transistor, described tenth two-transistor
Drain electrode is connected with the first power port VDD, and the grid of the tenth two-transistor is connected with signal memory node Q, the
The source electrode of ten two-transistors and the drain electrode of the 13rd transistor are all connected with the second delivery outlet GOUT；Tenth is trimorphism
The grid of body pipe is connected with output node QB, and the source electrode of the 13rd transistor is connected with second source mouth VDD.
Drive element of the grid the most according to claim 1, it is characterised in that the crystalline substance of drive element of the grid
Body pipe is N-type TFT.
3. the row gated sweep driver being made up of the drive element of the grid described in any one of claim 1-2,
It is characterized in that, including power supply and time-sequence control mode and row raster data model array, wherein power supply and sequential control
The output signal of molding block is high voltage VD, low-voltage VS, the first clock CK1, second clock CK2,
3rd clock CK3, triggering clock VI；
The row raster data model group that described row raster data model array is connected by N level is constituted, each row raster data model group by
First grid driver element, second grid driver element and the 3rd drive element of the grid are constituted, described first,
The control signal of second and third drive element of the grid all includes that the first clock input port IN_EN, second clock are defeated
Entrance OUT_EN, the 3rd clock input port CLR, the first power port VDD, second source mouth VSS, signal are adopted
Collection mouth Cin, the first delivery outlet COUT and the second delivery outlet GOUT.
Row gated sweep driver the most according to claim 3, it is characterised in that
In row raster data model array, the signal of the first grid driver element in first order row raster data model group is adopted
Collection mouth Cin is connected with the triggering clock VI of time-sequence control mode with power supply；
The signals collecting mouth Cin of first grid driver element and K-1 level row in K level row raster data model group
In raster data model group, the first delivery outlet COUT of the 3rd drive element of the grid is connected, second grid driver element
Signals collecting mouth Cin be connected with the first delivery outlet COUT of first grid driver element, the 3rd grid drives
The signals collecting mouth Cin of moving cell is connected with the first delivery outlet COUT of second grid driver element；
Every first clock input port IN_EN of first grid driver element of one-level row raster data model group, second
Clock input port OUT_EN, the 3rd clock input port CLR respectively with the first of power supply and time-sequence control mode
Clock CK1, second clock CK2, the 3rd clock CK3 are connected；
First clock input port IN_EN, the second clock input port OUT_EN of second grid driver element and
3rd clock input port CLR respectively with power supply and the second clock CK2 of time-sequence control mode, the 3rd clock
CK3, the first clock CK1 are connected；
First clock input port IN_EN, the second clock input port OUT_EN of the 3rd drive element of the grid and
3rd clock input port CLR respectively with power supply and the 3rd clock CK3 of time-sequence control mode, the first clock
CK1, second clock CK2 are connected.
Row gated sweep driver the most according to claim 3, it is characterised in that described first to
The high level of three clock signals is equal with high voltage VD, and the low level of told first the 3rd clock signal is with low
Voltage VS is equal.
6. according to the driving method of drive element of the grid described in any one of claim 1-2, it is characterised in that
First clock input port IN_EN, second clock input port OUT_EN and the 3rd clock input port CLR
The clock-pulse width inputted is identical, and dutycycle is 33.3%, and level pulse is from the first clock input port
IN_EN is successively to second clock input port OUT_EN, the flowing water of the 3rd clock input port CLR shifting flow
Line sequential；
Driving method specifically includes signals collecting memory phase, signal output stage and reset phase；
Signals collecting memory phase: flare IN_EN high input voltage when first, by the first transistor, second
Transistor is opened, signals collecting mouth Cin input high level signal, and be input to gather a signal storage point Q, the
In the grid of six transistors and the first storage electric capacity, the tenth transistor, the tenth two-transistor are opened, simultaneously
4th transistor, the 5th transistor are opened by input high level signal, and reverse output node QB is pulled low to
Low-voltage state, the 9th transistor, the 11st transistor and the 13rd transistor be turned off, the first delivery outlet
COUT, the second delivery outlet GOUT export positive voltage, but less than input high level VD.Additionally, the 7th is brilliant
Body pipe is also turned on, and electric current flows into from the first power port VDD, by the 7th transistor, second storage electric capacity,
Flow out through second source mouth VSS after 4th transistor, the 5th transistor and form loop, the second storage electric capacity quilt
Charging, now node N is high level, and output node QB is low level；Second clock mouth OUT_EN and
When the 3rd, flare CLR all inputs low-voltage.Subsequently, the first clock signal IN_EN becomes low-voltage, by
One transistor, transistor seconds turn off, signals collecting mouth Cin input low-voltage turn off the 4th transistor and,
5th transistor and the 7th transistor, signals collecting completes, and this stage continues 1/3 clock period time；
The signal output stage: second clock mouth OUT_EN high input voltage, owing to the bootstrapping of the first electric capacity is made
With, the high level of the level saltus step of signal memory node Q to about twice VD, the tenth transistor and the tenth
Two-transistor is fully opened, and the first delivery outlet COUT, the second delivery outlet GOUT output level are about VD
Driving signal；Meanwhile, the 8th transistor is opened, now the current potential of node N and the 9th transistor,
11 transistors and the 13rd transistor source potential are low level VS；3rd clock input port CLR simultaneously
And signals collecting mouth Cin input low level signal, the 3rd to the 5th transistor closedown, reverse output point QB phase
Quick condition is in for arbitrary power port, and due to the second storage electric capacity storage effect, the 9th transistor,
The gate-source voltage difference of the 11st transistor and the 13rd transistor is negative, and above-mentioned transistor is thoroughly closed,
Avoiding interference output signal, this stage continues 1/3 clock period time；
Reset phase: flare CLR input high level signal when the 3rd, third transistor is opened, the most defeated
Egress QB becomes high level, and the 9th transistor, the 11st transistor and the 13rd transistor are opened, and adopt
Collection signal storage point Q becomes low level, and the tenth transistor, the tenth two-transistor are turned off, the first delivery outlet
COUT and the second delivery outlet GOUT all exports low-voltage, and circuit resets complete, when this stage continues 1/3
Clock cycle time.
7., according to the driving method of row gated sweep driver described in any one of claim 3-5, its feature exists
In, the first clock CK1, second clock CK2, the 3rd clock CK3 pulse width identical with the cycle, account for
Empty ratio is 33.3%, and be level pulse from the first clock CK1, successively to second clock CK2, the 3rd time
The streamline sequential of clock CK3 cyclic shift；
When clock VI produces the level pulse identical for clock CK1 with first upon activation, row gated sweep drives
Device enters initial phase, and after 1/3 clock cycle T, first order drive element of the grid produces gate drive signal,
Drive element of the grid the most at different levels are driven by clock and produce gate drive signal step by step, when afterbody grid drives
While moving cell produces gate drive signal, trigger clock VI and also produce identical with this gate drive signal
Level pulse, row gated sweep driver enters duplication stages, and after 1/3 clock cycle T, first order grid drives
Moving cell second time produces gate drive signal, and row gated sweep drives process to terminate.
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| PCT/CN2016/109469 WO2017202005A1 (en) | 2016-05-25 | 2016-12-12 | Gate driving unit, row gate scanning driver and driving method thereof |
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