CN105843749A - NAND Flash fault-tolerance method based on FPGA (Field Programmable Gate Array) - Google Patents
NAND Flash fault-tolerance method based on FPGA (Field Programmable Gate Array) Download PDFInfo
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
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Abstract
The invention discloses a NAND Flash fault-tolerance method based on a FPGA (Field Programmable Gate Array). The NAND Flash fault-tolerance method comprises the following steps: carrying out Flash bad block detection, bad block management and dynamic table lookup. The bad block is detected through judging whether the state of a Flash write zone bit is the same with read-write contents or not. The addresses of detected good blocks and bad blocks are managed by a bad block management algorithm, and an address mapping table is established. The FPGA carries out write, read and erasure operations on the Flash through a dynamic table lookup way, and the accuracy and the efficiency of data access are greatly improved. The method can directly improve the space use ratio of the Flash, the integral performance and the processing speed of the Flash can obtain an important guarantee, and the method has a reference meaning for the application development of the new-generation large-volume NAND Flash.
Description
Technical field
The present invention relates to Flash fault-toleranr technique, particularly relate to a kind of NAND Flash fault-tolerance approach based on FPGA.
Background technology
Along with information technology ground development, digital product has become as the vital part of life.During people constantly pursue high-quality life, capacity and the process performance of the digital product such as smart mobile phone, digital camera, player need lifting badly.Meanwhile, storage industry is faced with the opportunity to develop brought by great demand.In the most civilian consumer electronics market, flash memory (Flash) plays dominant role in non-volatile memory medium.NOR Flash and NAND Flash two kinds can be divided into by the difference on logical architecture.NOR Flash occupies main status in market in early days, after technological innovation, NAND Flash emphasizes to reduce the cost of every bit, can easily be upgraded by interface as disk, have speed high, reliability is high, low in energy consumption, the advantages such as volume is little, generate heat less, antidetonation is strong, gradually replace NOR Flash, are increasingly becoming the main flow of memorizer.
Owing to the technique of NAND Flash is it cannot be guaranteed that the Memory Array of NAND keeps the reliable of performance in its life cycle, therefore can produce during appearing on the scene and using can not the invalid block of erasure error, the worst piece.The bad block existed during appearance cannot be used for storing data, identified by producer, and some position that the day after tomorrow increases, due to access times, the bad block caused can not overturn, make system become unstable, data in Flash are caused cannot normally to be read and write, the problem such as even cause that Flash scraps.Therefore, the key problem in technology during bad block management is always NAND Flash management and difficult point.By to the detection of bad block and management, it is possible not only to find bad block in the very first time, and can skip or replace bad block as required, and the bad block replaced is stored in reserved area, data safety can be ensured, it is to avoid the trouble that loss of data etc. are unnecessary.
Summary of the invention
Present invention aims to the deficiencies in the prior art, it is provided that a kind of NAND Flash fault-tolerance approach based on FPGA.
It is an object of the invention to be achieved through the following technical solutions: a kind of NAND Flash fault-tolerance approach based on FPGA, including the detection of Flash bad block, bad block management and On-line Timing Plan Selection.Write the state of flag bit and read-write by Flash content is the most identical and detect bad block.Utilize bad block management algorithm that good, the defect block addresses that detect are managed, and set up address mapping table.Flash is write by the way of On-line Timing Plan Selection, reads and wipe operation by FPGA, substantially increases the Accuracy and high efficiency of data access.
Further, described Flash bad block detection process is as follows:
(1) by FPGA, all pieces of Flash chip is carried out write operation by page address, once write one page.After one write cycle time terminates, by checking that write state flag bit judges whether to be write as merit, if continuous 3 times are not write as merit, then judge that current block is bad block；
(2) if writing successfully, then will write data and store to RAM.Read current block content, and the data of writing in RAM contrast, read for continuous 2 times and write content differs, then judge that current block is bad block；
(2) if writing successfully, read current block content, and the data of writing in RAM contrast, read for continuous 2 times and write content differs, then judge that current block is bad block；
Further, described bad block management process is as follows:
(1) first the good block every piece of Flash detected carries out erasing operation, and after erasing, all byte content are 0XFF.Then being marked at its page 1 all bytes write 0X0A, show that this block, for storage address mapping table, is designated as Block1, its block address is designated as address1；
(2) depositor of definition one 16, is designated as block_addr, for depositing the state of detection block.The page 2 of Block1 starts, and uses the mode storage address mapping table of each one block of bit labelling, and good block is designated as 1, and bad block is designated as 0；
(3) the BOB(beginning of block) detection after Block1, if block preferably, then
Block_addr [0]=1,
Otherwise,
Block_addr [0]=0.
Meanwhile, block_addr moves to left one, and definition register bit_counter, and record moves to left figure place；
(4), during by checking write state flag bit detection bad block, if current page meets write fail condition, then judge that current block is bad block, and skip the detection of continued page, directly start the detection of next block；
(5) as bit_counter=31, block_addr being written to first word of the page 2 of Block1, and Block1 column address adds 1, bit_counter resets.Meanwhile, definition register block_counter, record resets number of times；
(6) setting a total of N number of piece of Flash, maximum block address is designated as addr_max, if meeting
Block_counter ＞=(addr_max-address1)/16,
Then explanation detection completes, and address mapping table has been stored in Block1.
Further, described Flash is after setting up address mapping table, and On-line Timing Plan Selection process is as follows:
(1) read: perform read operation from the first of Flash BOB(beginning of block), if the page 1 reading block is all 0X0A, then judge that current block is address mapping table memory block.Read the address mapping table of page 2, and store to RAM, meanwhile, after block address, move to next block.Judge address mapping table by turn, if 1, read current block content, if 0, then skip current block.After position judges to terminate with block operations every time, address moves a unit the most afterwards, until performing to block address addr_max；
(2) erasing: perform read operation from the first of Flash BOB(beginning of block), if the page 1 reading block is all 0X0A, then judge that current block is address mapping table memory block.Erasing operation is performed, until performing to block address addr_max from next BOB(beginning of block)；
(3) dynamically update: when again performing write operation after erasing, first perform read operation from the first of Flash BOB(beginning of block), if the page 1 reading block is all 0X0A, then judge that current block is address mapping table memory block.Read the address mapping table of page 2, and store to RAM, meanwhile, after block address, move to next block.Judge address mapping table by turn, if 0, skip current block, if 1, write data at current block, perform detection operation simultaneously, if current block is detected as bad block, then update address mapping table, current record position is updated to 0, and skips current block.After position judges to terminate with block operations every time, address moves a unit the most afterwards, until performing to block address addr_max.
The invention have the advantages that: NAND Flash fault-tolerance approach based on FPGA, the detection of bad block and problem of management can be efficiently solved, thus improve Flash storage performance, extend its service life, ensure the data safety of user.The method includes the detection of Flash bad block, bad block management and On-line Timing Plan Selection.Write the state of flag bit and read-write by Flash content is the most identical and detect bad block.Utilize bad block management algorithm that good, the defect block addresses that detect are managed, and set up address mapping table.Flash is write by the way of On-line Timing Plan Selection, reads and wipe operation by FPGA, proposes practicable processing method for the deficiencies in the prior art, substantially increases the Accuracy and high efficiency of data access.In a word, by NAND Flash fault-tolerance approach, the bad block run into during using dynamically can be managed, dynamically update bad block information table, directly improve block space utilization ratio, make Flash overall performance and processing speed obtain important guarantee, the application development of a new generation Large Copacity NAND Flash is had reference significance.
Accompanying drawing explanation
Fig. 1 is Flash bad block overhaul flow chart；
Fig. 2 is Flash bad block management flow chart；
Fig. 3 is that address mapping table dynamically updates flow chart.
Detailed description of the invention
The invention will be further described with embodiment below in conjunction with the accompanying drawings.
As it is shown in figure 1, Flash bad block detection process is as follows:
(1) by FPGA, all pieces of Flash chip is carried out write operation by page address, once write one page.After one write cycle time terminates, by checking that write state flag bit judges whether to be write as merit, if continuous 3 times are not write as merit, then judge that current block is bad block；
(2) if writing successfully, then will write data and store to RAM.Read current block content, and the data of writing in RAM contrast, read for continuous 2 times and write content differs, then judge that current block is bad block；
As in figure 2 it is shown, bad block management process is as follows:
(1) first the good block every piece of Flash detected carries out erasing operation, and after erasing, all byte content are 0XFF.Then being marked at its page 1 all bytes write 0X0A, show that this block, for storage address mapping table, is designated as Block1, its block address is designated as address1；
(2) depositor of definition one 16, is designated as block_addr, for depositing the state of detection block.The page 2 of Block1 starts, and uses the mode storage address mapping table of each one block of bit labelling, and good block is designated as 1, and bad block is designated as 0；
(3) the BOB(beginning of block) detection after Block1, if block preferably, then
Block_addr [0]=1,
Otherwise,
Block_addr [0]=0.
Meanwhile, block_addr moves to left one, and definition register bit_counter, and record moves to left figure place；
(4), during by checking write state flag bit detection bad block, if current page meets write fail condition, then judge that current block is bad block, and skip the detection of continued page, directly start the detection of next block；
(5) as bit_counter=31, block_addr being written to first word of the page 2 of Block1, and Block1 column address adds 1, bit_counter resets.Meanwhile, definition register block_counter, record resets number of times；
(6) setting a total of N number of piece of Flash, maximum block address is designated as addr_max, if meeting
Block_counter ＞=(addr_max-address1)/16,
Then explanation detection completes, and address mapping table has been stored in Block1.
As it is shown on figure 3, Flash is after setting up address mapping table, On-line Timing Plan Selection process is as follows:
(1) read: perform read operation from the first of Flash BOB(beginning of block), if the page 1 reading block is all 0X0A, then judge that current block is address mapping table memory block.Read the address mapping table of page 2, and store to RAM, meanwhile, after block address, move to next block.Judge address mapping table by turn, if 1, read current block content, if 0, then skip current block.After position judges to terminate with block operations every time, address moves a unit the most afterwards, until performing to block address addr_max；
(2) erasing: perform read operation from the first of Flash BOB(beginning of block), if the page 1 reading block is all 0X0A, then judge that current block is address mapping table memory block.Erasing operation is performed, until performing to block address addr_max from next BOB(beginning of block)；
(3) dynamically update: when again performing write operation after erasing, first perform read operation from the first of Flash BOB(beginning of block), if the page 1 reading block is all 0X0A, then judge that current block is address mapping table memory block.Read the address mapping table of page 2, and store to RAM, meanwhile, after block address, move to next block.Judge address mapping table by turn, if 0, skip current block, if 1, write data at current block, perform detection operation simultaneously, if current block is detected as bad block, then update address mapping table, current record position is updated to 0, and skips current block.After position judges to terminate with block operations every time, address moves a unit the most afterwards, until performing to block address addr_max.
Claims (4)
1. a NAND Flash fault-tolerance approach based on FPGA, it is characterised in that include that Flash is bad
Block detection, bad block management and On-line Timing Plan Selection.The state being write flag bit by Flash is the most identical with read-write content
Detect bad block.Utilize bad block management algorithm that good, the defect block addresses that detect are managed, and set up ground
Location mapping table.Flash is write by the way of On-line Timing Plan Selection, reads and wipe operation by FPGA.
A kind of NAND Flash fault-tolerance approach based on FPGA the most according to claim 1, it is special
Levying and be, described Flash bad block detection process is as follows:
(1) by FPGA, all pieces of Flash chip is carried out write operation by page address, once write one page.One
After individual write cycle time terminates, by checking that write state flag bit judges whether to be write as merit, if continuous 3 times are not write
Success, then judge that current block is bad block；
(2) if writing successfully, then will write data and store to RAM.Read current block content, and in RAM
Data of writing contrast, continuous 2 times read and write content differ, then judge that current block is bad block.
A kind of NAND Flash fault-tolerance approach based on FPGA the most according to claim 1, it is special
Levying and be, described bad block management process is as follows:
(1) first the good block every piece of Flash detected carries out erasing operation, all byte content after erasing
It is 0XFF.Then it is marked at its page 1 all bytes write 0X0A, shows that this block is for depositing
Address mapping table, is designated as Block1, and its block address is designated as address1；
(2) depositor of definition one 16, is designated as block_addr, for depositing the state of detection block.
The page 2 of Block1 starts, and uses the mode storage address mapping table of each one block of bit labelling, and good block is remembered
Being 1, bad block is designated as 0；
(3) the BOB(beginning of block) detection after Block1, if block preferably, then
Block_addr [0]=1,
Otherwise,
Block_addr [0]=0.
Meanwhile, block_addr moves to left one, and definition register bit_counter, and record moves to left figure place；
(4) during by checking write state flag bit detection bad block, if current page meets write fail condition,
Then judge that current block is bad block, and skip the detection of continued page, directly start the detection of next block；
(5) as bit_counter=31, block_addr is written to first of page 2 of Block1
Word, and Block1 column address adds 1, and bit_counter resets.Meanwhile, definition register block_counter,
Record resets number of times；
(6) setting a total of N number of piece of Flash, maximum block address is designated as addr_max, if meeting
Block_counter ＞=(addr_max-address1)/16,
Then explanation detection completes, and address mapping table has been stored in Block1.
A kind of NAND Flash fault-tolerance approach based on FPGA the most according to claim 1, it is special
Levying and be, described Flash is after setting up address mapping table, and On-line Timing Plan Selection process is as follows:
(1) read: perform read operation from the first of Flash BOB(beginning of block), if the page 1 reading block is all
0X0A, then judge that current block is address mapping table memory block.Read the address mapping table of page 2, and store
To RAM, meanwhile, next block is moved to after block address.Judge address mapping table by turn, if 1, read and work as
Front piece of content, if 0, then skip current block.After position judges to terminate with block operations every time, address moves one the most afterwards
Individual unit, until performing to block address addr_max；
(2) erasing: perform read operation from the first of Flash BOB(beginning of block), if the page 1 reading block is all
0X0A, then judge that current block is address mapping table memory block.Erasing operation is performed from next BOB(beginning of block), until
Perform to block address addr_max；
(3) dynamically update: when again performing write operation after erasing, first from the first of Flash BOB(beginning of block)
Perform read operation, if the page 1 reading block is all 0X0A, then judge that current block is address mapping table storage
Block.Read the address mapping table of page 2, and store to RAM, meanwhile, after block address, move to next block.
Judge address mapping table by turn, if 0, skip current block, if 1, write data at current block, simultaneously
Perform detection operation, if current block is detected as bad block, then update address mapping table, current record position is updated
It is 0, and skips current block.After position judges to terminate with block operations every time, address moves a unit the most afterwards, until
Perform to block address addr_max.
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106527997A (en) * | 2016-11-25 | 2017-03-22 | 西安电子科技大学 | NAND flash bad block reutilization method and device based on sequence expansion |
| CN106648463A (en) * | 2016-12-21 | 2017-05-10 | 广州周立功单片机科技有限公司 | Nand Flash block management method and system |
| CN106844079A (en) * | 2016-12-28 | 2017-06-13 | 中国北方车辆研究所 | The FLASH bad block managements system and management method of a kind of armored vehicle |
| CN106909519A (en) * | 2017-02-24 | 2017-06-30 | 济南浪潮高新科技投资发展有限公司 | A kind of Nand Flash memory mapped systems based on FPGA |
| CN106920576A (en) * | 2017-03-22 | 2017-07-04 | 惠州佰维存储科技有限公司 | A kind of method and system of inspection Nand Flash mass |
| CN109358814A (en) * | 2018-10-17 | 2019-02-19 | 天津易众腾动力技术有限公司 | A kind of method of EEPROM storage |
| CN109545266A (en) * | 2018-11-13 | 2019-03-29 | 深圳忆联信息***有限公司 | A kind of solid state hard disk finds weak piece of method and its system |
| CN109634534A (en) * | 2019-01-02 | 2019-04-16 | 威胜集团有限公司 | The capacity method for rapidly judging of storage chip |
| CN109783411A (en) * | 2018-12-20 | 2019-05-21 | 成都旋极历通信息技术有限公司 | A kind of FLASH antenna array control method and controller based on FPGA |
| WO2019205444A1 (en) * | 2018-04-27 | 2019-10-31 | 江苏华存电子科技有限公司 | Bad block management method for increasing available capacity of storage device |
| CN112331252A (en) * | 2020-12-14 | 2021-02-05 | 深圳市芯天下技术有限公司 | Method and device for automatically marking bad blocks of Nand flash memory, storage medium and terminal |
| CN112764670A (en) * | 2019-11-04 | 2021-05-07 | 深圳宏芯宇电子股份有限公司 | Flash memory device and flash memory management method |
| CN114546292A (en) * | 2022-02-28 | 2022-05-27 | 深圳市风云实业有限公司 | Method and system for managing bad blocks of nand flash |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106527997A (en) * | 2016-11-25 | 2017-03-22 | 西安电子科技大学 | NAND flash bad block reutilization method and device based on sequence expansion |
| CN106648463A (en) * | 2016-12-21 | 2017-05-10 | 广州周立功单片机科技有限公司 | Nand Flash block management method and system |
| CN106648463B (en) * | 2016-12-21 | 2020-06-16 | 广州立功科技股份有限公司 | Nand Flash block management method and system |
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| CN106909519A (en) * | 2017-02-24 | 2017-06-30 | 济南浪潮高新科技投资发展有限公司 | A kind of Nand Flash memory mapped systems based on FPGA |
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| WO2019205444A1 (en) * | 2018-04-27 | 2019-10-31 | 江苏华存电子科技有限公司 | Bad block management method for increasing available capacity of storage device |
| CN109358814A (en) * | 2018-10-17 | 2019-02-19 | 天津易众腾动力技术有限公司 | A kind of method of EEPROM storage |
| CN109545266A (en) * | 2018-11-13 | 2019-03-29 | 深圳忆联信息***有限公司 | A kind of solid state hard disk finds weak piece of method and its system |
| CN109783411A (en) * | 2018-12-20 | 2019-05-21 | 成都旋极历通信息技术有限公司 | A kind of FLASH antenna array control method and controller based on FPGA |
| CN109783411B (en) * | 2018-12-20 | 2022-05-17 | 成都旋极历通信息技术有限公司 | FLASH array control method based on FPGA and controller |
| CN109634534A (en) * | 2019-01-02 | 2019-04-16 | 威胜集团有限公司 | The capacity method for rapidly judging of storage chip |
| CN112764670A (en) * | 2019-11-04 | 2021-05-07 | 深圳宏芯宇电子股份有限公司 | Flash memory device and flash memory management method |
| CN112331252A (en) * | 2020-12-14 | 2021-02-05 | 深圳市芯天下技术有限公司 | Method and device for automatically marking bad blocks of Nand flash memory, storage medium and terminal |
| CN114546292A (en) * | 2022-02-28 | 2022-05-27 | 深圳市风云实业有限公司 | Method and system for managing bad blocks of nand flash |
| CN114546292B (en) * | 2022-02-28 | 2023-12-15 | 深圳市风云实业有限公司 | Method and system for managing nand flash bad blocks |
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