CN105828084B

CN105828084B - HEVC (high efficiency video coding) inter-frame coding processing method and device

Info

Publication number: CN105828084B
Application number: CN201610192558.3A
Authority: CN
Inventors: 郭利财; 邓海波; 谷沉沉; 毛煦楠
Original assignee: Tencent Technology Shenzhen Co Ltd
Current assignee: Tencent Technology Shenzhen Co Ltd
Priority date: 2016-03-30
Filing date: 2016-03-30
Publication date: 2021-04-13
Anticipated expiration: 2036-03-30
Also published as: CN105828084A

Abstract

An HEVC interframe coding processing method is used for accelerating the judgment speed of a skip mode and improving the HEVC coding efficiency. In some possible embodiments of the invention, the method comprises: acquiring a predicted value and an original value of a current prediction unit PU; calculating the error square sum of the predicted value and the original value of the PU; and comparing the error square sum with a threshold value, and judging whether the prediction mode of the PU is a skip mode according to a comparison result. The embodiment of the invention also provides a corresponding device.

Description

HEVC (high efficiency video coding) inter-frame coding processing method and device

Technical Field

The invention relates to the technical field of video coding, in particular to a HEVC inter-frame coding processing method and device.

Background

High Efficiency Video Coding (HEVC) is a next generation new Video compression standard, and aims to improve Video compression Efficiency by more than 30% compared with existing h.264/AVC (Advanced Video Coding) High Profile (High end specification) so as to replace the h.264/AVC Coding standard.

CU (Coding Unit) is the most basic Unit of HEVC inter and intra Coding, and may be 64 × 64, 32 × 32, 16 × 16, and 8 × 8 in size, in units of pixels. Each CU may be divided into a plurality of PUs (Prediction units). A PU is a basic unit for intra prediction and inter prediction, and may range in size from 4 × 4 to 64 × 64, a PU may be square, e.g., 4 × 4, or rectangular, e.g., 4 × 8, etc.

In HEVC encoders, the decision to skip a mode inside a P frame (Prediction frame, inter coding) has a significant impact on the performance of the encoder. Once the prediction mode of the current PU is selected as the skip mode, further partitioning and motion search processes can be avoided. Determining whether the PU is in skip mode requires calculating the rate-distortion cost in skip mode and normal mode, respectively. The rate distortion cost of the common mode can be calculated only through a complete coding process, and the complete coding process is time-consuming, so that the decision speed of a skipped mode is reduced, and the HEVC coding efficiency is seriously affected.

Disclosure of Invention

The embodiment of the invention provides a HEVC inter-frame coding processing method and device, which are used for accelerating the judgment speed of a skip mode and improving the HEVC coding efficiency.

The invention provides an HEVC inter-frame coding processing method in a first aspect, which comprises the following steps: acquiring a predicted value and an original value of a current prediction unit PU; calculating the error square sum of the predicted value and the original value of the PU; and comparing the error square sum with a threshold value, and judging whether the prediction mode of the PU is a skip mode according to a comparison result.

The second aspect of the present invention provides an HEVC inter-frame coding processing apparatus, including: the first calculation module is used for acquiring a predicted value and an original value of a current prediction unit PU; calculating the error square sum of the predicted value and the original value of the PU; and the first processing module is used for comparing the error sum of squares with a threshold value and judging whether the prediction mode of the PU is a skip mode according to a comparison result.

A third aspect of the invention provides a computer device comprising a processor, a memory, a bus, and a communication interface; the memory is used for storing a program, the processor is connected with the memory through the bus, and when the computer device runs, the processor executes the program stored in the memory, so that the computer device executes the HEVC inter-frame coding processing method according to the first aspect.

A fourth aspect of the present invention provides a computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computer device comprising one or more processors, cause the computer device to perform the HEVC inter-frame coding processing method as recited in the first aspect.

From the above, in some possible embodiments of the present invention, the sum of the squares of the errors of the predicted value and the original value of the current PU is calculated; the sum of squared errors can be compared with a threshold, and whether the prediction mode of the PU is a skip mode is judged according to the comparison result, so that a complete coding process can be skipped over for part of PUs, the judgment speed for improving the skip mode can be reduced, and the improvement of the HEVC coding efficiency is facilitated.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the embodiments and the drawings used in the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a conventional PU prediction mode decision flow;

fig. 2 is a schematic flowchart of an HEVC inter-frame coding processing method according to an embodiment of the present invention;

fig. 3 is a schematic flowchart of an HEVC inter-frame coding processing method according to another embodiment of the present invention;

fig. 4 is a schematic structural diagram of an HEVC inter-frame coding processing apparatus according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a computer device according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," "third," and the like in the description and in the claims, and in the above-described drawings, are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

The technical scheme of the invention is applied to the technical field of video coding. The indexes for measuring the standard performance of video coding are mainly coding rate and coding distortion. The coding rate refers to coding information obtained by a residual error of a coding block through predictive coding, and then through transformation and quantization. Image distortion refers to the difference in the image of the reconstructed block and the original block. The number of coding bits is less, which is beneficial to storage or network transmission, but the reconstructed video coding distortion is larger; otherwise, the number of coded bits is increased. These two criteria are restrictive and contradictory.

In video coding, Rate-Distortion Optimization (RDO) techniques may be used to achieve a trade-off between bitrate and Distortion. RDO is a video coding technique for reducing the distortion of images at the smallest possible coding rate, so as to maximize the coding efficiency. The purpose of the RDO is: how to minimize the distortion of the reconstructed image at a certain bit rate; or to encode pictures with the smallest number of bits under conditions that allow for some distortion.

The next generation video compression standard HEVC includes many high complexity coding algorithms, and the coding efficiency is limited, so that it is a very realistic need to improve the HEVC video coding efficiency. In the HEVC Coding technique, each frame of image of a video is divided into CTUs (Coding tree units), which are basic units of HEVC Coding and similar to macroblocks (Macro blocks) in h.264/AVC, and the size of the CTUs may be from 16 × 16 to 64 × 64, in pixels. Each CTU may be one CU, or may be further divided into a plurality of CUs. A CU is the most basic unit of HEVC inter and intra coding and may be 64 × 64, 32 × 32, 16 × 16, and 8 × 8 in size, in pixels.

Each CU may in turn be divided into a plurality of PUs. The PU is a basic unit for intra prediction and inter prediction, and may have a size of 4 × 4 to 64 × 64, and the PU may have a square shape such as 4 × 4 or 8 × 4, or a rectangular shape such as 4 × 8 or 8 × 16.

In HEVC inter coding, or P-frame coding, a PU may be coded in skip mode, merge mode, and other modes. The present invention collectively refers to the merge mode and other modes as the normal mode. The skip mode is a mode in which only a skip flag and a reference index are transmitted, and a prediction mode, a partition size, a prediction direction, a motion vector difference, and residual information are not transmitted. Mode selection of an HEVC encoder may be selected according to a Rate-Distortion Cost (RDCost), which may be calculated by RDO.

As shown in fig. 1, the flow of the prediction mode decision of the PU is shown. Determining whether to select the skip mode for a PU, a specific decision process may include:

firstly, calculating a predicted value of a current PU, coding the PU according to a skip mode, and calculating a rate-distortion cost RDcost C0 of the skip mode;

then, a complete coding process is carried out according to the common mode, and the rate distortion cost RDcost C1 of the common mode is calculated;

if the cost RDCost C0 of the skip mode is smaller than the cost RDCost C1 of the normal mode, the prediction mode of the current PU is judged to be the skip mode, and if not, the prediction mode of the current PU is judged to be the normal mode.

As can be seen from the above, the rate-distortion cost RDCost C1 of the normal mode can be calculated only through a complete coding process, and the complete coding process is time-consuming, which results in a reduction in the decision speed of the skipped mode and a serious impact on the HEVC coding efficiency.

Therefore, the embodiment of the invention provides an HEVC inter-frame coding processing method and device, which are used for accelerating the judgment speed of a skip mode and improving the HEVC coding efficiency.

The following are detailed descriptions of the respective embodiments.

Referring to fig. 2, an embodiment of the present invention provides an HEVC inter-frame coding processing method.

The method provided by the embodiment of the invention is applied to the judgment process of the PU mode in HEVC inter-frame coding.

HEVC video coding may employ inter-frame prediction, i.e. each frame in a video stream does not need to be a complete image, because there is temporal correlation between the previous and subsequent pictures, and the subsequent picture can be predicted by adding a motion vector on the basis of the previous picture. In a typical IPB frame coding structure, only an I frame is a complete picture, a P frame is reference predicted on the basis of the I frame, and a B frame is bidirectional predicted, and also needs to reference the I frame or the P frame to construct a complete picture by calculating error information. As can be seen, video is not simply a continuous playback of graphics. The video has time correlation, so that the time correlation can be utilized to eliminate time redundant information and complete interframe coding.

PU is a basic unit for intra prediction and inter prediction, and can range from 4 × 4 to 64 × 64, and in h.265, in addition to a symmetric mode (symmetric motion) of 2N × 2N, N × N, 2N × N, and N × 2N similar to the h.264 division method, h.265 provides an Asymmetric Mode (AMP) including 2N × nU, 2N × nD, nL × 2N, and nR × 2N, where the capital english alphabet represents the position of a shorter-side division block, where N is a power index of 2. Thus, the shape of the PU may be a square block, e.g., 4 × 4, or a rectangular block, e.g., 4 × 8, etc.

In HEVC encoders, the decision to skip a mode inside a P frame has a significant impact on the performance of the encoder. Once the prediction mode of the current PU is selected as the skip mode, further partitioning and motion search processes can be avoided.

Referring to fig. 2, an HEVC inter-frame coding processing method provided by an embodiment of the present invention is used for determining a PU mode, and the method may include:

201. acquiring a predicted value and an original value of a current prediction unit PU;

a PU in a P frame may be predicted with reference to an I frame, and its original and predicted values may be obtained for a given current PU. Wherein, the original value is the content to be coded by the current PU, and refers to the value of the input image at the current PU position; the predicted value is a value calculated by interpolation from the inside of a reference frame after a motion vector is given; the reference frame is the reconstructed value of the already encoded frame.

It should be noted that, in some embodiments of the present invention, the image values of each frame may be represented by a YUV color coding method, and the YUV signals include a luminance signal Y and two color difference signals B-Y (i.e., U) and R-Y (i.e., V). The original value and the predicted value may refer to YUV values of the image. Of course, other color coding methods may be used in other embodiments, which are not limited herein.

202. Calculating the error square sum of the predicted value and the original value of the PU;

in this step, the sum of the squares of errors (SSE) of the predicted and original values of the PU is calculated. The sum of squared errors is the sum of the squares of the deviations of the measured values from the true values under the same conditions. The SSE can be used to indicate the magnitude of the deviation of the predicted value from the true value, with smaller SSEs indicating closer predicted values to the original values.

Suppose a PU includes m x n pixels, m and n are positive integers, where the predicted value of the i x j pixel is a_ijExpressed as the original value b_ijThat is, i is a positive integer not greater than m, and j is a positive integer not greater than n, the sum of the square of the error between the predicted value and the original value of the PU can be expressed by the following formula:

203. and comparing the error square sum with a threshold value, and judging whether the prediction mode of the PU is a skip mode according to a comparison result.

In the step, firstly, the error sum of squares is used as the decision criterion of the PU mode, and whether the skipping mode is selected or not is judged according to the comparison result by comparing the error sum of squares with the threshold value. If the comparison shows that the deviation of the predicted value from the true value is small, the skip mode may be selected.

Specifically, it may be determined whether the sum of squared errors is smaller than a preset Threshold, and if so, the SSE is considered to be small enough, and the predicted value is close to the original value, so that the skip mode may be selected, and the mode decision selection process of the PU is ended.

In some embodiments, the Threshold corresponding to the PU may be calculated in advance based on the size of the PU and a Quantization Parameter (QP). QP is a quantization parameter in HEVC, the legal range is 0-51, the larger the value the higher the compression ratio, the more severe the distortion. The Threshold is a function of PU and QP, and may be expressed as Threshold ═ f (QP, PU).

In one specific implementation, Threshold may be calculated using the following formula:

where N is the width of the PU.

In this embodiment of the present invention, if the sum of squared errors SSE is not less than the Threshold, the following decision process may be continuously performed:

s1, calculating a first rate-distortion cost of a skip mode of the PU, encoding the CU according to a common mode, and calculating a second rate-distortion cost of the common mode;

the first rate-distortion cost may be represented by RDCost C0 and the second rate-distortion cost may be represented by RDCost C1. Wherein, the PU may be coded in a skip mode to calculate RDCost C0; and coding the PU according to a common mode, and calculating to obtain RDcost C1. Note that the normal mode is an abbreviation of a normal inter mode.

S2, comparing the first rate distortion cost with the second rate distortion cost, and judging whether the prediction mode of the PU is a skip mode according to the comparison result.

Specifically, step S2 may include: judging whether the first rate distortion cost is smaller than the second rate distortion cost; if so, judging that the prediction mode of the PU is a skip mode, otherwise, judging that the prediction mode of the PU is a common mode.

In this step, if the cost RDCost C0 of the skip mode is smaller than the cost RDCost C1 of the normal mode, it is determined that the prediction mode of the current PU is the skip mode, otherwise, the prediction mode is the normal mode.

The method comprises two stages, wherein the first stage adopts the error Sum of Squares (SSE) as a judgment criterion to judge whether a skip mode is adopted, if the skip mode is selected, the whole judgment process is ended, otherwise, the second stage is entered; and in the second stage, the rate distortion cost RDcost is adopted as a judgment criterion to judge whether a skip mode is adopted or not, and if the rate distortion cost in which prediction mode is small, which prediction mode is adopted.

It is understood that the above-described aspects of the embodiments of the present invention can be implemented in various devices, such as a personal computer, a tablet computer, a mobile phone, a server, a television, a game console, and the like.

In order to better understand the technical solutions provided by the embodiments of the present invention, the following description is given by taking an implementation mode in a specific scenario as an example.

Referring to fig. 3, another HEVC inter-frame coding processing method according to an embodiment of the present invention may include:

301. calculating a predicted value of the current PU;

302. calculating the error Sum of Squares (SSE) of the predicted value and the original value of the PU;

303. judging whether the error sum of squares SSE is smaller than a Threshold, if so, entering a step 308, otherwise, entering a step 304;

304. calculating a first rate-distortion cost RDcost C0 of the skip mode;

305. coding according to a common mode;

306. calculating a second rate-distortion cost RDcost C1 of the common mode;

307. judging whether RDCost C0< RDCost C1 is true, if yes, entering the step 308, otherwise, entering the step 309;

308. judging the current PU as a skipping mode;

309. and judging the current PU to be in a common mode.

From the above, if the sum of squared errors SSE is smaller than the Threshold, then SSE is considered to be small enough, and the predicted value is close enough to the original value, so that the skip mode can be selected, and the mode decision selection process of the PU is ended. Similarly, if RDCost C0 is smaller than RDCost C1, the prediction value is considered to be close enough to the original value, and the prediction mode of the current PU can be determined to be the skip mode.

In the HEVC inter-frame coding process flow, the logic flow of the PU mode decision is introduced. Compared with the prior art, the method calculates the error square sum of the predicted value and the original value of the PU before calculating the rate distortion cost of the skip mode and the normal mode, directly judges the prediction mode of the PU as the skip mode when the error square sum is smaller than a threshold value, does not calculate the rate distortion cost of the skip mode and the normal mode, and can greatly improve the processing speed of inter-frame coding because the calculation of the rate distortion cost is skipped and the PU does not need to be coded.

In this document, the error sum of squares and the rate-distortion cost RDCost are used as the decision criteria, but it should be noted that the rate-distortion cost may be replaced by other similar metrics.

From the above, in some possible embodiments of the present invention, the prediction value of the current PU is calculated; and calculating the sum of squares of errors of the predicted value and the original value of the PU; the sum of squared errors can be compared with a threshold, and whether the prediction mode of the PU is a skip mode is judged according to the comparison result, so that a complete coding process can be skipped over for part of PUs, the judgment speed for improving the skip mode can be reduced, and the improvement of the HEVC coding efficiency is facilitated.

In order to better implement the above-mentioned aspects of the embodiments of the present invention, the following also provides related devices for implementing the above-mentioned aspects cooperatively.

Referring to fig. 4, an embodiment of the invention provides an HEVC inter-frame coding processing apparatus 400.

The method provided by the embodiment of the invention is applied to an HEVC encoder.

When the HEVC encoder performs video coding, inter prediction may be used, that is, each frame in a video stream does not need to be a complete image, because there is temporal correlation between previous and subsequent pictures, and a subsequent picture may be predicted by adding a motion vector on the basis of the previous picture. In a typical IPB frame coding structure, only an I frame is a complete picture, a P frame is reference predicted on the basis of the I frame, and a B frame is bidirectional predicted, and also needs to reference the I frame or the P frame to construct a complete picture by calculating error information. As can be seen, video is not simply a continuous playback of graphics. The video has time correlation, so that the time correlation can be utilized to eliminate time redundant information and complete interframe coding.

PU is a basic unit for intra prediction and inter prediction, and can range from 4 × 4 to 64 × 64, and in h.265, in addition to a symmetric mode (symmetric motion) of 2N × 2N, N × N, 2N × N, and N × 2N similar to the h.264 division method, h.265 provides an Asymmetric Mode (AMP) including 2N × nU, 2N × nD, nL × 2N, and nR × 2N, where the capital english alphabet represents the position of a shorter-side division block, where N is a power index of 2. Thus, the shape of a PU may be a square block, e.g., 4 × 4, or a rectangular block, e.g., 4 × 8.

As shown in fig. 4, an HEVC inter-coding processing device 400 according to an embodiment of the present invention may include:

a first calculating module 401, configured to calculate a prediction value of a current prediction unit PU; calculating the error square sum of the predicted value and the original value of the PU;

a first processing module 402, configured to compare the sum of squared errors with a threshold, and determine whether the prediction mode of the PU is a skip mode according to a comparison result.

In some embodiments of the present invention, the first processing module 402 is specifically configured to determine whether the sum of squared errors is smaller than the threshold, and if so, determine that the prediction mode of the PU is a skip mode.

In some embodiments of the invention, the apparatus 400 further comprises:

a second calculating module 403, configured to calculate a first rate-distortion cost of the skip mode of the PU if the first processing module determines that the sum of squared errors is not smaller than the threshold, and calculate a second rate-distortion cost of the normal mode by encoding the CU according to the normal mode;

the second processing module 404 is further configured to compare the first rate-distortion cost with the second rate-distortion cost, and determine whether the prediction mode of the PU is a skip mode according to a comparison result.

In some embodiments of the present invention, the second processing module 404 is specifically configured to determine whether the first rate-distortion cost is smaller than the second rate-distortion cost; if so, judging that the prediction mode of the PU is a skip mode, otherwise, judging that the prediction mode of the PU is a common mode.

In some embodiments of the invention, the apparatus 400 further comprises:

a third calculation module 405, configured to calculate a threshold corresponding to the PU according to the size of the PU and a quantization parameter QP.

The HEVC inter-frame coding processing apparatus according to the embodiment of the present invention may be, for example, a server, a personal computer, a tablet computer, a mobile phone, a television, a game console, and other devices.

It can be understood that the functions of each functional module of the HEVC inter-frame coding processing apparatus according to the embodiments of the present invention can be specifically implemented according to the method in the above method embodiments, and the specific implementation process thereof can refer to the relevant description in the above method embodiments, and is not described herein again.

Referring to fig. 5, an embodiment of the present invention further provides a computer apparatus 500, which may include:

a processor 501, a memory 502, a bus 503, and a communication interface 504; the memory 502 is used for storing a program 505, the processor 501 is connected to the memory 502 through the bus 503, when the computer device 500 runs, the processor 501 executes the program 505 stored in the memory 502, so that the computer device 500 executes the HEVC inter-frame coding processing method according to the above method embodiment.

The computer device 500 may be a micro-processing computer. Such as: the computer device 500 may be one of a general-purpose computer, a server, a personal computer, a mobile phone terminal, a tablet computer, a television, a game machine, and the like.

The bus 503 may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into one or more of an address bus, a data bus, and a control bus. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.

The memory 502 is used to store program code, which includes computer operating instructions. The memory 502 may comprise a high-speed ram (ramdom Access memory) memory. Optionally, the memory 502 may further include a non-volatile memory (non-volatile memory). The memory 502 may comprise disk storage, for example.

The processor 501 may be a Central Processing Unit (CPU), or the processor 501 may be an Application Specific Integrated Circuit (ASIC), or the processor 501 may be one or more Integrated circuits configured to implement embodiments of the present invention.

The processor 501 is configured to perform the following steps: acquiring a predicted value and an original value of a current prediction unit PU; calculating the error square sum of the predicted value and the original value of the PU; and comparing the error square sum with a threshold value, and judging whether the prediction mode of the PU is a skip mode according to a comparison result.

Optionally, the comparing, by the processor 501, the sum of squared errors with a threshold, and determining whether the prediction mode of the PU is a skip mode according to the comparison result may include: and judging whether the error sum of squares is smaller than the threshold value, if so, judging that the prediction mode of the PU is a skip mode.

Optionally, after the processor 501 performs the determination whether the sum of squared errors is smaller than the threshold, the following steps may be further performed: if the sum of squared errors is not smaller than the threshold, calculating a first rate-distortion cost of a skip mode of the PU, and encoding the CU according to a common mode to calculate a second rate-distortion cost of the common mode; and comparing the first rate distortion cost with the second rate distortion cost, and judging whether the prediction mode of the PU is a skip mode according to a comparison result.

Optionally, the comparing, by the processor 501, the first rate-distortion cost with the second rate-distortion cost, and determining whether the prediction mode of the PU is the skip mode according to the comparison result may include: judging whether the first rate distortion cost is smaller than the second rate distortion cost; if so, judging that the prediction mode of the PU is a skip mode, otherwise, judging that the prediction mode of the PU is a common mode.

Optionally, the processor 501 is further configured to perform the following steps: prior to comparing the sum of squared errors to a threshold, a threshold corresponding to the PU is calculated from the size of the PU and a quantization parameter, QP.

It can be understood that the functions of the computer device 500 according to the embodiment of the present invention may be specifically implemented according to the method in the foregoing method embodiment, and the specific implementation process may refer to the description related to the foregoing method embodiment, which is not described herein again.

Embodiments also provide a computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computer device comprising one or more processors, cause the computer device to perform the HEVC inter-frame coding processing method as described in the above method embodiments.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The HEVC inter-frame coding processing method and apparatus provided by the embodiments of the present invention are described in detail above, and a specific example is applied in the present disclosure to explain the principle and the embodiments of the present invention, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A High Efficiency Video Coding (HEVC) inter-frame coding processing method is characterized by comprising the following steps:

acquiring a predicted value and an original value of a current prediction unit PU; wherein, the original value is the content to be coded by the PU at present, and refers to the value of the input image at the PU position at present; the predicted value is a value calculated by interpolation from the reference frame after the motion vector is given; the reference frame is a reconstructed value of the already encoded frame;

calculating the error square sum of the predicted value and the original value of the PU;

and judging whether the error sum of squares is smaller than a threshold value, if so, judging that the prediction mode of the PU is a skipping mode.

2. The method of claim 1, wherein after determining whether the sum of squared errors is less than the threshold, further comprising:

if the error square sum is not less than the threshold value, calculating a first rate distortion cost of a skip mode of the PU, and encoding the PU according to a common mode to calculate a second rate distortion cost of the common mode;

and comparing the first rate distortion cost with the second rate distortion cost, and judging whether the prediction mode of the PU is a skip mode according to a comparison result.

3. The method of claim 2, wherein comparing the first rate-distortion cost with the second rate-distortion cost, and wherein determining whether the prediction mode of the PU is the skip mode according to the comparison comprises:

judging whether the first rate distortion cost is smaller than the second rate distortion cost;

if so, judging that the prediction mode of the PU is a skip mode, otherwise, judging that the prediction mode of the PU is a common mode.

4. The method according to any one of claims 1 to 3, wherein before said determining whether the sum of squared errors is less than a threshold, further comprising;

calculating a threshold corresponding to the PU according to the size of the PU and a quantization parameter QP.

5. An apparatus for HEVC inter-frame coding, comprising:

the first calculation module is used for acquiring a predicted value and an original value of a current prediction unit PU; calculating the error square sum of the predicted value and the original value of the PU; wherein, the original value is the content to be coded by the PU at present, and refers to the value of the input image at the PU position at present; the predicted value is a value calculated by interpolation from the reference frame after the motion vector is given; the reference frame is a reconstructed value of the already encoded frame;

and the first processing module is used for judging whether the error sum of squares is smaller than the threshold value, and if so, judging that the prediction mode of the PU is a skip mode.

6. The apparatus of claim 5, further comprising:

a second calculating module, configured to calculate a first rate-distortion cost of the skip mode of the PU if the first processing module determines that the sum of squared errors is not smaller than the threshold, and calculate a second rate-distortion cost of the normal mode by encoding the PU according to the normal mode;

and the second processing module is further configured to compare the first rate-distortion cost with the second rate-distortion cost, and determine whether the prediction mode of the PU is a skip mode according to a comparison result.

7. The apparatus of claim 6,

the second processing module is specifically configured to determine whether the first rate-distortion cost is smaller than the second rate-distortion cost; if so, judging that the prediction mode of the PU is a skip mode, otherwise, judging that the prediction mode of the PU is a common mode.

8. The apparatus of any of claims 5 to 7, further comprising:

a third calculation module to calculate a threshold corresponding to the PU according to the size of the PU and a quantization parameter QP.

9. A storage medium, wherein a program is stored in the storage medium; when executed, the program implements a High Efficiency Video Coding (HEVC) inter-frame coding processing method as recited in any one of claims 1-4.

10. A computer device comprising a processor, a memory, a bus, and a communication interface; the memory is used for storing a program, the processor is connected with the memory through the bus, and when the computer device runs, the processor executes the program stored in the memory to enable the computer device to execute the High Efficiency Video Coding (HEVC) inter-frame coding processing method as set forth in any one of claims 1-4.