CN105826333B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN105826333B CN105826333B CN201510012082.6A CN201510012082A CN105826333B CN 105826333 B CN105826333 B CN 105826333B CN 201510012082 A CN201510012082 A CN 201510012082A CN 105826333 B CN105826333 B CN 105826333B
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Abstract
The present invention provides a kind of forming method of semiconductor structure, comprising: provides substrate；Buffer layer, the first insulating layer and hard mask layer are sequentially formed over the substrate；Using the hard mask layer as exposure mask, first insulating layer, buffer layer and substrate are etched, forms groove in the substrate, buffer layer, the first insulating layer and hard mask layer；Electrode material layer is filled in the groove, until covering the hard mask layer surface；Chemical mechanical grinding is carried out to the electrode material layer and hard mask layer, the electrode material layer in removal and hard mask layer, remaining electrode material layer in the grooves forms electrode layer.The present invention first fills electrode material layer in the groove, then carries out chemical mechanical grinding to electrode material layer and hard mask layer.Chemical mechanical grinding substantially will not impact the buffer layer.After forming the electrode layer, buffer layer still keeps preferable pattern, and the present invention is made to be formed by semiconductor capacitor with preferable performance.
Description
Technical field
The present invention relates to semiconductor fields, and in particular to a kind of forming method of semiconductor structure.
Background technique
Cmos image sensor is semiconductor transducer common currently on the market, be widely used in mobile phone, tablet computer,
The fields such as fingerprint recognition.Have become the hot spot of this field research using 3D IC technology production cmos image sensor.Using 3D
IC technology makes cmos image sensor, and semiconductor capacitor is needed to form in bottom wafers.Usual semiconductor capacitor
Electrode plate is both formed in the deep trench in substrate.
Fig. 1 and Fig. 2 are please referred to, is a kind of schematic diagram of semiconductor capacitor production method of the prior art.Referring initially to figure
1, wherein substrate 01 is the active substrates after overdoping, and buffer layer 02, insulating layer 03 are formed on substrate 01 and is covered firmly
Film layer 04.The insulating layer 03 is used to protect the electrode plate in substrate 01 and substrate 01, and makes in substrate 01 and substrate 01
Electrode plate and substrate 01 on device isolation, the buffer layer 02 is for combination between reinforced insulation layer 03 and substrate 01
Property, with the hard mask layer 04 for exposure mask, etches the insulating layer 03, buffer layer 02 and substrate 01, the insulating layer 03,
Groove 05 is formed in buffer layer 02 and substrate 01.The groove is for filling electrode material, to form electrode plate.
Need to remove the hard mask layer 04 after forming groove 05 with reference to Fig. 2, the usual hard mask layer 04 and institute
Stating buffer layer 02 is that silica material is constituted.As shown in Fig. 2, the prior art often removes hard mask layer 04 with wet etching, with
Ensure to be removed clean in the hard mask layer 04 at the uneven place in 03 upper surface of insulating layer.But in the mistake of removal hard mask layer 04
Cheng Zhong, the groove 05 expose the side wall of buffer layer 02, and the buffer layer 02 is also easy to be etched, so that the side wall of groove 05
Form the notch as shown in circle.It is formed after electrode layer in the groove 05, also forms electrode layer in the notch, make
Electrode layer generates rough defect in gap position, may influence the capacitance between electrode plate, or even cause electrode plate
Open circuit, while the associativity between substrate 01 and insulating layer 03 may also be reduced, semiconductor capacitor is made to generate defect.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of semiconductor structure, improves and buffers in semiconductor capacitor
The pattern of layer, and then improve the performance of semiconductor capacitor.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising:
Substrate is provided；
Buffer layer, the first insulating layer and hard mask layer are sequentially formed over the substrate；
Using the hard mask layer as exposure mask, first insulating layer, buffer layer and substrate are etched, in the substrate, buffering
Groove is formed in layer, the first insulating layer and hard mask layer；
Electrode material layer is filled in the groove, until covering the hard mask layer surface；
Chemical mechanical grinding is carried out to the electrode material layer and hard mask layer, removes the electrode material on hard mask layer
Layer, remaining electrode material layer in the grooves are used to form electrode layer.
It optionally, include: using KOH or NH in the step of chemical mechanical grinding4OH is as lapping liquid.
Optionally, in the step of chemical mechanical grinding, the revolving speed of grinding head is at 60 rpms or more.
Optionally, chemical mechanical grinding also removes the hard mask layer of segment thickness, and the forming method is ground in chemical machinery
Mill is after the meeting further include: removes remaining hard mask layer by dry etching.
Optionally, the semiconductor structure is used to form capacitor, after providing substrate, is formed over the substrate slow
It rushes before layer, the substrate is doped, the partial region of the substrate is made to form doped region；
In the step of forming groove in the substrate, buffer layer, the first insulating layer and hard mask layer, the groove position
In the doped region of the substrate.
Optionally, in the step of forming hard mask layer on the first insulating layer, dew is formed in the hard mask layer
The opening of first insulating layer out；
Using the hard mask layer as exposure mask, first insulating layer, buffer layer and substrate are etched, in the substrate, is delayed
It rushes in layer, the first insulating layer and hard mask layer in the step of forming groove, etches the first insulating layer of the opening exposing, delays
Rush layer and substrate.
Optionally, it is formed after groove in the substrate, buffer layer, the first insulating layer and hard mask layer, described
Before filling electrode material layer in groove, the forming method further include:
Second insulating layer is formed on surface and the hard mask layer in the groove；
The step of electrode material layer is filled in the groove includes: that electricity is filled in the groove for being formed with second insulating layer
Pole material layer.
Optionally, the second insulating layer includes: the silicon oxide layer and silicon nitride layer sequentially formed.
Optionally, the material of the buffer layer is silica.
Optionally, the thickness of the buffer layer is in the range of 25 to 150 angstroms.
Optionally, the material of the hard mask layer is silica.
Optionally, the thickness of the hard mask layer is in the range of 7000 to 17000 angstroms.
Optionally, the material of the electrode layer is polysilicon.
Optionally, the depth of the groove is in the range of 5.7 microns to 9 microns.
Optionally, first insulating layer, buffer layer and substrate are etched, the step of to form groove in, etch described the
The method of one insulating layer, buffer layer and substrate is dry etch process.
Compared with prior art, technical solution of the present invention has the advantage that the present invention successively shape over the substrate
At buffer layer, the first insulating layer and hard mask layer；Using the hard mask layer as exposure mask, first insulating layer, buffering are etched
Layer and substrate form groove in the substrate, buffer layer, the first insulating layer and hard mask layer, fill electricity in the groove
After the material layer of pole, chemical mechanical grinding is carried out to the hard mask layer and electrode material layer.In the process of chemical mechanical grinding
In, there is the first insulating layer as blocking between buffer layer and the hard mask layer, the top of buffer layer and side wall are respectively first
Under the covering of insulating layer and electrode material layer, chemical mechanical grinding substantially will not impact the buffer layer.Forming institute
After stating electrode layer, buffer layer still keeps preferable pattern, and therefore, the associativity between substrate and the first insulating layer is preferable,
And the electrode layer will not generate rough defect near buffer layer, this sample embodiment is formed by semi-conductor electricity
Container has preferable performance.
Detailed description of the invention
Fig. 1 to Fig. 2 is a kind of schematic diagram of semiconductor capacitor production method of the prior art；
Fig. 3 to Figure 11 is the schematic diagram of one embodiment of forming method of semiconductor structure of the present invention.
Specific embodiment
In prior art semiconductor capacitor production method, remove hard mask layer the step of be easy to damage buffer layer, reduce
The performance of semiconductor capacitor.
In order to solve the above-mentioned technical problem, the present invention proposes a kind of forming method of semiconductor structure, comprising: provides lining
Bottom；Buffer layer, the first insulating layer and hard mask layer are sequentially formed over the substrate；Using the hard mask layer as exposure mask, carve
First insulating layer, buffer layer and substrate are lost, is formed in the substrate, buffer layer, the first insulating layer and hard mask layer
Groove；Electrode material layer is filled in the groove, until covering the hard mask layer surface；It covers to the electrode material layer and firmly
Film layer carries out chemical mechanical grinding, removes the electrode material layer on hard mask layer, remaining electrode material layer in the grooves
It is used to form electrode layer.
The present invention first fills electrode material layer in the groove, until covering the hard mask layer surface；To the electrode
Material layer and hard mask layer carry out chemical mechanical grinding, are carrying out chemical mechanical grinding to the electrode material layer and hard mask layer
During, under the covering of electrode material layer and the first insulating layer, chemical mechanical grinding is basic for the side wall of buffer layer and top
The buffer layer will not be impacted.After forming the electrode layer, buffer layer still keeps preferable pattern, therefore,
Associativity between substrate and the first insulating layer is preferable, also, the electrode layer will not generate lacking for protrusion near buffer layer
It falls into, this sample embodiment is formed by semiconductor capacitor with preferable performance.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
With reference to Fig. 3 to Figure 11, the schematic diagram of one embodiment of forming method of semiconductor structure is shown.
With reference to Fig. 3, substrate 100 is provided.
In the present embodiment, the substrate 100 is located on wafer, and the substrate 100 is monocrystalline substrate, in other implementations
In example, the substrate can also partly lead for multicrystalline silicon substrate, amorphous silicon substrate, germanium silicon substrate or silicon-on-insulator substrate etc. are other
Body substrate does not do any restrictions to this present invention.
In the present embodiment, multiple shallow trench are formed in the substrate 100 after substrate 100 is provided with reference to Fig. 4
Then isolation structure 101 is doped the multiple regions of substrate 100 for substrate 100 to be separated into multiple regions, is serving as a contrast
Multiple doped regions are formed in bottom 100.It is a doped region between two adjacent fleet plough groove isolation structures 101, is used as semiconductor
The plate of capacitor.But whether the present invention is to forming the fleet plough groove isolation structure with no restrictions.
With reference to Fig. 4, buffer layer 102, the first insulating layer 103 and hard mask layer are sequentially formed on the substrate 100
104。
First insulating layer 103 is used for substrate 100 and other semiconductor structures of 103 top of the first insulating layer is exhausted
Edge, the doped region to guarantee as semiconductor capacitor plate are less likely to occur to leak electricity.
The buffer layer 102 is used to reinforce the binding force between the first insulating layer 103 and substrate 100, makes the first insulating layer
103 and its other semiconductor structures of top be stably formed on substrate 100.In addition, the first insulating layer 103 usually have compared with
Big stress, first insulating layer 103 can also be buffered by forming buffer layer 102 between the first insulating layer 103 and substrate 100
With the stress between substrate 100, to protect substrate 100.
It should be noted that being formed by the thickness of semiconductor structure if the thickness of the buffer layer 102 is excessive
Can increase accordingly, if the thickness of the buffer layer 102 is too small, be difficult to play reinforcing line bottom 100 and the first insulating layer 103 it
Between binding force effect.Therefore, in the present embodiment, the thickness of the buffer layer 102 is in the range of 25 to 150 angstroms.
The hard mask layer 104 is used as the exposure mask for etching first insulating layer 103, buffer layer 102 and substrate 100,
The depth of groove formed in first insulating layer 103, buffer layer 102 and substrate 100 is larger, it is therefore desirable to etching speed
The slower hard mask layer 104 of the etching speed of counter substrate 100 is used as exposure mask, in addition, being used as exposure mask energy using hard mask layer 104
It is enough to improve the pattern for being formed by recess sidewall.
If the thickness of the hard mask layer 104 is excessive, the difficulty of subsequent removal hard mask layer 104 is larger, if institute
The thickness for stating hard mask layer 104 is too small, then predetermined value may have not been reached yet in depth of groove when subsequent etching forms groove
When, the depleted progress for influencing etching process of hard mask layer 104.Therefore, in the present embodiment, the hard mask layer 104
Thickness is in the range of 7000 to 17000 angstroms.
In the present embodiment, the buffer layer 102, the first insulating layer 103 and hard are formed using chemical vapour deposition technique
Mask layer 104.The material of the buffer layer 102 is silica, and the material of first insulating layer 103 is silicon nitride, described hard
The material of mask layer 104 is silica.But the present invention is to the buffer layer 102, the first insulating layer 103 and hard mask layer
104 specific material is with no restrictions.
It is exposure mask with the hard mask layer 104 after the etching in conjunction with reference Fig. 5, Fig. 6, Fig. 7, etches first insulation
Layer 103, buffer layer 102 and substrate 100, in the substrate 100, buffer layer 102, the first insulating layer 103 and hard mask layer 104
Middle formation groove 107.
It should be noted that the groove 107 is used to form the electrode layer of semiconductor capacitor, the electrode layer be used for
Doped region in substrate 100 respectively constitutes two electrodes of semiconductor capacitor, therefore the groove 107 is formed in the substrate
In 100 doped region.
In the present embodiment, referring initially to Fig. 5, polysilicon layer 105 and photoresist are sequentially formed on the hard mask layer 104
Layer 106, with the figure of respective slot shape on the photoresist layer 106.
The polysilicon layer 105 is used as pattern transfer to the mask layer of hard mask layer 104, can be improved the essence of pattern transfer
Degree.But whether the present invention is to forming the polysilicon layer 105 with no restrictions.
It is exposure mask with the photoresist layer 106 with reference to Fig. 6, etches the polysilicon layer 105, by the respective slot shape
Pattern transfer to polysilicon layer 105 on, then with the polysilicon layer 105 be exposure mask, the hard mask layer 104 etched, by institute
It states in the pattern transfer to hard mask layer 104 of respective slot shape.
It is exposure mask with the hard mask layer 104 in conjunction with reference Fig. 6, Fig. 7, etches first insulating layer 103, buffer layer
102 and substrate 100, groove is formed in the substrate 100, buffer layer 102, the first insulating layer 103 and hard mask layer 104
107.During etching first insulating layer 103, buffer layer 102 and substrate 100, polysilicon layer 105 is etched completely,
Hard mask layer 104, which is also etched, gets rid of certain thickness.
In the present embodiment, the method for etching first insulating layer 103, buffer layer 102 and substrate 100 is dry etching
Technique.
In the present embodiment, the depth H 1 of the groove 107 is in the range of 5.7 microns to 9 microns.But the present invention couple
The depth of the groove 107 is with no restrictions.It should be noted that depth H 2 of the groove 107 in substrate 100 is at 5 microns
To in the range of 8 microns.
With reference to Fig. 8, second insulating layer 108 is formed on 107 inner surface of groove and the hard mask layer 104.
The dielectric layer for functioning as semiconductor capacitor of the second insulating layer 108, it is therefore desirable to dielectric constant compared with
High material is formed.In the present embodiment, the second insulating layer 108 includes: the silicon oxide layer and silicon nitride layer sequentially formed,
Such composite layer while dielectric constant with higher and preferable insulating properties, but the present invention is to the second insulating layer
With no restrictions, in other embodiments, the second insulating layer 108 can also be single layer structure to 108 structure, such as described the
Two insulating layers 108 are silicon oxide layer or silicon nitride layer.
With reference to Fig. 9, electrode material layer 109 is filled in the groove 107, until covering 104 surface of hard mask layer.
In the present embodiment, due to being also formed with second insulating layer 108, the electrode material on the hard mask layer 104
109 covering 108 surface of second insulating layer of layer.
In the present embodiment, the material of the electrode material layer 109 is polysilicon, but the invention is not limited in this regard,
In other embodiments, the material of the electrode material layer 109 can also be metal.
It should be noted that the electrode material layer 109 is on 104 surface of hard mask layer in the present embodiment
Thickness is in the range of 2000 to 3000 angstroms.
In conjunction with reference Figure 10, Figure 11, chemical mechanical grinding is carried out to the electrode material layer 109 and hard mask layer 104, is gone
It is remaining to be located in groove 107 except the hard mask layer 104 of electrode material layer 109 and segment thickness on hard mask layer 104
Electrode material layer 109 forms electrode layer 110.The electrode layer 110 is used as the cathode plate of semiconductor capacitor, with the substrate
Doped region in 100 is used separately as two electrodes of semiconductor capacitor.
During chemical mechanical grinding, the electrode material layer 109 on 104 surface of hard mask layer is covered on by chemical machinery
Grind the removal.The material of first insulating layer 103 is silicon nitride, it is difficult to be removed by chemical mechanical grinding, therefore the first insulation
Layer 103 is used as the stop-layer of chemical mechanical grinding.There is the resistance of the first insulating layer 103 between buffer layer 102 and the hard mask layer 104
It keeps off, full electrode material layer 109 is also filled in groove 107, therefore the top of buffer layer 102 and side wall are respectively in first insulation
Layer 103 is under the covering of electrode material layer 109, and chemical mechanical grinding substantially will not impact the buffer layer 102, buffering
The position that layer 102 is contacted with electrode layer 110 will not generate notch.After forming the electrode layer 110, buffer layer 102 according to
So keep preferable pattern.
Specifically, in the present embodiment, the wafer where the substrate 100 is placed on grinding plate, is covered firmly to described
Electrode material layer 109, hard mask layer 104 in film layer 104 and the second insulating layer 108 on hard mask layer 104 carry out chemistry
Mechanical lapping, remove the electrode material layer 109 on the hard mask layer 104, the second insulating layer 108 on hard mask layer 104 with
And the hard mask layer 104 of segment thickness.
During chemical mechanical grinding, the technological parameter of the chemical mechanical grinding include: the lapping liquid that uses for
KOH or NH4OH.The revolving speed of grinding head is at 60 rpms or more.But the present invention to the process conditions of chemical mechanical grinding not
It is limited.
It should be noted that in the present embodiment chemical mechanical grinding, chemical mechanical grinding removes electrode material layer 109, hard
The speed of second insulating layer 108 on mask layer 104 and hard mask layer 104 is in the range of 40~5500 angstroms/min.Wherein,
KOH or NH4The lapping liquid of OH removes fast speed to the hard mask layer 104 of silica, goes to the electrode material layer 109 of polysilicon
Except speed is slower.And electrode material layer of the thickness of hard mask layer 104 than being covered on 104 surface of hard mask layer in the present embodiment
109 thickness are bigger, and therefore, the present embodiment uses KOH or NH4OH is as lapping liquid, to improve the efficiency of chemical mechanical grinding.
In the present embodiment, the process duration of chemical mechanical grinding was at 2 to 10 minutes.But the present invention does not limit this
System can also be directed to electrode material layer 109, second insulating layer 108 and hard mask layer 104 respectively and use in other embodiments
Suitable lapping liquid, to accelerate grinding rate.
It should be noted that the amount of grinding due to chemical mechanical grinding is more difficult to control, in the present embodiment, in chemical machine
After the hard mask layer 104 of tool grinding removal segment thickness, remaining hard mask layer 104 can prevent chemical machinery as buffering
The substrate 100 of 104 lower section of grinding damage hard mask layer.In the present embodiment, remaining 104 thickness of hard mask layer is arrived 500
In the range of 1000 angstroms.But the present invention is without limitation, it in other embodiments, can be in the process of chemical mechanical grinding
It is middle all to remove the hard mask layer 104.
In conjunction with reference Figure 11, dry etching is carried out to the surface after the chemical mechanical grinding, remaining is covered firmly with removing
Film layer 104.
The dry etching removes the remaining hard mask layer 104 as buffering completely, and will be located at the first insulation
Segment electrode layer 110 and second insulating layer 108 on layer 103 remove.
To sum up, in the present embodiment, it after filling electrode material layer 109 in the groove 107, is ground by chemical machinery
The electrode material layer 109 of electrode material layer 109 and segment thickness on the method removal hard mask layer 104 of mill.In chemical machine
During tool is ground, there is the blocking of the first insulating layer 103 between buffer layer 102 and the hard mask layer 104, buffer layer 102
Side wall is also covered by electrode material layer 109, and chemical mechanical grinding substantially will not impact the buffer layer 102.In dry method
During etching removes remaining hard mask layer 104, the side wall of buffer layer 102 is covered by electrode layer 110, the buffer layer
102 will not be influenced by dry etching, and after forming the electrode layer 110, buffer layer 102 still keeps preferable shape
Looks will not generate notch in the part contacted with electrode layer 110.In this way, the forming method of the present embodiment semiconductor structure avoids
In the prior art, since groove exposes the side wall of buffer layer, wet etching removal hard mask layer causes buffer layer to damage.Cause
This, the associativity between substrate 100 and the first insulating layer 103 is preferable, also, the electrode layer 110 near buffer layer 102 not
Rough defect can be generated, will not influence the capacitance of semiconductor capacitor, this sample embodiment is formed by semiconductor
Capacitor has preferable performance.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (14)
1. a kind of forming method of semiconductor structure, which is characterized in that the semiconductor structure is used to form capacitor, comprising:
Substrate is provided；
The substrate is doped, the partial region of the substrate is made to form doped region；
Buffer layer, the first insulating layer and hard mask layer are sequentially formed over the substrate；
Using the hard mask layer as exposure mask, first insulating layer, buffer layer and substrate are etched, in the substrate, buffer layer, the
Groove is formed in one insulating layer and hard mask layer；The groove is located in the doped region of the substrate；
Electrode material layer is filled in the groove, until covering the hard mask layer surface；
Chemical mechanical grinding is carried out to the electrode material layer and hard mask layer, removes the electrode material layer on hard mask layer, is remained
Remaining electrode material layer in the grooves is used to form electrode layer.
2. forming method as described in claim 1, which is characterized in that in the step of chemical mechanical grinding include: use
KOH or NH4OH is as lapping liquid.
3. forming method as described in claim 1, which is characterized in that in the step of the chemical mechanical grinding, grinding head
Revolving speed is at 60 rpms or more.
4. forming method as described in claim 1, which is characterized in that chemical mechanical grinding also removes the hard exposure mask of segment thickness
Layer, the forming method chemical mechanical grinding after the meeting further include: remaining hard mask layer is removed by dry etching.
5. forming method as described in claim 1, which is characterized in that form the step of hard mask layer on the first insulating layer
In rapid, the opening for exposing the first insulating layer is formed in the hard mask layer；
Using the hard mask layer as exposure mask, etch first insulating layer, buffer layer and substrate, the substrate, buffer layer,
In the step of forming groove in first insulating layer and hard mask layer, the first insulating layer, buffer layer that the opening is exposed are etched
And substrate.
6. forming method as described in claim 1, which is characterized in that in the substrate, buffer layer, the first insulating layer and hard
It is formed after groove in mask layer, before filling electrode material layer in the groove, the forming method further include:
Second insulating layer is formed on surface and the hard mask layer in the groove；
The step of electrode material layer is filled in the groove includes: the filling electrode material in the groove for being formed with second insulating layer
The bed of material.
7. the forming method stated such as claim 6, which is characterized in that the second insulating layer includes: the silica sequentially formed
Layer and silicon nitride layer.
8. forming method as described in claim 1, which is characterized in that the material of the buffer layer is silica.
9. forming method as described in claim 1, which is characterized in that range of the thickness of the buffer layer at 25 to 150 angstroms
It is interior.
10. forming method as described in claim 1, which is characterized in that the material of the hard mask layer is silica.
11. forming method as described in claim 1, which is characterized in that the thickness of the hard mask layer is at 7000 to 17000 angstroms
In the range of.
12. forming method as described in claim 1, which is characterized in that the material of the electrode layer is polysilicon.
13. forming method as described in claim 1, which is characterized in that the depth of the groove is at 5.7 microns to 9 microns
In range.
14. forming method as described in claim 1, which is characterized in that etching first insulating layer, buffer layer and substrate,
It is dry etch process in the method in the step of forming groove, etching first insulating layer, buffer layer and substrate.
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| CN102339791A (en) * | 2011-10-29 | 2012-02-01 | 上海华力微电子有限公司 | Manufacture method of semiconductor device |
| CN102903669A (en) * | 2011-04-21 | 2013-01-30 | 新加坡商格罗方德半导体私人有限公司 | Scheme for planarizing through-silicon vias |
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| CN102903669A (en) * | 2011-04-21 | 2013-01-30 | 新加坡商格罗方德半导体私人有限公司 | Scheme for planarizing through-silicon vias |
| CN102339791A (en) * | 2011-10-29 | 2012-02-01 | 上海华力微电子有限公司 | Manufacture method of semiconductor device |
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