CN105826187A - FinFET (Fin Field Effect Transistor) and formation method thereof - Google Patents
FinFET (Fin Field Effect Transistor) and formation method thereof Download PDFInfo
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Abstract
The invention relates to a FinFET (Fin Field Effect Transistor) and a formation method thereof. The formation method of the FinFET comprises the steps of providing a substrate, wherein the substrate comprises a first semiconductor layer, an insulating layer and a second semiconductor layer, forming a mask layer at partial surface of the second semiconductor layer and etching the second semiconductor layer by taking the mask layer as a mask to the insulating layer so as to form a fin portion, forming a sacrificial layer at the surface of the sacrificial layer, wherein the surface of the sacrificial layer is lower than top surface of the fin portion and covers partial side wall of the fin portion, and the part, which is higher than the sacrificial layer, of the fin portion acts as a first sub-fin portion, forming a protection layer at the side wall surface of the first sub-fin portion, removing the sacrificial layer, carrying out transverse etching on the fin portion along the exposed side wall of the fin portion so as to enable the width of partial fin portion to be reduced and enable the first sub-fin portion to be partially suspended, wherein the part, which is reduced in width, of the fin portion acts as a second sub-fin portion, and removing the protection layer and the mask layer and forming a gate structure which stretches across the first sub-fin portion and the second sub-fin portion. The formation method provided by the invention can improve the performance of the formed FinFET.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to a kind of fin formula field effect transistor and forming method thereof.
Background technology
Along with the development of semiconductor process technique, process node is gradually reduced, and rear grid (gate-last) technique is widely applied, and to obtain preferable threshold voltage, improves device performance.But when the characteristic size of device declines further, even if grid technique after Cai Yonging, the structure of conventional metal-oxide-semiconductor field effect transistor the most cannot meet the demand to device performance, and fin formula field effect transistor (FinFET) has obtained paying close attention to widely as a kind of multi-gate device.Fin formula field effect transistor can be effectively improved the short-channel effect of transistor, and the performance improving device is widely used in the semiconductor device such as logic circuit and SRAM memory.
Fig. 1 shows the perspective view of a kind of fin formula field effect transistor of prior art.As it is shown in figure 1, include: Semiconductor substrate 10, described Semiconductor substrate 10 being formed with the fin 11 of protrusion, fin 11 obtains generally by after etching Semiconductor substrate 10；Dielectric layer 12, covers the surface of described Semiconductor substrate 10 and a part for the sidewall of fin 11；Grid structure 13, across on described fin 11, covers atop part and the sidewall of described fin 11, and grid structure 13 includes gate dielectric layer (not shown) and the gate electrode (not shown) being positioned on gate dielectric layer.The part contacted with grid structure 13 for fin formula field effect transistor, the top of fin 11 and the sidewall of both sides all becomes channel region, i.e. has multiple grid, is conducive to increasing large-drive-current, improves device performance.
The performance of existing fin formula field effect transistor need further to improve.
Summary of the invention
The problem that the present invention solves is to provide a kind of fin formula field effect transistor and forming method thereof, improves the performance of fin formula field effect transistor.
For solving the problems referred to above, the present invention provides the forming method of a kind of fin formula field effect transistor, including: providing substrate, described substrate includes the first semiconductor layer, the insulating barrier being positioned at the first semiconductor layer surface and is positioned at the second semiconductor layer of described surface of insulating layer；Part surface at described second semiconductor layer forms mask layer, with described mask layer as mask, etches described second semiconductor layer to insulating barrier, formation fin；Forming sacrifice layer at described surface of insulating layer, the surface of described sacrifice layer is less than the top surface of fin and covers the partial sidewall of fin, higher than the part fin of sacrifice layer as the first sub-fin；Protective layer is formed in the first sub-fin sidewall surfaces；Remove sacrifice layer, expose the partial sidewall of fin；Fin sidewall along described exposure carries out lateral etching to described fin, makes the width of part fin reduce, and makes the first sub-fin part unsettled, and the part fin that described width reduces is as the second sub-fin；After removing described protective layer and mask layer, it is developed across the first sub-fin and the grid structure of the second sub-fin, the sidewall of the described sub-fin of grid structure covering part second, the sidewall of the sub-fin of part first, top and overhanging portion bottom surface.
Optionally, the second sub-fin width is the 30%～60% of the first sub-fin width.
Optionally, described sacrifice layer is 2nm～20nm with the difference in height at fin top.
Optionally, the thickness of described protective layer is
Optionally, the quantity of described fin is two or more, and the spacing between adjacent fin is more than
Optionally, the method forming described sacrifice layer includes: form expendable material, described expendable material mask film covering layer surface at described surface of insulating layer；With described mask layer as stop-layer, described expendable material is planarized, form sacrificial material layer, make the surface of described sacrificial material layer flush with mask layer surface；Etch described sacrificial material layer, make the height of described sacrificial material layer decline, form sacrifice layer.
Optionally, the material of described sacrifice layer is different from the material of mask layer, insulating barrier.
Optionally, the material of described mask layer is silicon oxide, and the material of insulating barrier is silicon oxide, and the material of sacrifice layer is silicon nitride.
Optionally, the method forming described expendable material is plasma deposition process or heat deposition technique.
Optionally, the depositing temperature of described plasma deposition process is 350 DEG C～600 DEG C, and reacting gas is SiH2Cl2And NH3, wherein SiH2Cl2Flow be 1slm～10slm, NH3Flow be 1slm～20slm, pressure is 2mTorr～5Torr.
Optionally, the depositing temperature of described heat deposition technique is 630 DEG C～800 DEG C, and reacting gas is SiH2Cl2And NH3, wherein SiH2Cl2Flow be 50sccm～1000sccm, NH3Flow be 100sccm～5000slm, pressure is 0.1Torr～5Torr.
Optionally, use wet-etching technology or dry etch process to etch described sacrificial material layer, form sacrifice layer.
Optionally, if described sacrificial material layer using plasma depositing operation is formed, then hydrofluoric acid solution or phosphoric acid solution is used to etch described sacrificial material layer；If described sacrificial material layer uses heat deposition technique to be formed, then phosphoric acid solution is used to etch described sacrificial material layer.
Optionally, use wet-etching technology or gas phase etching technics, along the fin sidewall of described exposure, described fin is carried out lateral etching.
Optionally, the etching solution that described wet-etching technology uses is tetramethyl ammonium hydroxide solution, and temperature is 25 DEG C～100 DEG C, and mass fraction is 2%～35%.
Optionally, the etching gas that described gas phase etching technics uses is Cl2Or one or both in HCl, etching gas flow is 20sccm～2000sccm, and temperature is 500 DEG C～800 DEG C, and pressure is 5Torr～15Torr.
Optionally, the height of described fin is 20nm～50nm, and width is 15nm～40nm.
Optionally, thermal oxidation technology is used to form protective layer in described first sub-fin sidewall surfaces.
Optionally, the method forming described protective layer includes: form protection material layer at described sacrificial layer surface, the first sub-fin sidewall surfaces, the sidewall of mask layer and top surface；Use without mask etching technique, described protection material layer is performed etching, remove the protection material layer being positioned at sacrificial layer surface and mask layer top surface, formed and cover the first sub-fin sidewall surfaces, the protective layer of mask layer sidewall surfaces.
Technical scheme also provides for a kind of fin formula field effect transistor using said method to be formed, including: the first semiconductor layer；It is positioned at the insulating barrier of the first semiconductor layer surface；Being positioned at the fin of described surface of insulating layer, described fin includes the second sub-fin being positioned at surface of insulating layer, is positioned at the first sub-fin above the first sub-fin, and the width of described first sub-fin is more than the width of the second sub-fin；Across the first sub-fin and the grid structure of the second sub-fin, the sidewall of the described sub-fin of grid structure covering part second, the sidewall of the sub-fin of part first, top and overhanging portion bottom surface.
Compared with prior art, technical scheme has the advantage that
Technical scheme proposes the forming method of a kind of fin formula field effect transistor, etches the second semiconductor layer and forms fin, and described fin top has mask layer；Forming sacrifice layer the most on the insulating layer, described sacrificial layer surface is less than the top surface of fin, higher than the part fin of sacrifice layer as the first sub-fin；Protective layer is formed in the first sub-fin sidewall surfaces; then described sacrifice layer is removed; expose part fin sidewall; then the fin sidewall along described exposure carries out lateral etching; form the second sub-fin; make the width width less than the first sub-fin of described second sub-fin, be then developed across described first sub-fin and the grid structure of the second sub-fin.During fin is carried out lateral etching, the first sub-fin protected by described mask layer and protective layer, makes the size of described first sub-fin not change.The fin structure surface area that described first sub-fin and the second sub-fin are formed is more than the surface area of the fin being initially formed, so after forming grid structure in described fin structure, channel region area below described grid structure increases, the short-channel effect of fin formula field effect transistor can be improved, thus improve the performance of transistor.
Further, width is the first sub-fin width the 30%～60% of described second sub-fin, the channel area that can make the fin field effect pipe ultimately formed is significantly increased, and is avoided that again the first sub-fin above being not enough to owing to the second sub-fin width is too small to support and collapses and constitute the harmful effects such as the deposition quality of grid structure that the excessive impact of depth of groove is subsequently formed between insulating barrier, the second sub-fin and the first sub-fin.
Further, described sacrifice layer is 2nm～20nm with the difference in height at fin top.The difference in height at described sacrifice layer and fin top is the thickness of the first sub-fin, so that it is guaranteed that described first sub-fin has enough thickness.If the thickness of described first sub-fin is too low, it is easily caused in follow-up oxidation, cleans or in other technological processes such as etching, described first sub-fin is totally consumed.
Further, the thickness of described protective layer isIf the thickness of described protective layer is too small; then in subsequent technique; the sidewall of the first sub-fin can not be played enough protective effects; if and the thickness of described protective layer 302 is excessive; then it is easily caused protective layer and fills the gap between the adjacent first sub-fin of full phase, cause the follow-up sacrifice layer that cannot take out below protective layer.
Technical scheme also provides for a kind of fin formula field effect transistor, described fin formula field effect transistor has the first sub-fin and the fin of the second sub-fin, first sub-fin is positioned on the second sub-fin, and second the width of sub-fin less than the width of the first sub-fin, then the grid structure of described fin it is developed across, thus compared with prior art, the channel region area of fin formula field effect transistor can be improved, thus improve the performance of fin formula field effect transistor.
Accompanying drawing explanation
Fig. 1 is the structural representation of the fin formula field effect transistor of the prior art of the present invention；
Fig. 2 to Figure 11 is the structural representation of the forming process of the fin formula field effect transistor of embodiments of the invention.
Detailed description of the invention
As described in the background art, the performance of existing fin formula field effect transistor needs further to be improved.
In embodiments of the invention, formed and there is the first sub-fin and the fin of the second sub-fin, first sub-fin is positioned on the second sub-fin, and second the width of sub-fin less than the width of the first sub-fin, then the grid structure of described fin it is developed across, such that it is able to improve the channel region area of transistor, thus improve the performance of fin formula field effect transistor.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with the accompanying drawings the specific embodiment of the present invention is described in detail.
Refer to Fig. 2, it is provided that substrate, described substrate includes the first semiconductor layer 101, the insulating barrier 102 being positioned at the first semiconductor layer 101 surface and is positioned at second semiconductor layer 103 on described insulating barrier 102 surface.
The material of described first semiconductor layer 101 can be the semi-conducting materials such as silicon, germanium, germanium silicon or carborundum, the material of described second semiconductor layer 103 can be the semi-conducting materials such as silicon, germanium, germanium silicon or carborundum, and the material of described insulating barrier 102 can be the insulating dielectric materials such as silicon oxide, silicon oxynitride, silicon nitride.
In the present embodiment, described substrate is silicon-on-insulator substrate, wherein, described first semiconductor layer 101 material be silicon, insulating barrier 102 material be silicon oxide, the material of the 3rd semiconductor layer 102 is silicon.Described insulating barrier 102 is as the isolation structure between follow-up device and the first semiconductor layer 101 formed on substrate.
Refer to Fig. 3, the part surface at described second semiconductor layer 103 forms mask layer 200.
The material of described mask layer 200 can be the mask materials such as silicon oxide, silicon nitride, amorphous carbon.
In the present embodiment, the material of described mask layer 200 is silicon oxide, use oxidation technology after described second semiconductor layer 103 surface forms mask layer, described mask layer is patterned, forms the mask layer 200 of covering part the second semiconductor layer 103.
In other embodiments of the invention, it would however also be possible to employ depositing operation forms mask layer on described second semiconductor layer 103 surface, is then patterned described mask layer, forms the mask layer 200 of covering part the second semiconductor layer 103.
The thickness of described mask layer 200 can beIt is thus possible to after being subsequently formed fin, enough protective effects are played at the top of fin.
Refer to Fig. 4, with described mask layer 200 as mask, etch described second semiconductor layer 103 (refer to Fig. 3) to insulating barrier 102, form fin 201.
Using dry etch process to etch described second semiconductor layer 103, concrete described dry etch process is plasma etch process, and the etching gas of employing includes HBr and Cl2.In the present embodiment, the etching gas that described dry etch process uses is HBr and Cl2Mixed gas as etching gas, O2As buffer gas, wherein the flow of HBr is 50sccm～1000sccm, Cl2Flow be 50sccm～1000sccm, O2Flow be 5sccm～20sccm, pressure is 5mTorr～50mTorr, and power is 400W～750W, O2Gas flow be 5sccm～20sccm, temperature is 40 DEG C～80 DEG C, and bias voltage is 100V～250V.
The quantity of described fin 201 can be one or more.In the present embodiment, to form two fins 201 as example.
When the quantity of described fin 201 is two or more, and the spacing between adjacent fin 201 is more thanIt is easy to follow-up form certain thickness protective layer in fin 201 sidewall surfaces.
In the present embodiment, owing to using oxidation technology to form mask layer on the second semiconductor layer 103 surface, the thickness making the second semiconductor layer 103 has been lost, so the height of fin 201 that the second semiconductor layer 103 described in described mask layer 200 as mask etching is formed is slightly less than the elemental height of the second semiconductor layer 103.
The height of described fin 201 is 20nm～50nm, and width is 15nm～40nm.The size of described fin 201 can be adjusted according to actual needs.
Refer to Fig. 5, form sacrificial material layer 300 on described insulating barrier 102 surface, the surface of described sacrificial material layer 300 flushes with mask layer 200 surface.
Concrete, the method forming described sacrificial material layer 300 includes: on described insulating barrier 102 surface deposited sacrificial material, described expendable material mask film covering layer surface；With described mask layer 200 as stop-layer, described expendable material is planarized, form sacrificial material layer 300, make the surface of described sacrificial material layer 300 flush with mask layer 200 surface.In the present embodiment, use chemical machinery masking process that described expendable material is planarized.
The material of described sacrificial material layer 300 is different from the material of mask layer 200, insulating barrier 102.In the present embodiment, the material of described mask layer 200 is silicon oxide, the material of insulating barrier 102 is silicon oxide, the material of sacrificial material layer 300 is silicon nitride, so that mask layer 200 can sacrifice adjacent stop-layer as planarization, and, follow-up sacrificial material layer 300 is being performed etching formation sacrifice layer, and during removal sacrifice layer, described insulating barrier 103 and mask layer 200 will not be impacted.
The method forming described expendable material is plasma deposition process or heat deposition technique.
In the present embodiment, using plasma depositing operation forms described expendable material, concrete, and the depositing temperature of described plasma deposition process is 350 DEG C～600 DEG C, and reacting gas is SiH2Cl2And NH3, wherein SiH2Cl2Flow be 1slm～10slm, NH3Flow be 1slm～20slm, pressure is 2mTorr～5Torr.Described plasma deposition process, by after plasmarized for reacting gas, deposits, and reaction temperature is relatively low, can reduce process heat budget.
In other embodiments of the invention, it would however also be possible to employ heat deposition technique forms described expendable material, concrete, the depositing temperature of described heat deposition technique is 630 DEG C～800 DEG C, and reacting gas is SiH2Cl2And NH3, wherein SiH2Cl2Flow be 50sccm～1000sccm, NH3Flow be 100sccm～5000slm, pressure is 0.1Torr～5Torr.Described heat deposition technique directly uses reactant gas molecules to carry out expendable material described in reactive deposition, and reaction temperature is higher.
In other embodiments of the invention, it would however also be possible to employ other depositing operations form described expendable material.
Refer to Fig. 6, lose described sacrificial material layer 300 (refer to Fig. 5), the height making described sacrificial material layer 300 declines, form sacrifice layer 301, the surface of described sacrifice layer 301 is less than the top surface of fin 201 (refer to Fig. 5) and covers the partial sidewall of fin 201, higher than the part fin 201 of sacrifice layer 301 as the first sub-fin 211.In Fig. 6, split described first sub-fin 211 with dotted line.
Dry or wet etch technique can be used to etch described sacrificial material layer 300, form described sacrifice layer 301.
In the present embodiment, wet-etching technology is used to etch described sacrificial material layer 300.Owing to the material of described sacrificial material layer 300 is different from the material of mask layer 200 and insulating barrier 102, the etching solution making that there is between sacrificial material layer 300 and mask layer 200, insulating barrier 102 relatively high selectivity can be selected, described sacrificial material layer 300 is performed etching.
Refer to table 1, the silicon nitride that the silicon nitride formed for silicon oxide, plasma deposition process and heat deposition technique are formed etch rate under phosphoric acid and two kinds of solution of Fluohydric acid..
Table 1
In table 1, HF solution is the hydrofluoric acid solution that mass fraction is 49% and the H of 100 volumes of 1 volume2The mixed solution of O, H3PO4The mass fraction of solution is 85%.
It can be seen that the etch rate that the silicon nitride of employing heat deposition technique formation is in HF solution is the least, and at H3PO4Solution then has higher etch rate；And plasma deposition process formed silicon nitride in HF solution with H3PO4Solution is respectively provided with higher etch rate, at H3PO4Etch rate in solution is higher.
So, if described sacrificial material layer 300 using plasma depositing operation is formed, then hydrofluoric acid solution or phosphoric acid solution can be used to etch described sacrificial material layer；If described sacrificial material layer 300 uses heat deposition technique to be formed, then phosphoric acid solution can be used to etch described sacrificial material layer.
In the present embodiment, use H3PO4Described sacrificial material layer 300 is performed etching by solution, and the mass fraction of wherein said H3PO4 solution is 80%～90%, and temperature is 165 DEG C.Due to H3PO4Solution is much larger than the etch rate of silicon oxide to the etch rate of silicon nitride, so, during etching described sacrificial material layer 300, insulating barrier 102 and mask layer 200 will not be caused damage.
In other embodiments of the invention, if described sacrificial material layer 300 using plasma depositing operation is formed, can also use HF solution that described sacrificial material layer 300 is performed etching, hydrofluoric acid solution be 1 volume mass mark be hydrofluoric acid solution and the H of 100 volumes of 49%2The mixed solution of O, temperature is room temperature 23 DEG C.But in this case, can first use H3PO4Sacrificial material layer 300 is performed etching by solution, make described sacrificial material layer 300 surface less than after mask layer 200, HF solution is used to perform etching again, owing to described HF solution pair also has higher etch rate with silicon oxide, so, mask layer 200 and sacrificial material layer 300, the thickness of the sacrifice layer 301 that can be ultimately formed by adjustment can be lost in the same time, after making to form described sacrifice layer 301, described fin 301 top also has the mask layer 200 of segment thickness.In other embodiments of the invention, it is also possible to directly use HF solution to perform etching, while forming sacrifice layer 301; remove described mask layer 200; follow-up again fin 201 is aoxidized, form silicon oxide layer at described fin 201 top, subsequent technique is protected the top of described fin 201.Due to H3PO4Solution has certain etch rate to silicon, uses HF solution to perform etching sacrificial material layer 300, can avoid H3PO4Fin 201 sidewall is caused damage by solution.
In the present embodiment, the difference in height between described sacrifice layer 301 and fin 201 top of formation is 2nm～20nm.Higher than the part fin 201 of sacrifice layer 301 as the first sub-fin 211, the thickness of the most described first sub-fin 211 is 2nm～20nm, it is ensured that described first sub-fin 211 has enough thickness.If the thickness of described first sub-fin 211 is too low, it is easily caused in follow-up oxidation, cleans or in other technological processes such as etching, described first sub-fin 211 is totally consumed.The thickness of described sacrifice layer 301 can be 5nm～10nm.
Refer to Fig. 7, form protective layer 302 in the first sub-fin 211 sidewall surfaces.
Thermal oxidation technology or depositing operation can be used to form described protective layer 302 in described first sub-fin 211 sidewall surfaces.
In the present embodiment, use depositing operation to form described protective layer 302, including: on described sacrifice layer 301 surface, the first sub-fin 211 sidewall surfaces, the sidewall of mask layer 200 and top surface form protection material layer；Use without mask etching technique, described protection material layer is performed etching, remove the protection material layer being positioned at sacrifice layer 301 surface and mask layer 200 top surface, formed and cover the first sub-fin 211 sidewall surfaces, the protective layer 302 of mask layer sidewall surfaces.
If the thickness of described protective layer 302 is too small; then in subsequent technique; the sidewall of the first sub-fin 211 can not be played enough protective effects; if and the thickness of described protective layer 302 is excessive; then it is easily caused protective layer 302 and fills the gap between the adjacent first sub-fin 211 of full phase, cause the follow-up sacrifice layer 301 that cannot take out below protective layer 302.In the present embodiment, the thickness of described protective layer 302 is
In other embodiments of the invention, it would however also be possible to employ thermal oxidation technology, the sidewall of the first sub-fin 211 is aoxidized, form the protective layer 302 covering the first sub-fin 211 sidewall.But use thermal oxidation technology that the width of the first sub-fin 211 can be made to reduce, the performance of transistor can be affected.
Refer to Fig. 8, remove described sacrifice layer 301 (refer to Fig. 7), expose the partial sidewall of fin 201.
Wet-etching technology is used to remove sacrifice layer 301; the etching solution that described wet-etching technology uses is phosphoric acid solution; described phosphoric acid solution has higher Etch selectivity to sacrifice layer 301; thus during removing described sacrifice layer 301; still can retain described protective layer 302 and mask layer 200, so that described protective layer 302 and mask layer 200 can protect described first sub-fin 211 in subsequent technique.
After removing described sacrifice layer 301, expose the fin sidewall being positioned at below the first sub-fin 211.
Refer to Fig. 9, fin 201 sidewall along described exposure carries out lateral etching to described fin 201, makes the width of part fin 201 reduce, and makes the first sub-fin 211 part unsettled, and the part fin that described width reduces is as the second sub-fin 212.In Fig. 9, split described first sub-fin 211 and the second sub-fin 212 with dotted line.
Can use wet-etching technology or gas phase etching technics, along fin 201 sidewall of described exposure, described fin 201 is carried out lateral etching, form the second sub-fin 212.
During described fin 201 is carried out lateral etching; described protective layer 301 and mask layer 200 protect described first sub-fin 211; the width making described first sub-fin 211 does not changes, and the width making described first sub-fin 211 is consistent with fin 201 (the refer to Fig. 4) width originally formed.
The etching solution that described wet-etching technology uses is tetramethyl ammonium hydroxide solution, and temperature is 25 DEG C～100 DEG C, and mass fraction is 2%～35%.Owing to described tetramethyl ammonium hydroxide solution has different etch rates on the different crystal orientations of silicon.When described second semiconductor layer 103 is when the crystal orientation etched on direction is<110>, tetramethyl ammonium hydroxide solution is used to carry out lateral etching, it is possible to obtain preferable etching effect.
In other embodiments of the invention, gas phase etching technics can be used to etch described fin 201, the etching gas that described gas phase etching technics uses is Cl2Or one or both in HCl, described gas phase etching technics is mainly reacted by fin 201 sidewall of etching gas molecule with exposure, thus performs etching described fin 201.Can be by adjusting the parameter of described gas phase etching process so that described gas phase etching technics has anisotropic etching character, make the lateral etch rate that described gas phase etches much larger than longitudinal etch rate.In one embodiment of the invention, described etching gas flow is 20sccm～2000sccm, and temperature is 500 DEG C～800 DEG C, and pressure is 5Torr～15Torr.
The width of the second sub-fin 212 formed by above-mentioned etching is the least, finally forms at first sub-fin the 211, second sub-fin 212 that to have the channel area that the grid structure of same width formed the biggest, and the saturation current of fin formula field effect transistor is the biggest.If but the width of described second sub-fin 212 is too small, it is not enough to the first sub-fin 211 above supporting, it is susceptible to collapse, and, depth of groove is constituted excessive, the deposition quality of the grid structure that impact is subsequently formed between described insulating barrier the 102, second sub-fin 212 and the first sub-fin 211.So, in one embodiment of the invention, the width of the second sub-fin 212 can be the 30%～60% of the first sub-fin 201 width, the channel area of the fin field effect pipe ultimately formed can be made to be significantly increased, be avoided that again other bad impacts.In the present embodiment, the degree of depth that described fin 201 is carried out lateral etching is 5nm～15nm, such as, can be 6nm, 10nm or 14nm.
It is T-shaped or the fin structure of Ω shape that described first sub-fin 211 and the second sub-fin 212 constitute cross section, compared with the fin 201 vertical with the sidewall originally formed, section girth increases, i.e. surface area increases, the channel area of the fin formula field effect transistor being subsequently formed can be effectively improved, thus improve the short-channel effect of fin formula field effect transistor further, improve the performance of fin formula field effect transistor.
Refer to Figure 10, remove described protective layer 302 and mask layer 200.
Using wet-etching technology to remove described protective layer 302 and mask layer 200, the etching solution that described wet-etching technology uses is hydrofluoric acid solution.Although using hydrofluoric acid solution to carry out wet etching; insulating barrier 102 can be caused a certain degree of etching; but owing to the thickness of described protective layer 302 and mask layer 200 is relatively low; the etching process time is shorter; so; insulating barrier 102 is not resulted in considerable influence, does not interferes with the performance of the fin formula field effect transistor ultimately formed.
Refer to Figure 11, be developed across the first sub-fin 211 and grid structure 400 of the second sub-fin 212, sidewall, the sidewall of the sub-fin of part first 211, top and the overhanging portion bottom surface of the described sub-fin 212 of grid structure 400 covering part second.
Described grid structure 400 includes: gate dielectric layer 401 and the grid 402 being positioned at gate dielectric layer 401 surface.The material of described gate dielectric layer 401 can be silicon oxide, hafnium oxide, silicon hafnium oxide, zirconium oxide or aluminium oxide etc., and the material of described grid 402 can be polysilicon, tungsten, aluminum or titanium etc..
The method forming described grid structure 400 includes: forms gate dielectric material layer on the surface of the sub-fin in described insulating barrier 102 surface and first 211, second sub-fin 212 and is positioned at the gate material layers on gate dielectric material layer surface；Described gate material layers and gate dielectric material layer are patterned, are formed described across the first sub-fin 211 and grid structure 400 of the second sub-fin 212.
In the present embodiment, described grid structure 400 is simultaneously across two fin structure, and in an embodiment of the present invention, described grid structure 400 is only disconnected from each other across between a fin structure, the grid structure 400 in adjacent fin structure.
After forming described grid structure 400, in being additionally included in first sub-fin the 211, second sub-fin 212 of described grid structure 400 both sides, form source electrode and drain electrode (not shown).
In embodiments of the invention, formed and there is the first sub-fin and the fin of the second sub-fin, first sub-fin is positioned on the second sub-fin, and second the width of sub-fin less than the width of the first sub-fin, then the grid structure of described fin it is developed across, such that it is able to improve the channel region area of fin formula field effect transistor, thus improve the performance of fin formula field effect transistor.
Embodiments of the invention also provide for a kind of fin formula field effect transistor using said method to be formed.
Refer to Figure 11, described fin formula field effect transistor includes: the first semiconductor layer 101；It is positioned at the insulating barrier 102 on the first semiconductor layer 101 surface；Being positioned at the fin on described insulating barrier 102 surface, described fin includes the second sub-fin 212 being positioned at insulating barrier 102 surface, is positioned at the first sub-fin 211 above the second sub-fin 212, and the width of described first sub-fin 211 is more than the width of the second sub-fin 212；Across the first sub-fin 211 and grid structure 400 of the second sub-fin 212, sidewall, the sidewall of the sub-fin of part first 211, top and the overhanging portion bottom surface of the described sub-fin 212 of grid structure 400 covering part second.
Second sub-fin 212 width is the 30%～60% of the first sub-fin 211 width.The thickness of described first sub-fin 211 is 2nm～20nm.
Described grid structure 400 includes: gate dielectric layer 401 and the grid 402 being positioned at gate dielectric layer 401 surface.
Compared with existing fin formula field effect transistor, the channel region area of described fin formula field effect transistor improves, it is possible to is effectively improved short-channel effect, thus has higher performance.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. the forming method of a fin formula field effect transistor, it is characterised in that including:
Thering is provided substrate, described substrate includes the first semiconductor layer, the insulating barrier being positioned at the first semiconductor layer surface and is positioned at the second semiconductor layer of described surface of insulating layer；
Part surface at described second semiconductor layer forms mask layer, with described mask layer as mask, etches described second semiconductor layer to insulating barrier, formation fin；
Forming sacrifice layer at described surface of insulating layer, the surface of described sacrifice layer is less than the top surface of fin and covers the partial sidewall of fin, higher than the part fin of sacrifice layer as the first sub-fin；
Protective layer is formed in the first sub-fin sidewall surfaces；
Remove sacrifice layer, expose the partial sidewall of fin；
Fin sidewall along described exposure carries out lateral etching to described fin, makes the width of part fin reduce, and makes the first sub-fin part unsettled, and the part fin that described width reduces is as the second sub-fin；
After removing described protective layer and mask layer, it is developed across the first sub-fin and the grid structure of the second sub-fin, the sidewall of the described sub-fin of grid structure covering part second, the sidewall of the sub-fin of part first, top and overhanging portion bottom surface.
The forming method of fin formula field effect transistor the most according to claim 1, it is characterised in that the second sub-fin width is the 30%～60% of the first sub-fin width.
The forming method of fin formula field effect transistor the most according to claim 1, it is characterised in that described sacrifice layer is 2nm～20nm with the difference in height at fin top.
The forming method of fin formula field effect transistor the most according to claim 1, it is characterised in that the thickness of described protective layer is
The forming method of fin formula field effect transistor the most according to claim 4, it is characterised in that the quantity of described fin is two or more, the spacing between adjacent fin is more than
The forming method of fin formula field effect transistor the most according to claim 1, it is characterised in that the method forming described sacrifice layer includes: form expendable material, described expendable material mask film covering layer surface at described surface of insulating layer；With described mask layer as stop-layer, described expendable material is planarized, form sacrificial material layer, make the surface of described sacrificial material layer flush with mask layer surface；Etch described sacrificial material layer, make the height of described sacrificial material layer decline, form sacrifice layer.
The forming method of fin formula field effect transistor the most according to claim 6, it is characterised in that the material of described sacrifice layer is different from the material of mask layer, insulating barrier.
The forming method of fin formula field effect transistor the most according to claim 7, it is characterised in that the material of described mask layer is silicon oxide, the material of insulating barrier is silicon oxide, and the material of sacrifice layer is silicon nitride.
The forming method of fin formula field effect transistor the most according to claim 8, it is characterised in that the method forming described expendable material is plasma deposition process or heat deposition technique.
The forming method of fin formula field effect transistor the most according to claim 9, it is characterised in that the depositing temperature of described plasma deposition process is 350 DEG C～600 DEG C, and reacting gas is SiH2Cl2And NH3, wherein SiH2Cl2Flow be 1slm～10slm, NH3Flow be 1slm～20slm, pressure is 2mTorr～5Torr.
The forming method of 11. fin formula field effect transistors according to claim 9, it is characterised in that the depositing temperature of described heat deposition technique is 630 DEG C～800 DEG C, and reacting gas is SiH2Cl2And NH3, wherein SiH2Cl2Flow be 50sccm～1000sccm, NH3Flow be 100sccm～5000slm, pressure is 0.1Torr～5Torr.
The forming method of 12. fin formula field effect transistors according to claim 1, it is characterised in that use wet-etching technology or dry etch process to etch described sacrificial material layer, form sacrifice layer.
The forming method of 13. fin formula field effect transistors according to claim 9, it is characterised in that if described sacrificial material layer using plasma depositing operation is formed, then use hydrofluoric acid solution or phosphoric acid solution to etch described sacrificial material layer；If described sacrificial material layer uses heat deposition technique to be formed, then phosphoric acid solution is used to etch described sacrificial material layer.
The forming method of 14. fin formula field effect transistors according to claim 1, it is characterised in that use wet-etching technology or gas phase etching technics, along the fin sidewall of described exposure, described fin is carried out lateral etching.
The forming method of 15. fin formula field effect transistors according to claim 14, it is characterised in that the etching solution that described wet-etching technology uses is tetramethyl ammonium hydroxide solution, and temperature is 25 DEG C～100 DEG C, and mass fraction is 2%～35%.
The forming method of 16. fin formula field effect transistors according to claim 14, it is characterised in that the etching gas that described gas phase etching technics uses is Cl2Or one or both in HCl, etching gas flow is 20sccm～2000sccm, and temperature is 500 DEG C～800 DEG C, and pressure is 5Torr～15Torr.
The forming method of 17. fin formula field effect transistors according to claim 1, it is characterised in that the height of described fin is 20nm～50nm, width is 15nm～40nm.
The forming method of 18. fin formula field effect transistors according to claim 1, it is characterised in that use thermal oxidation technology to form protective layer in described first sub-fin sidewall surfaces.
The forming method of 19. fin formula field effect transistors according to claim 1; it is characterized in that, the method forming described protective layer includes: form protection material layer at described sacrificial layer surface, the first sub-fin sidewall surfaces, the sidewall of mask layer and top surface；Use without mask etching technique, described protection material layer is performed etching, remove the protection material layer being positioned at sacrificial layer surface and mask layer top surface, formed and cover the first sub-fin sidewall surfaces, the protective layer of mask layer sidewall surfaces.
The fin formula field effect transistor that the method that 20. 1 kinds use described in claim 1 to 19 any claim is formed, it is characterised in that including:
First semiconductor layer；
It is positioned at the insulating barrier of the first semiconductor layer surface；
Being positioned at the fin of described surface of insulating layer, described fin includes the second sub-fin being positioned at surface of insulating layer, is positioned at the first sub-fin above the first sub-fin, and the width of described first sub-fin is more than the width of the second sub-fin；
Across the first sub-fin and the grid structure of the second sub-fin, the sidewall of the described sub-fin of grid structure covering part second, the sidewall of the sub-fin of part first, top and overhanging portion bottom surface.
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| CN111509045A (en) * | 2019-01-31 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and forming method thereof |
| CN112864227A (en) * | 2021-03-30 | 2021-05-28 | 长江存储科技有限责任公司 | Fin type field effect transistor and manufacturing method thereof |
| CN113948396A (en) * | 2021-09-18 | 2022-01-18 | 上海华力集成电路制造有限公司 | Method for manufacturing fin field effect transistor |
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| CN103367131A (en) * | 2012-04-09 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Fins and formation methods for fins and fin field effect transistor |
| CN103594361A (en) * | 2012-08-13 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor structure |
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| CN113948396A (en) * | 2021-09-18 | 2022-01-18 | 上海华力集成电路制造有限公司 | Method for manufacturing fin field effect transistor |
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