CN105826177B - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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Abstract
A kind of forming method of semiconductor devices, including：Substrate including first area, second area and third region is provided, the first pseudo- grid are formed on the part of substrate of first area, are formed with the second metal gates on second area part of substrate, first area and second area substrate surface are formed with interlayer dielectric layer；Nitridation coat of metal is converted by the second metal gates of segment thickness；On third substrate areas, the first pseudo- grid surface, nitridation metal coating layer surface and inter-level dielectric layer surface form initial gallium nitride layer；Initial gallium nitride layer is etched using dry etch process, forms the gallium nitride layer being located on third substrate areas；Using gallium nitride layer as exposure mask, the pseudo- grid of etching first form the first opening in the interlayer dielectric layer of first area；Form the first metal gates of full first opening of filling.The present invention is in semiconductor devices forming process, and the protection by nitridation coat of metal, the electric property of the semiconductor devices of formation are good always for the second metal gates.
Description
Technical field
The present invention relates to field of semiconductor fabrication technology, in particular to a kind of forming method of semiconductor devices.
Background technique
Currently, in the manufacturing process of semiconductor devices, P type metal oxide semiconductor (PMOS, P type Metal
Oxide Semiconductor) pipe, N-type metal-oxide semiconductor (MOS) (NMOS, N type Metal Oxide
Semiconductor) pipe or the CMOS complementary metal-oxide-semiconductor collectively formed by PMOS tube and NMOS tube (CMOS,
Complementary Metal Oxide Semiconductor) pipe be constitute chip main devices.
With the continuous development of production of integrated circuits technology, semiconductor device art node constantly reduces, the geometry of device
Size follows Moore's Law and constantly reduces.When device size reduces to a certain extent, the various physics limit institutes because of device
Bring second-order effect occurs in succession, and the characteristic size of device is scaled to become more and more difficult.Wherein, in semiconductor system
Make field, most challenging is how to solve the problems, such as that device creepage is big.The leakage current of device is big, mainly by traditional grid
Thickness of dielectric layers constantly reduces caused.The solution currently proposed is to replace traditional two using high-k gate dielectric material
Gate silicon oxide dielectric material, and use metal as gate electrode, Fermi's energy occurs to avoid high-g value and conventional gate electrodes material
Grade pinning effect and boron osmotic effect.The introducing of high-k/metal gate reduces the leakage current of device.
However, although the high-k/metal gate technique introduced, the electric property for the semiconductor devices that the prior art is formed still needs
It improves.
Summary of the invention
Problems solved by the invention is that the prior art is previously formed after the second metal gates when forming the first metal gates, first
The second metal gate formed is easily corroded or by etching injury, causes the overall performance of semiconductor devices low.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, including：There is provided includes the firstth area
Domain, second area and third region substrate, the first pseudo- grid, the second area are formed on the first area part of substrate
The second metal gates are formed on part of substrate, the first area and second area substrate surface are formed with interlayer dielectric layer,
And the interlayer dielectric layer is also covered in the first pseudo- grid sidewall surfaces and the second metal gates sidewall surfaces；To second metal
Gate surface carries out nitrogen treatment, converts nitridation coat of metal for the second metal gates of segment thickness；In the third
On substrate areas, the first pseudo- grid surface, nitridation metal coating layer surface and inter-level dielectric layer surface form initial gallium nitride
Layer；The initial gallium nitride layer is etched using dry etch process, exposes the first pseudo- grid surface and nitridation coat of metal
Surface forms the gallium nitride layer being located on third substrate areas；Using the gallium nitride layer as exposure mask, etching removal described first is pseudo-
Grid form the first opening in the first area interlayer dielectric layer；Form the first metal gate of full first opening of filling
Pole.
Optionally, the etching gas of the dry etch process includes Cl2；The dry etch process is to initial gallium nitride
The etching selection ratio of layer and nitridation coat of metal is more than or equal to 10.
Optionally, the dry etch process is inductively coupled plasma etching.
Optionally, the technological parameter of the inductively coupled plasma etching technique is：There is provided source power be 100 watts extremely
1100 watts, direct current biasing power is 10V to 50V, and etching cavity pressure is 1 millitorr to 20 millitorrs, Cl2Flow be 10sccm extremely
30sccm, is also passed through Ar into etching cavity, and Ar flow is 0sccm to 15sccm.
Optionally, the etching technics is more than or equal to the etching selection ratio of initial gallium nitride layer and nitridation coat of metal
10 and be less than or equal to 40.
Optionally, the initial nitridation is formed using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process
Gallium layer.
Optionally, use chemical vapor deposition process formed the technological parameter of the initial gallium nitride layer for：Gallium source is provided
And nitrogen source, wherein gallium source is (C2H5)3Ga、(CH3)3Ga or (C4H9)3Ga, nitrogen source NH3, reaction chamber temperature is 600 to take the photograph
Family name's degree is to 1000 degrees Celsius.
Optionally, the initial gallium nitride layer with a thickness of 50 angstroms to 500 angstroms.
Optionally, using N2O and NH3Carry out the nitrogen treatment；The treatment temperature of the nitrogen treatment is 300 degrees Celsius
To 1000 degrees Celsius.
Optionally, it is described nitridation coat of metal with a thickness of 10 angstroms to 100 angstroms.
Optionally, second metal gates include：Second work-function layer and positioned at the of the second work-function layer surface
Two metallic object layers, and flushed at the top of the second metallic object layer and second area interlayer dielectric layer.
Optionally, it is by the method that the second metal gates of the segment thickness are converted into nitridation coat of metal：By portion
The second metallic object layer of thickness is divided to be converted into nitridation coat of metal.
Optionally, the material of the second metallic object layer includes copper, aluminium or tungsten.
Optionally, when the material of the second metallic object layer is aluminium, the material of the nitridation coat of metal is aluminium nitride.
It optionally, further include step after forming first opening, before forming first metal gates：It adopts
Use CF4Gas performs etching post-processing to the first opening.
Optionally, the technological parameter of the etching post-processing is：Reaction chamber pressure is 0.2 support to 1 support, provides radio frequency source
Power is 50 watts to 200 watts, Ar is also passed through into reaction chamber, wherein Ar and CF4Gas flow ratio be 0 to 0.3, technique
Shi Changwei 10 seconds to 600 seconds.
Optionally, first metal gates include：Positioned at the first work-function layer of the first open bottom and sidewall surfaces；
Positioned at the first work-function layer surface and the first metallic object layer of full first opening of filling, and at the top of the first metallic object layer
It is flushed with first area interlayer dielectric layer top.
Optionally, the first gate dielectric layer is formed between first metal gates and substrate；Second metal gates
The second gate dielectric layer is formed between substrate.
Optionally, the first area is NMOS area or PMOS area；The second area is NMOS area or PMOS
Region, and the first area is different from the area type of second area.
Compared with prior art, technical solution of the present invention has the following advantages that：
In the technical solution of method for forming semiconductor devices provided by the invention, is formed on the part of substrate of first area
One pseudo- grid are formed with the second metal gates on second area part of substrate；Then the second metal gates surface is carried out at nitridation
Reason, converts nitridation coat of metal for the second metal gates of segment thickness, the nitridation coat of metal of formation can play
The effect for protecting the second metal gates prevents the second metal gates to be corroded or be damaged；Then, the first pseudo- grid surface,
Nitridation metal coating layer surface, inter-level dielectric layer surface form initial gallium nitride layer；Then, initial nitrogen is etched using dry etching
Change gallium layer, exposes the first pseudo- grid surface and nitridation metal coating layer surface, form the gallium nitride being located on third substrate areas
Layer, for identical compared to the thickness for nitrogenizing coat of metal after traditional titanium nitride layer and nitrogen treatment, dry method in the present invention
Etching technics is big to the etching selection ratio between initial gallium nitride layer and nitridation coat of metal, and dry etch process is to nitridation
Etching selection ratio between titanium layer and nitridation coat of metal is small, therefore is etching initial gallium nitride layer formation nitridation in the present invention
During gallium layer, the amount of the nitrided metal layer consumed is less, so that in the present embodiment after forming gallium nitride layer, second
Still there is the nitridation metal nitride layer of adequate thickness on metal gates surface, and the second metal gates is prevented to be exposed to the dry etching work
In skill, the second metal gates is avoided to be corroded.
Simultaneously as being removed in the present invention by mask etching of gallium nitride layer compared with traditional titanium nitride layer is exposure mask
When the first pseudo- grid, the thickness positioned at the nitridation coat of metal on the second metal gates surface is thicker, can be avoided and is formed in etching
Coat of metal is nitrogenized during first pseudo- grid to be removed, and the second metal gates is avoided to be exposed to the etching of the pseudo- grid of etching second
In environment.Therefore, the present invention can be improved the performance of the second metal gates, to improve the electrical property of the semiconductor devices of formation
Energy.
Further, in the present invention, etching selection of the dry etch process to initial gallium nitride layer and nitridation coat of metal
Than being more than or equal to 10, so that nitridation coat of metal is hardly etched during etching forms gallium nitride layer.
Further, initial gallium nitride layer is performed etching using inductively coupled plasma etching technique in the present invention, and
The technological parameter that three-dimensional etching technics is waited by changing inductive coupling, so that dry etch process is to initial gallium nitride layer and nitrogen
Change etching selection ratio with higher between coat of metal.Specifically, the technique of inductively coupled plasma etching technique is joined
Number is：There is provided source power is 100 watts to 1100 watts, and direct current biasing power is 10V to 50V, and etching cavity pressure is 1 millitorr to 20
Millitorr, Cl2Flow is 10sccm to 30sccm, and Ar is also passed through into etching cavity, and Ar flow is 0sccm to 15sccm.
Further, after etching forms the first opening, using CF4Gas performs etching post-processing to the first opening,
Etching removal is located at the etch by-products in the first opening.Meanwhile etching post-processing is also avoided in the present invention to nitridation metal
Protective layer causes excessive etching, so that etching post-processing is very small to the etch rate of nitridation coat of metal, to keep away
Exempt from the second metal gates to be exposed, so that the second metal gates obtain preferably protection, further increases semiconductor devices
Electric property.Specifically, the technological parameter for etching post-processing in the present invention is：Reaction chamber pressure is 0.2 support to 1 support, is mentioned
It is 50 watts to 200 watts for RF source power, Ar is also passed through into reaction chamber, wherein Ar and CF4Gas flow ratio be 0 to
0.3, when technique, is 10 seconds to 600 seconds a length of.
Detailed description of the invention
Fig. 1 to Fig. 4 is the schematic diagram of the section structure for the semiconductor devices forming process that an embodiment provides；
Fig. 5 to Figure 12 be another embodiment of the present invention provides semiconductor devices forming process the schematic diagram of the section structure.
Specific embodiment
It can be seen from background technology that the electric property for the semiconductor devices that the prior art is formed is to be improved.
It has been investigated that in order to meet NMOS tube and PMOS tube improvement threshold voltage (Threshold Voltage) simultaneously
Requirement, generally use different metal materials as work function (WF, Work in the metal gates of NMOS tube and PMOS tube
Function) layer material, therefore the metal gates of NMOS tube and PMOS tube are successively formed, rather than be formed simultaneously NMOS tube and
PMOS tube metal gates.
In one embodiment, with reference to Fig. 1, provide substrate 100, the substrate 100 include PMOS area, NMOS area with
And other device areas；The first pseudo- grid 111, shape in the PMOS area substrate 100 are formed in the NMOS area substrate 100
At there are the second pseudo- grid 121, inter-level dielectric is formed in the PMOS area, NMOS area and other device area substrates 100
Layer 101, and the interlayer dielectric layer 101 is covered in the first pseudo- 111 side wall of grid and the second 121 side wall of pseudo- grid.
With reference to Fig. 2, the pseudo- grid 111 of etching removal described first form first in NMOS area interlayer dielectric layer 101 and open
Mouthful；The first metal gates 112 of full first opening of filling are formed, and first metal gate material has the first work content
Number.
With reference to Fig. 3, formation is covered in 101 surface of interlayer dielectric layer, 112 surface of the first metal gates and the second pseudo- grid
The initial hard mask layer 102 on 121 surfaces；
With reference to Fig. 4, etches initial hard mask layer 102 (the referring to Fig. 3) formation and be covered in other device area interlayers Jie
The hard mask layer 103 on 101 surface of matter layer, the hard mask layer 103 expose the pseudo- grid 121 of the first metal gates 112, second, with
And 101 surface of interlayer dielectric layer of NMOS area and PMOS area.
It then, is exposure mask with the hard mask layer 103, the pseudo- grid 121 of etching removal second are situated between in the PMOS area interlayer
The second opening is formed in matter layer 101；Form the second metal gates of full second opening of filling, and second metal gates
Material has the second work function.
Using the above method, enables to PMOS tube different with the work function of the metal gates of NMOS tube, meet respectively
The requirement of PMOS tube and NMOS tube to metal gates work function.However, using the above method formed semiconductor devices in, NMOS
The degraded performance of pipe is to cause the electric property of semiconductor devices integrally low.
The material of first metal gates 112 includes copper, aluminium or tungsten.For example, the material of the first metal gates 112 may include
Aluminium, the material on 112 surface of the first metal gates that corresponding hard mask layer 103 exposes are aluminium.Not with semiconductor structure size
It is disconnected to reduce, the thickness of initial hard mask layer 102 is blocked up in order to prevent and the problem of the figure that occurs collapses, made using metal material
For initial 102 material of hard mask layer, common initial 102 material of hard mask layer is TiN；And etch initial hard mask layer 102
Etching gas includes Cl2, first metal gates, 112 surface can be exposed during etching initial hard mask layer 102, because
This Cl2Into in the first metal gates 112.Due to Cl2Electrochemical reaction can occur with aluminium, and then lead to the first metal gates 112
Corrode, causes the electric property of NMOS tube low.
In order to avoid the above problem nitrogenizes the first metal gates 112 before forming initial hard mask layer 102
Processing, converts nitridation coat of metal for the first metal gates 112 of segment thickness, for example, 112 surface of the first metal gates
When material is aluminium, the material of the nitridation coat of metal is aluminium nitride.The nitridation coat of metal can stop Cl2Into
In first metal gates 112, so that the first metal gates 112 be prevented to be corroded.
However, further study show that, when etching the initial formation of hard mask layer 102 hard mask layer 103, the etching technics
It is low to the etching selection ratio between initial hard mask layer 102 and nitridation coat of metal, therefore hard mask layer 103 is formed in etching
During, a large amount of coat of metal that nitrogenizes is etched removal, or even will cause at the beginning of the first metal gates 112 are exposed to etching
In the environment of beginning hard mask layer 102, so that the first metal gates 112 are corroded.
Even if first metal gates, 112 surface is still covered by nitridation coat of metal after forming hard mask layer 103,
However compared with forming hard mask layer 103 before, the thickness for nitrogenizing coat of metal seriously reduces.When the pseudo- grid of etching removal second
When 121, nitridation coat of metal is exposed in etching environment, and since the thickness of nitridation coat of metal is excessively thin, so that nitridation
Coat of metal is easy to be etched, and causes the first metal gates 112 to be exposed in the etching environment of the pseudo- grid 121 of etching second, leads
It causes the first metal gates 112 by etching injury, influences the electric property of NMOS tube.
As the above analysis, if etching technics can be improved to the quarter between initial hard mask layer and nitridation coat of metal
Erosion selection ratio can then reduce the thickness of the nitridation coat of metal of loss, the first metal gates is prevented to be exposed to etching environment
In.
For this purpose, the embodiment of the present invention also provides a kind of forming method of semiconductor devices, provide including first area, second
The substrate in region and third region is formed with the first pseudo- grid, second area part base on the first area part of substrate
The second metal gates are formed on bottom, the first area and second area substrate surface are formed with interlayer dielectric layer, and described
Interlayer dielectric layer is also covered in the first pseudo- grid sidewall surfaces and the second metal gates sidewall surfaces；To the second metal gates table
Face carries out nitrogen treatment, converts nitridation coat of metal for the second metal gates of segment thickness；In third region base
On bottom, the first pseudo- grid surface, nitridation metal coating layer surface and inter-level dielectric layer surface form initial gallium nitride layer；Using
Dry etch process etches the initial gallium nitride layer, forms the gallium nitride layer being located on third substrate areas, the gallium nitride
Layer exposes the first pseudo- grid surface, nitridation metal coating layer surface and first area and second area inter-level dielectric layer surface,
And the etching technics is more than or equal to 10 to the etching selection ratio of initial gallium nitride layer and nitridation coat of metal；With the nitridation
Gallium layer is exposure mask, and the pseudo- grid of etching removal described first form the first opening in the first area interlayer dielectric layer；Formation is filled out
The first metal gates full of first opening.The present invention is formed after gallium nitride layer compared with forming gallium nitride layer before
The thickness of nitridation coat of metal be kept approximately constant so that nitridation coat of metal can play enough protections the
The effect of two metal gates prevents the second metal gates to be damaged, and then improves the electric property of semiconductor devices and reliable
Property.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 5 to Figure 12 be another embodiment of the present invention provides semiconductor devices forming process the schematic diagram of the section structure.
With reference to Fig. 5, substrate 200 is provided, the substrate 200 includes first area I, second area II and third region III,
It is formed with the first pseudo- grid 212 on the first area I part of substrate 200, is formed on the second area II part of substrate 200
Second pseudo- grid 222, the first area I and 200 surface of second area II substrate are formed with interlayer dielectric layer 201, and the layer
Between dielectric layer 201 be also covered in the sidewall surfaces of the first pseudo- 212 sidewall surfaces of grid and the second pseudo- grid 222.
The material of the substrate 200 is silicon, germanium, SiGe, GaAs, silicon carbide or gallium indium；The substrate 200 may be used also
Think the germanium substrate on the silicon substrate or insulator on insulator.In the present embodiment, the material of the substrate 200 is silicon.
The first area I is NMOS area or PMOS area, and the second area II is NMOS area or PMOS area；
The first area I and second area II can be adjacent or interval.The area type of the first area I and second area II
Difference, when the first area I is NMOS area, the second area II is PMOS area, when the first area I is
When PMOS area, the second area II is NMOS area.It in an embodiment of the present invention, is NMOS with the first area I
Region, second area II be PMOS area do it is exemplary illustrated, it is subsequent NMOS area formed NMOS tube, formed in PMOS area
PMOS tube.
The third region III is the region for being formed with the region of other devices or being other devices to be formed, described
Other devices refer to the NMOS tube or PMOS tube that non-the present embodiment is formed.The present embodiment is with 200 surface of third region III substrate
Example is used as by the covering of interlayer dielectric layer 201.
Fleet plough groove isolation structure, the packing material of the fleet plough groove isolation structure can also be formed in the substrate 200
For silica, silicon nitride or silicon oxynitride.
The material of described first pseudo- grid 212 is polysilicon, silicon nitride or amorphous carbon；The material of the second pseudo- grid 222 is
Polysilicon, silicon nitride or amorphous carbon.In the present embodiment, the material of the described first pseudo- grid 212 is polysilicon, the second pseudo- grid 222
Material is polysilicon.
In the present embodiment, the first gate dielectric layer 211, the second pseudo- grid are also formed between the first pseudo- grid 212 and substrate 200
The second gate dielectric layer 221 is also formed between 222 and substrate 200, wherein the first gate dielectric layer 211 and the second gate dielectric layer 221
Material be high-k gate dielectric material, it is normal with respect to dielectric that high-k gate dielectric material refers to that relative dielectric constant is greater than silica
Several gate dielectric material, for example, high-k gate dielectric material can be HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、
ZrO2Or Al2O3。
The technique of the pseudo- grid 212 of subsequent etching first causes to damage to the first gate dielectric layer 211 in order to prevent, can also be the
Etching barrier layer is formed between one gate dielectric layer 211 and the first pseudo- grid 212, it is similarly pseudo- in the second gate dielectric layer 221 and second
Etching stop layer is formed between grid 222, the material of the etching stop layer can be TiN or TaN.
In other embodiments, first gate dielectric layer and the second gate dielectric layer may be pseudo- gate dielectric layer, subsequent
Etching the first gate dielectric layer of removal while etching the first pseudo- grid of removal, etching removal while etching the second pseudo- grid of removal
Second gate dielectric layer；Then, before forming the first metal gates, the first high-k gate dielectric layer is re-formed, is forming the second gold medal
Before belonging to grid, the second high-k gate dielectric layer is re-formed.
In the present embodiment, the material of the interlayer dielectric layer 201 is silica, and the material of interlayer dielectric layer 201 can also be with
For silicon nitride or silicon oxynitride.The pseudo- grid 212 of the interlayer dielectric layer 201, first are flushed with the second pseudo- 222 top surface of grid.
In a specific embodiment, the pseudo- grid 212 of the first gate dielectric layer 211, first, the second gate dielectric layer 221, the are formed
The processing step of two pseudo- grid 222 and interlayer dielectric layer 201 includes：Gate dielectric film, Yi Jiwei are formed on 200 surface of substrate
Pseudo- grid film in gate dielectric film surface；The graphical pseudo- grid film forms and is located at the of 200 surface of first area I part of substrate
One gate dielectric layer 211 and the first pseudo- grid 212 positioned at 211 surface of the first gate dielectric layer, form and are located at the part second area II
Second gate dielectric layer 221 on 200 surface of substrate and the second pseudo- grid 222 positioned at 221 surface of the second gate dielectric layer；Then, exist
First area I, second area II and 200 surface of third region III substrate form interlayer dielectric layer 201, the interlayer dielectric layer
201 are covered in the first pseudo- 212 sidewall surfaces of grid and the second 222 sidewall surfaces of pseudo- grid；The interlayer dielectric layer 201 is planarized,
Until being flushed at the top of 201 top of interlayer dielectric layer and the first pseudo- grid 222 of pseudo- grid 212, second.
With reference to Fig. 6, the pseudo- grid 222 (referring to Fig. 5) of etching removal described second, in second area II interlayer dielectric layer 201
Form the second opening；Form the second metal gates of full second opening of filling.
Using the pseudo- grid 222 of dry etch process etching removal described second, the etching gas of dry etch process includes
CF4、HBr、Cl2、HCl、O2、CHF3、NF3Or SF6One or more of.
In the present embodiment, the technological parameter of the pseudo- grid 222 of etching removal second is：Etching gas is HBr, O2And Cl2, also to
He is passed through in etching cavity, etching cavity pressure is 2 millitorrs to 50 millitorrs, and the source power of etching is 200 watts to 2000 watts, etching
Biasing power is 10 watts to 100 watts, and HBr flow is 50sccm to 500sccm, O2Flow is 2sccm to 20sccm, Cl2Flow
For 10sccm to 300sccm, He flow is 50sccm to 500sccm.
In order to improve the work function of the second metal gates to improve the driveability of PMOS tube, the second metal gates packet
It includes：Positioned at the second work-function layer 223 of the second open bottom and sidewall surfaces, it is located at 223 surface of the second work-function layer and filling
Second metallic object layer 224 of full second opening.Second metallic object layer, 224 top and second area II interlayer dielectric layer 201
Surface flushes.
Wherein, the material work functions range of the second work-function layer 223 be 5.1ev to 5.5ev, for example, 5.2ev, 5.3ev or
5.4ev.The material of second work-function layer 223 is one or more of TiN, TaN, TaSiN, TiSiN, TaAlN or TiAlN；
The material of the second metallic object layer 224 is Al, Cu, Ag, Au, Pt, Ni, Ti or W.
In the present embodiment, the material of the second work-function layer 223 is TiN, and the material of the second metallic object layer 224 is Al.Second
The second gate dielectric layer 221 is also formed between metal gates and substrate 200.
With reference to Fig. 7, nitrogen treatment is carried out to second metal gates surface, the second metal gates of segment thickness are turned
Turn to nitridation coat of metal 225.
In the present embodiment, nitridation metal is converted by the second metallic object layer 224 of segment thickness in the second metal gates and is protected
Sheath 225.
It is subsequent to will form the initial gallium nitride layer for being covered in 224 surface of the second metallic object layer, then use dry etching work
Skill etching removal is located at the initial gallium nitride layer on 224 surface of the second metallic object layer, forms the gallium nitride for being located at third region III
Layer, the etching gas of the dry etching includes Cl2；After etching initial gallium nitride layer, 224 surface of the second metallic object layer will
It is exposed in etching environment, so that Cl2Into in the second metallic object layer 224, cause that electrification will occur in the second metallic object layer 224
It learns reaction and is corroded.
For this purpose, the present embodiment forms nitridation coat of metal 225, the nitridation metal on 224 surface of the second metallic object layer
Protective layer 225 can stop Cl2Into in the second metallic object layer 224, so that the second metallic object layer 224 be prevented to be corroded.
When the material of second metallic object layer 224 is copper, the material of the nitridation coat of metal 225 of formation is copper nitride.This
In embodiment, the material of the second metallic object layer 224 is aluminium, and the material of the nitridation coat of metal 225 of formation is aluminium nitride.
Using N2O and NH3Carry out the nitrogen treatment.In the present embodiment, the treatment temperature of the nitrogen treatment is taken the photograph for 300
Family name's degree is to 1000 degrees Celsius, for example, 500 degrees Celsius, 600 degrees Celsius or 800 degrees Celsius.
If the thickness of the nitridation coat of metal 225 formed is excessively thin, metal is nitrogenized in subsequent etching process
Protective layer 225 is easy the removal that is etched, and does not have the effect of the second metallic object layer 224 of protection；If the nitridation metal coating formed
The thickness of layer 225 is blocked up, then the thickness of remaining second metallic object layer 224 is excessively thin, leads to the degradation of the second metal gates.
For this purpose, formed in the present embodiment nitridation coat of metal 225 with a thickness of 10 angstroms to 100 angstroms.
With reference to Fig. 8, in the third region III substrate 200, the first 212 surface of pseudo- grid, nitridation coat of metal 225
Surface and 201 surface of interlayer dielectric layer form initial gallium nitride layer 202.
In the present embodiment, third region III substrate 200 is covered by interlayer dielectric layer 201, therefore third region III's is first
Beginning gallium nitride layer 202 is located at 201 surface of interlayer dielectric layer of third region III.
Subsequent to use dry etch process, etching removal is located at the initial gallium nitride layer of first area I and second area II
202, the first pseudo- grid 212 and the second metal gates surface are exposed, the nitridation being located in third region III substrate 200 is formed
Gallium layer is formed by exposure mask of the gallium nitride layer as the pseudo- grid 212 of subsequent etching removal first, and plays protection third region III
Effect.
Since dry etch process is to the etching selection ratio between initial gallium nitride layer 202 and nitridation coat of metal 225
It is higher, while etching removal is located at initial gallium nitride layer 202 on nitridation 225 surface of coat of metal, it can be avoided described
Dry etch process causes to etch to nitridation coat of metal 225, so that subsequent in the process for etching initial gallium nitride layer 202
In, the thickness of nitridation coat of metal 225 remains unchanged, so that nitridation coat of metal 225 be prevented to be etched, avoids the second gold medal
Belong to body layer 224 to be exposed in etching environment, the second metallic object layer 224 is avoided to be corroded.
The prior art generallys use material of the titanium nitride layer as the pseudo- grid of etching removal first.Nitrogen is covered in firstly, being formed
Change the initial titanium nitride layer of coat of metal and inter-level dielectric layer surface, is then located at using dry etch process etching removal
The initial titanium nitride layer for nitrogenizing metal coating layer surface and the first pseudo- grid surface, forms the titanium nitride layer for being located at third region.
However, being carved since dry etch process is relatively low to the etching selection between titanium nitride layer and nitridation coat of metal
During erosion forms titanium nitride layer, the dry etch process easily etching removal completely nitrogenizes coat of metal, so that the
Two metallic object layers are exposed in etching environment, and the second metallic object layer is caused to corrode；Alternatively, the dry etch process etching
The nitridation coat of metal thickness of removal is blocked up, therefore during the pseudo- grid of subsequent etching first, remaining nitridation metal is protected
Sheath is also easy the removal that is etched, and causes the second metallic object layer to be exposed in the etching environment of the pseudo- grid of etching first, and then also can
Second metallic object layer is caused to damage.
The initial gallium nitride layer is formed using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process.This
In embodiment, use chemical vapor deposition process formed the technological parameter of the initial gallium nitride layer for：Gallium source and nitrogen are provided
Source, wherein gallium source is (C2H5)3Ga、(CH3)3Ga or (C4H9)3Ga, nitrogen source NH3, reaction chamber temperature be 600 degrees Celsius extremely
1000 degrees Celsius.
It is subsequent during etching the first pseudo- grid 212 of removal if the thickness of initial gallium nitride layer 202 is excessively thin, first
Pseudo- grid 212 have not been disappeared by gallium nitride layer when all etching removals also；If the thickness of initial gallium nitride layer 202 is blocked up, after
Overlong time needed for the continuous initial gallium nitride layer 202 of etching.
For this purpose, initial gallium nitride layer 202 described in the present embodiment with a thickness of 50 angstroms to 500 angstroms.
It is formed using the dry etch process etching initial gallium nitride layer 202 (referring to Fig. 8) with reference to Fig. 9 and is located at third
Gallium nitride layer 203 in region III substrate 200, the gallium nitride layer 203 exposes the first 212 surface of pseudo- grid, nitridation metal is protected
225 surface of sheath and first area I and 201 surface of second area II interlayer dielectric layer.
The present embodiment is formed after then etching since III substrate 200 surface in third region is formed with interlayer dielectric layer 201
Gallium nitride layer 203 is located at 201 surface of third region III interlayer dielectric layer.
Specifically, forming patterned photoresist layer 204 on initial 202 surface of gallium nitride layer；With the patterned light
Photoresist layer 204 is exposure mask, and etching removal is located at the first 212 surface of pseudo- grid, nitridation 225 surface of coat of metal and the firstth area
The initial gallium nitride layer 202 on 201 surface domain I and second area II interlayer dielectric layer forms and is located at third region III inter-level dielectric
The gallium nitride layer 203 on 201 surface of layer.
The etching gas of the dry etch process includes Cl2.Also, dry etch process is to first described in the present embodiment
Etching selection ratio between beginning gallium nitride layer 202 and nitridation coat of metal 225 is more than or equal to 10, therefore in the nitridation metal
After 225 surface of protective layer is exposed, the dry etch process is very small to the etch rate of nitridation coat of metal 225
It even can be ignored, so that the thickness of the nitrided metal layer 225 after dry etching is almost protected compared with before dry etching
Hold it is constant, so that 224 surface of the second metallic object layer be avoided to be exposed in dry etching environment.
Simultaneously as second metallic object layer, 224 surface still has the nitrogen of adequate thickness after forming gallium nitride layer 203
Change coat of metal 225, so that the nitridation coat of metal 225 during pseudo- grid 212 of subsequent etching first be avoided to be etched
It removes, the second metallic object layer 224 is avoided to be exposed in 212 environment of pseudo- grid of etching first.
In the present embodiment, etching selection of the etching technics to initial gallium nitride layer 202 and nitridation coat of metal 225
Than being more than or equal to 10 and being less than or equal to 40；The dry etch process is inductively coupled plasma body (ICP, (Inductive
Coupling Plasma) etching.
In inductive coupling induction etching process, except offer Cl2Outside, DC offset voltage is also provided, forms inductance
The source power and etching cavity pressure of coupled plasma.
It has been investigated that if Cl2Flow is excessive, then etch rate of the dry etch process to nitridation coat of metal 225
It will be bigger.For this purpose, Cl in the present embodiment2Flow be 10sccm to 30sccm, for example, 15sccm, 20sccm or
25sccm。
The density of Cl plasma increases with the increase of source power, to enhance ion physical sputtering and etching table
The reaction rate in face, so that etching technics adds the etch rate of initial gallium nitride layer 202 and nitridation coat of metal 225
Fastly, and the degree accelerated of the etch rate of initial gallium nitride layer 202 is bigger, improve etching technics to initial gallium nitride layer 202 with
Nitrogenize the etching selection ratio of coat of metal 202；When source power becomes excessive, the etch rate of coat of metal 225 is nitrogenized
The degree of quickening can also become very big, therefore etching technics is to initial gallium nitride layer 202 and nitridation coat of metal 225
Etching selection ratio reduces.For this purpose, source power is 100 watts to 1100 watts, for example, 300 watts, 500 watts, 800 watts in the present embodiment
Or 1000 watts.
When DC offset voltage is less than or equal to 20V, since the increase of bias voltage produces what more orientations accelerated
Cl plasma improves etching technics to initial so that etching technics increases the etch rate of initial gallium nitride layer 202
The etching selection ratio of gallium nitride layer 202 and nitridation coat of metal 225；And after DC offset voltage is greater than 20V, due to Cl etc.
The energy of gas ions is excessive, is just adsorbed so that Cl plasma does not also perform etching initial gallium nitride layer 202, because this moment
Etching technique reduces the etching selection ratio of initial gallium nitride layer 202 and nitridation coat of metal 225.For this purpose, in the present embodiment, directly
Stream bias voltage is 10V to 50V, for example, 15V, 20V, 30V or 40V.
In a specific embodiment, the technological parameter of the inductively coupled plasma etching technique is：Offer source function
Rate is 100 watts to 1100 watts, and direct current biasing power is 10V to 50V, and etching cavity pressure is 1 millitorr to 20 millitorrs, Cl2Flow
For 10sccm to 30sccm, Ar can also be passed through into etching cavity, Ar flow is 0sccm to 15sccm.
After forming the gallium nitride layer 203, patterned photoresist layer 204 is removed.
It is exposure mask with the gallium nitride layer 203 with reference to Figure 10, the pseudo- grid 212 (referring to Fig. 9) of etching removal described first,
The first opening 205 is formed in the first area I interlayer dielectric layer 201.
The technique of the pseudo- grid 212 of etching removal described first can refer to the technique of the pseudo- grid 222 of aforementioned etching removal second, herein
It repeats no more.
Due to aforementioned after forming gallium nitride layer 203,224 surface of the second metallic object layer still has thicker nitridation metal
Protective layer 225, therefore during etching the described first pseudo- grid 212, nitridation coat of metal 225 can play the second gold medal of protection
The effect for belonging to body layer 224 prevents the second metallic object layer 224 to be exposed in the etching environment of the pseudo- grid 212 of etching first, to avoid
The second metallic object layer 224 is by etching injury, so that the second metallic object layer 224 keeps higher performance.
With reference to Figure 11, using CF4Gas performs etching post-processing (PET, Post Etch to first opening 205
Treatment)。
Aforementioned to will form etch by-products in etching formation 205 processes of the first opening, partial etching by-product can leave quarter
Chamber is lost, and 205 bottom and side wall surface of the first opening can be attached under the effect of gravity there are also partial etching by-product.After if
Continuous directly to form the first metal gates in the first opening 205, then the etch by-products adhered to can be to the first metal gates performance
Cause adverse effect.
For this purpose, the present embodiment performs etching post-processing before forming the first metal gates, to the first opening 205, etch
Etch by-products in the first opening 205 of removal.
In the etching last handling process of the present embodiment, it is desirable that quarter of the post-etch treatment process to nitridation coat of metal 225
It is smaller to lose rate, so that still thering is the nitridation coat of metal 225 of thicker degree to be covered in the second metal after handling after etching
224 surface of body layer avoids the second metallic object layer 224 from being exposed in external environment.
After etching in treatment process, CF is provided into reaction chamber4, also offer Ar, reaction chamber is with certain pressure
By force, it is also necessary to which RF source power is provided.
If reaction chamber pressure is too low, etch post-processing to nitridation coat of metal 225 etch rate it is excessive, thus
Reaction chamber pressure is 0.2 support to 1 support, for example, 0.4 support, 0.6 support to 0.8 support in the present embodiment.
If the RF source power provided is too small, the ability of the etch by-products in the first opening of post-processing removal is etched
It is low；If the RF source power provided is excessive, etch rate also opposite change of the post-processing to nitridation coat of metal 225 is etched
Greatly.For this purpose, providing RF source power in the present embodiment is 50 watts to 200 watts, for example, 100 watts or 150 watts.
In a specific embodiment, the technological parameter for etching post-processing is：Reaction chamber pressure is 0.2 support to 1 support, is mentioned
It is 50 watts to 200 watts for RF source power, Ar is also passed through into reaction chamber, wherein Ar and CF4Gas flow ratio be 0 to
0.3, when technique, is 10 seconds to 600 seconds a length of.
With reference to Figure 12, the first metal gates of full first opening 205 (referring to Figure 11) of filling are formed.
In the present embodiment, first area I be NMOS area, in order to improve NMOS tube the first metal gates work function,
First metal gates include：The first work-function layer 213 positioned at the first 205 bottom and side wall surfaces of opening；Positioned at first
First metallic object layer 214 of 213 surface of work-function layer and full first opening 205 of filling, and the first metallic object layer 214
It is flushed at the top of top and first area I interlayer dielectric layer 201.
The material work functions range of first work-function layer 213 be 3.9ev to 4.5ev, for example, 4ev, 4.1ev or
4.3ev.The material of first work-function layer 213 is TiN, Mo, MoN or AlN；The material of the first metallic object layer 214 is
Al, Cu, Ag, Au, Pt, Ni or Ti.
In the present embodiment, the material of first work-function layer 213 is MoN, and the material of the first metallic object layer 214 is Al,
The first gate dielectric layer 211 is formed between first metallic object layer 214 and substrate 200.
In a specific embodiment, the processing step of formation first metal gates includes：In first opening
205 bottom and side wall surfaces form the first work-function layer 213, and first work-function layer 213 is also covered in interlayer dielectric layer
201 surfaces and nitridation 225 surface of coat of metal；The first metallic object layer is formed on 213 surface of the first work-function layer
214, full first opening 205 of the filling of the first metallic object layer 214；Using chemical mechanical milling tech, grinding removal is higher than the
The first metallic object layer 214 and the first work-function layer 213 on one region I interlayer dielectric layer, 201 surface.
During the grinding process, since 224 surface of the second metallic object layer is formed with nitridation coat of metal 225, the nitridation
Coat of metal 225 can prevent grinding technics from causing to damage to the second metallic object layer 224, so that the second metallic object layer
224 keep good performance.
It is covered always by nitridation coat of metal 225 by the second metallic object layer 224 in this present embodiment, avoids the second gold medal
Belonging to body layer 224 to be corroded or be damaged, the electric property of the PMOS tube of second area II is good thus, so that formed
Semiconductor devices has good electric property.
In other embodiments, the pseudo- grid of removal first can also first be etched, form the first metal gates, it then will be partially thick
First metal gates of degree are converted into nitridation coat of metal；Then the pseudo- grid of removal second are performed etching, form the second metal gate
The processing step of pole.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of forming method of semiconductor devices, which is characterized in that including：
There is provided include first area, second area and third region substrate, the is formed on the first area part of substrate
One pseudo- grid are formed with the second metal gates, the first area and second area substrate table on the second area part of substrate
Face is formed with interlayer dielectric layer, and the interlayer dielectric layer is also covered in the first pseudo- grid sidewall surfaces and the second metal gates side wall
Surface；
Nitrogen treatment is carried out to second metal gates surface, converts nitridation metal for the second metal gates of segment thickness
Protective layer, it is described nitridation coat of metal with a thickness of 10 angstroms to 100 angstroms；
On the third substrate areas, the first pseudo- grid surface, nitrogenize metal coating layer surface and inter-level dielectric layer surface shape
At initial gallium nitride layer, the initial gallium nitride layer with a thickness of 50 angstroms to 500 angstroms；
The initial gallium nitride layer is etched using dry etch process, exposes the first pseudo- grid surface and nitridation coat of metal
Surface forms the gallium nitride layer being located on third substrate areas；
Using the gallium nitride layer as exposure mask, the pseudo- grid of etching removal described first are formed in the first area interlayer dielectric layer
First opening；
Form the first metal gates of full first opening of filling.
2. the forming method of semiconductor devices according to claim 1, which is characterized in that the quarter of the dry etch process
Losing gas includes Cl2；The dry etch process is greater than the etching selection ratio of initial gallium nitride layer and nitridation coat of metal
Equal to 10.
3. the forming method of semiconductor devices according to claim 2, which is characterized in that the dry etch process is electricity
Feel coupled plasma etch.
4. the forming method of semiconductor devices according to claim 3, which is characterized in that the inductively coupled plasma body
The technological parameter of etching technics is：There is provided source power is 100 watts to 1100 watts, and direct current biasing power is 10V to 50V, etch chamber
Chamber pressure is 1 millitorr to 20 millitorrs, Cl2Flow is 10sccm to 30sccm, Ar is also passed through into etching cavity, Ar flow is
0sccm to 15sccm.
5. the forming method of semiconductor devices according to claim 3, which is characterized in that the etching technics is to initial nitrogen
Change gallium layer and nitrogenizes the etching selection ratio of coat of metal more than or equal to 10 and be less than or equal to 40.
6. the forming method of semiconductor devices according to claim 1, which is characterized in that use chemical vapor deposition, object
Physical vapor deposition or atom layer deposition process form the initial gallium nitride layer.
7. the forming method of semiconductor devices according to claim 6, which is characterized in that use chemical vapor deposition process
The technological parameter for forming the initial gallium nitride layer is：There is provided gallium source and nitrogen source, wherein gallium source is (C2H5)3Ga、(CH3)3Ga
Or (C4H9)3Ga, nitrogen source NH3, reaction chamber temperature is 600 degrees Celsius to 1000 degrees Celsius.
8. the forming method of semiconductor devices according to claim 1, which is characterized in that use N2O and NH3Progress described in
Nitrogen treatment；The treatment temperature of the nitrogen treatment is 300 degrees Celsius to 1000 degrees Celsius.
9. the forming method of semiconductor devices according to claim 1, which is characterized in that the second metal gates packet
It includes：Second work-function layer and the second metallic object layer positioned at the second work-function layer surface, and the second metallic object layer and
It is flushed at the top of two region interlayer dielectric layers.
10. the forming method of semiconductor devices according to claim 9, which is characterized in that by the of the segment thickness
Two metal gates are converted into the method for nitrogenizing coat of metal：Nitridation metal is converted by the second metallic object layer of segment thickness
Protective layer.
11. the forming method of semiconductor devices according to claim 9, which is characterized in that the second metallic object layer
Material includes copper, aluminium or tungsten.
12. the forming method of semiconductor devices according to claim 9, which is characterized in that the second metallic object layer
When material is aluminium, the material of the nitridation coat of metal is aluminium nitride.
13. the forming method of semiconductor devices according to claim 1, which is characterized in that forming first opening
Later, it is formed before first metal gates, further includes step：Using CF4Gas performs etching post-processing to the first opening.
14. the forming method of semiconductor devices according to claim 13, which is characterized in that the work of the etching post-processing
Skill parameter is：Reaction chamber pressure is 0.2 support to 1 support, and providing RF source power is 50 watts to 200 watts, also into reaction chamber
It is passed through Ar, wherein Ar and CF4Gas flow ratio be 0 to 0.3, when technique, is 10 seconds to 600 seconds a length of.
15. the forming method of semiconductor devices according to claim 1, which is characterized in that the first metal gates packet
It includes：Positioned at the first work-function layer of the first open bottom and sidewall surfaces；Described in the first work-function layer surface and filling completely
First metallic object layer of the first opening, and flushed at the top of the first metallic object layer with first area interlayer dielectric layer top.
16. the forming method of semiconductor devices according to claim 1, which is characterized in that first metal gates with
The first gate dielectric layer is formed between substrate；The second gate dielectric layer is formed between second metal gates and substrate.
17. the forming method of semiconductor devices according to claim 1, which is characterized in that the first area is NMOS
Region or PMOS area；The second area is NMOS area or PMOS area, and the area of the first area and second area
Field type is different.
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| US6171910B1 (en) * | 1999-07-21 | 2001-01-09 | Motorola Inc. | Method for forming a semiconductor device |
| CN102683282A (en) * | 2011-03-10 | 2012-09-19 | 联华电子股份有限公司 | Manufacturing method of semiconductor element with metal gate |
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