CN105810817A - Resistive device of two-dimensional nanosheet-layer MoS2 vertical structure - Google Patents

Resistive device of two-dimensional nanosheet-layer MoS2 vertical structure Download PDF

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CN105810817A
CN105810817A CN201610374450.6A CN201610374450A CN105810817A CN 105810817 A CN105810817 A CN 105810817A CN 201610374450 A CN201610374450 A CN 201610374450A CN 105810817 A CN105810817 A CN 105810817A
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layer
electrode
dimensional nano
sputtering
mos
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张楷亮
张志超
王芳
冯玉林
方明旭
袁育杰
赵金石
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Tianjin University of Technology
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors
    • H10N70/24Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/881Switching materials
    • H10N70/882Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8822Sulfides, e.g. CuS

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  • Semiconductor Memories (AREA)

Abstract

Disclosed is a resistive device of a two-dimensional nanosheet-layer MoS2 vertical structure. The resistive device is characterized in that the vertical structure is composed of an oxidized wafer, a Ti adhesion layer 2-5 nm in thickness, a lower electrode 50-200 nm in thickness, a resistive layer, an upper electrode 50-200 nm in thickness and an upper electrode SiO2 protecting layer 5-10 nm in thickness, wherein the resistive layer is two-dimensional nanosheet-layer MoS2 of a 'sandwich' laminated structure, and the two-dimensional nanosheet-layer MoS2 is 0.65-10 nm in thickness. The resistive device has the advantages that the two-dimensional nanosheet-layer MoS2 acts as the resistive layer of the resistive device, so that a dielectric layer material system in a resistive random access memory is expanded and application blank of the two-dimensional nanosheet-layer MoS2 in the resistive random access memory is filled; the resistive device of the pure vertical laminated structure is simple to manufacture, low in cost and easy to integrate.

Description

A kind of two-dimensional nano lamella MoS2Vertical stratification resistive device
Technical field
The present invention relates to inorganic advanced nano film material and microelectronics technology, be specifically related to a kind of two wieners Rice lamella MoS2Vertical stratification resistive device.
Technical background
Along with the arrival of semi-conductor industry 22nm technology node, traditional, nonvolatile memories based on silicon materials Memory density become closer to its intrinsic limit.Resistance-variable storing device (RRAM) has height as one The novel nonvolatile memory of density storage potentiality has developed very rapid since late 1990s, tool Have simple in construction, size can contractility speed good, erasable is fast, repeat erasable number of times height, data hold time length, The many merits such as multilevel storage and three-dimensional storage potentiality, receive the extensive concern of research worker, have very in recent years The design of many new structures and the proposition of new material, be the strong competitor of non-volatility memorizer of future generation.
Electric resistance changing refers to that the resistance of material exists two or more Resistance states under voltage (electric field) acts on, And the change of this resistance not time to time change.Generally device is converted to this of low resistance state from high-impedance state Process is referred to as set process, otherwise, the process that device is converted to high-impedance state from low resistance state calls reset process.
The initial stage that the R&D work of resistance-variable storing device is verified also in material development and device, many problems are also Needing to solve, wherein dielectric material has for the performance of resistance-variable storing device the most directly affects.
Simultaneously, two-dimensional nano lamella molybdenum bisuphide causes as a kind of important two-dimensional layer nano material The concern of numerous scientific research personnel, two-dimensional nano lamella molybdenum bisuphide has " sandwich " layer structure, middle One layer is molybdenum atom, and upper and lower two-layer is sulphur atom, and molybdenum atom is formed class " sandwich " folded by two-layer sulphur atom Structure, molybdenum atom is combined formation two-dimensional atomic crystal with sulphur atom with covalent bond.Two-dimensional nano lamella molybdenum bisuphide There is regulatable band gap, have vast potential for future development at field of photoelectric devices.
2011, Radisavljevic et al. was at Integrated circuits and logic operations based on single-layer MoS2In be prepared for two-dimensional semiconductor MoS first2Integrated circuit, this integrated circuit can be used as Phase inverter.2013, Zhang et al. was at article Graphene-Like Molybdenum Disulfide and Its By molybdenum disulfide powder is placed in polyvinylpyrrolidone in Application in Optoelectronic Devices In ketone (PVP) and the mixed solution of ethanol ultrasonic, obtain MoS2The nano-complex of-PVP is also successfully prepared Flash-type memory part.
According to above-mentioned technical background, two-dimensional nano lamella MoS2Application in terms of resistance-variable storing device does not also have, The present invention is prepared for a kind of two-dimensional nano lamella MoS2Vertical stratification resistive device, has filled up the blank of this respect.
Summary of the invention
It is an object of the invention to for two dimension MoS at present2The blank existed in terms of resistance-variable storing device, it is provided that A kind of two-dimensional nano lamella MoS2Vertical stratification resistive device, by using two-dimensional nano lamella to deposit as resistive The change resistance layer of reservoir, by two-dimensional nano lamella MoS2It is applied to resistance-variable storing device.
Technical scheme:
A kind of two-dimensional nano lamella MoS2Vertical stratification resistive device, by oxidized silicon chip substrate, Ti adhesion layer, Bottom electrode, change resistance layer, upper electrode and upper electrode SiO2Protective layer composition vertical stratification, wherein change resistance layer is tool There is the two-dimensional nano lamella MoS of " sandwich " layer structure2, each layer thickness is respectively as follows: Ti adhesion layer 2-5nm, bottom electrode 50-200nm, two-dimensional nano lamella MoS20.65-10nm, upper electrode 50-200nm, Upper electrode SiO2Protective layer 5-10nm.
Described upper and lower electrode material is conducting metal, metal alloy, conductive metallic compound and carbon electrode/silicon electricity Pole, wherein conducting metal is Ta, Cu, Ag, W, Ni, AL or Pt;Metal alloy is Pt/Ti, Ti/Ta, Cu/Ti, Cu/Au, Cu/AL or AL/Zr;Conductive metallic compound is TaN, TiN, ITO, FTO, AZO Or GZO;Carbon electrode/silicon electrode includes in Graphene, CNT, p-Si or n-Si.
A kind of described two-dimensional nano lamella MoS2The preparation method of vertical stratification resistive device, with titanium dioxide silicon chip As substrate, the method first with ion beam sputtering prepares Ti adhesion layer, then on silicon dioxide insulating layer Ti adhesion layer is prepared MoS2Vertical stratification resistive device, step is as follows:
1) utilizing the method for ion beam sputtering to prepare Ti adhesion layer in silicon dioxide substrates, sputtering condition is: With metallic target as target, base vacuum is less than 10-4Pa, underlayer temperature 18-500 DEG C, operating pressure 0.1-2Pa, Discharge voltage 50-100V, heater current 0.1-0.5A, accelerating potential 100V, line 4-6A;
2) electricity under being prepared by magnetron sputtering method, ion beam sputtering or electron-beam vapor deposition method on Ti adhesion layer Pole, magnetron sputtering condition is: with metallic target as target, and base vacuum is less than 10-4Pa, underlayer temperature 18-500 DEG C, Operating pressure 0.1-2Pa, sputtering power 40-250W;Ion beam sputtering condition is: with metallic target as target, Base vacuum is less than 10-4Pa, underlayer temperature 18-500 DEG C, operating pressure 0.1-2Pa, discharge voltage 50-100V, Heater current 0.1-0.5A, accelerating potential 100V, line 4A-6A;Electron beam evaporation process condition is: this End vacuum is less than 10-4Pa, the metal using fusing point relatively low is evaporation source, and mode of heating is crucible heating or electronics Shu Jiare;
3) mechanical stripping method, chemical vapour deposition technique, liquid phase stripping method, high temperature vulcanized is used on the bottom electrode Method, hydro-thermal method or atomic layer deposition method growth two-dimensional nano lamella molybdenum bisuphide, wherein, chemical gaseous phase deposition bar Part is: pressure be normal pressure, temperature 500-750 DEG C, growth time be 5-15min, the rate of heat addition be 10-20 DEG C /min;
4) on oxidized silicon chip, electrode in the process deposits of magnetron sputtering or electron beam evaporation is used, by preparation Upper electrode is by Cu line and two-dimensional nano lamella MoS2Being connected, on magnetron sputtering, the process conditions of electrode are: With metallic target as target, base vacuum is less than 10-4Pa, underlayer temperature are 18-500 DEG C, operating pressure is 0.1-2Pa, Sputtering power is 40-250W;Electron beam evaporation process condition is: base vacuum is less than 10-4Pa, uses eutectic Point metal is evaporation source, and mode of heating is the heating of dry pot or electron beam heating;
5) method one layer of SiO of growth of PECVD is utilized at upper electrode2As protective layer, technological parameter is: Base vacuum is less than 10-5Pa, operating pressure are 0.1-5Pa, radio-frequency power is 50-300W, reacting gas is SiH4And N2O, SiH4Flow is 50-600sccm, N2O flow is 20-50sccm.
The technical Analysis of the present invention:
The invention provides a kind of two-dimensional nano lamella MoS2Vertical stratification resistive device, change resistance layer have employed two Dimension nanoscale twins MoS2As change resistance layer, when power on extremely Ag, Cu or Ni isoreactivity electrode time, in two dimension Nanoscale twins MoS2The middle metallic conduction filament forming connection upper/lower electrode, under DC Electric Field, metal The formation of conductive filament and rupture and result in different resistance states, additionally electrode and two-dimensional nano lamella MoS2 Between formed Schottky barrier, under DC Electric Field, the change of schottky barrier height result also in device Different resistance states.
Advantages of the present invention and providing the benefit that:
1) this resistive device uses two-dimensional nano lamella MoS2As the change resistance layer of resistance-variable storing device, extend Dielectric layer material system in resistance-variable storing device, has filled up two-dimensional nano lamella MoS2Should in resistance-variable storing device Blank;
2) this resistive device is simple vertical stack structure, makes simple, with low cost and is easily integrated.
Accompanying drawing explanation
Fig. 1 is this two-dimensional nano lamella MoS2Vertical stratification resistance variation memory structure schematic diagram.
In figure: 1. oxidized silicon chip substrate 2.Ti adhesion layer 3. bottom electrode 4. two-dimensional nano lamella MoS2 5. go up electrode SiO on electrode 6.2Protective layer
Fig. 2 is this two-dimensional nano lamella MoS2The current-voltage characteristic curve of vertical stratification resistance-variable storing device, Under forward voltage effect, there is set process in this resistive device, device resistance state becomes low-resistance from high resistant, at negative sense Under voltage, there is reset process in this device, and device resistance state becomes high resistant from low-resistance, and above change illustrates, should Two-dimensional nano lamella MoS2Vertical stratification resistive memory possesses ambipolar resistance transformation characteristic.
Detailed description of the invention
Embodiment 1:
A kind of two-dimensional nano lamella MoS2Vertical stratification resistance-variable storing device, as it is shown in figure 1, served as a contrast by oxidized silicon chip The end, Ti adhesion layer thick for 5nm, TiN thick for 100nm are as bottom electrode, the two-dimensional nano lamella of 0.65nm MoS2The Cu thick with 100nm is constituted as upper electrode.
The preparation method of this vertical stratification resistance-variable storing device, first with silicon chip as substrate, the method utilizing thermal oxide Preparing layer of silicon dioxide insulating barrier on silicon chip, the method for recycling ion beam sputtering is at silicon dioxide insulating layer Upper preparation Ti adhesion layer, then prepares this vertical structure device on Ti adhesion layer, and step is as follows:
1) utilizing the method for ion beam sputtering to prepare Ti adhesion layer in silicon dioxide substrates, sputtering condition is: With metallic target as target, base vacuum is less than 10-4Pa, underlayer temperature 18-500 DEG C, operating pressure 0.1-2Pa, Discharge voltage 50-100V, heater current 0.1-0.5A, accelerating potential 100V, line 4-6A;(parameter takes fixed Value)
2) use reaction magnetocontrol sputtering to prepare the thick TiN hearth electrode of 100nm on Ti adhesion layer, sputter work Skill is: diameterMetal Ti target sputtering target material, sputtering mode is direct current (DC) magnetron sputtering, this End vacuum is less than 5 × 10-4Pa, underlayer temperature be room temperature, operating pressure 0.5Pa, sputtering power be 100w, Reacting gas N2, Ar flow be respectively 2.5,30Sccm;
3) method utilizing chemical gaseous phase to deposit grows nanoscale twins MoS on TiN2, technological parameter is: first First the mixed solution of substrate silicon chip sulphuric acid and hydrogen peroxide is processed, wherein H2SO4: H2O2=3:1, In acetone soln and aqueous isopropanol ultrasonic 10 minutes the most successively, place the MoO of 240mg3At high temperature District, and substrate silicon chip is placed on above it, the S powder of 240mg is placed on the low-temperature space of overdraught. In preparation process, it is passed through noble gas, keeps normal pressure, the temperature of tube furnace is raised to 700 from 100 degrees Celsius Degree Celsius, the rate of heat addition is 15 DEG C/min, temperature is controlled at 700 DEG C in growth course, and growth time is 10 minutes, after having grown, cool the temperature to room temperature.
4) utilize on oxidized silicon chip electron beam evaporation method growth 100nm Cu as on electrode, electricity Sub-beam evaporation condition is: base vacuum is less than 5 × 10-4Pa, using Cu metal is evaporation source, and mode of heating is Electron beam heats.
5) method one layer of SiO of growth of PECVD is utilized at upper electrode2As protective layer, technological parameter is: Base vacuum 5 × 10-4Pa, operating pressure are 3Pa, radio-frequency power is 150W, reacting gas is SiH4With N2O, SiH4Flow is 50sccm, N2O flow is 20sccm.
Electrical testing is tested by Semiconductor Parameter Analyzer, and Fig. 2 is the current-voltage characteristic of this resistance-variable storing device Curve, shows in figure: the electrology characteristic of this device is typical bipolar nature.
Embodiment 2:
A kind of two-dimensional nano lamella MoS2Vertical stratification resistive device, structure is substantially the same manner as Example 1, no Same is with Pt as bottom electrode, and Cu is upper electrode, and thickness is 100nm.
The preparation method of this resistance-variable storing device, the preparation technology of step and Cu electrode is same as in Example 1.
Bottom electrode Pt deposits the Pt bottom electrode of 100nm by the method for electron beam evaporation on Ti adhesion layer, Concrete technology condition is: base vacuum 5 × 10-5Pa, with Pt metal as evaporation source, mode of heating is electron beam Heating.
Electrical testing is tested by Semiconductor Parameter Analyzer, and this device shows typical bipolar nature, turns Time variant voltage is less than 2V.

Claims (3)

1. a two-dimensional nano lamella MoS2Vertical stratification resistive device, it is characterised in that: served as a contrast by oxidized silicon chip The end, Ti adhesion layer, bottom electrode, change resistance layer, upper electrode and upper electrode SiO2Protective layer composition vertical stratification, Wherein change resistance layer is the two-dimensional nano lamella MoS with " sandwich " layer structure2, each layer thickness is respectively For: Ti adhesion layer 2-5nm, bottom electrode 50-200nm, two-dimensional nano lamella MoS20.65-10nm, power on Pole 50-200nm, upper electrode SiO2Protective layer 5-10nm.
Two-dimensional nano lamella MoS the most according to claim 12Vertical stratification resistive device, it is characterised in that: Described upper and lower electrode material is conducting metal, metal alloy, conductive metallic compound and carbon electrode/silicon electrode, Wherein conducting metal is Ta, Cu, Ag, W, Ni, AL or Pt;Metal alloy is Pt/Ti, Ti/Ta, Cu/Ti, Cu/Au, Cu/AL or AL/Zr;Conductive metallic compound be TaN, TiN, ITO, FTO, AZO or GZO;Carbon electrode/silicon electrode includes Graphene, CNT, p-Si or n-Si.
3. a two-dimensional nano lamella MoS as claimed in claim 12The preparation method of vertical stratification resistive device, It is characterized in that using titanium dioxide silicon chip as substrate, first with the method for ion beam sputtering at silicon dioxide insulating layer Upper preparation Ti adhesion layer, then prepares MoS on Ti adhesion layer2Vertical stratification resistive device, step is as follows:
1) utilizing the method for ion beam sputtering to prepare Ti adhesion layer in silicon dioxide substrates, sputtering condition is: With metallic target as target, base vacuum is less than 10-4Pa, underlayer temperature 18-500 DEG C, operating pressure 0.1-2Pa, Discharge voltage 50-100V, heater current 0.1-0.5A, accelerating potential 100V, line 4-6A;
2) electricity under being prepared by magnetron sputtering method, ion beam sputtering or electron-beam vapor deposition method on Ti adhesion layer Pole, magnetron sputtering condition is: with metallic target as target, and base vacuum is less than 10-4Pa, underlayer temperature 18-500 DEG C, Operating pressure 0.1-2Pa, sputtering power 40-250W;Ion beam sputtering condition is: with metallic target as target, Base vacuum is less than 10-4Pa, underlayer temperature 18-500 DEG C, operating pressure 0.1-2Pa, discharge voltage 50-100V, Heater current 0.1-0.5A, accelerating potential 100V, line 4A-6A;Electron beam evaporation process condition is: this End vacuum is less than 10-4Pa, the metal using fusing point relatively low is evaporation source, and mode of heating is crucible heating or electronics Shu Jiare;
3) mechanical stripping method, chemical vapour deposition technique, liquid phase stripping method, high temperature vulcanized is used on the bottom electrode Method, hydro-thermal method or atomic layer deposition method growth two-dimensional nano lamella molybdenum bisuphide, wherein, chemical gaseous phase deposition bar Part is: pressure be normal pressure, temperature 500-750 DEG C, growth time be 5-15min, the rate of heat addition be 10-20 DEG C /min;
4) on oxidized silicon chip, electrode in the process deposits of magnetron sputtering or electron beam evaporation is used, by preparation Upper electrode is by Cu line and two-dimensional nano lamella MoS2Being connected, on magnetron sputtering, the process conditions of electrode are: With metallic target as target, base vacuum is less than 10-4Pa, underlayer temperature are 18-500 DEG C, operating pressure is 0.1-2Pa, Sputtering power is 40-250W;Electron beam evaporation process condition is: base vacuum is less than 10-4Pa, uses eutectic Point metal is evaporation source, and mode of heating is the heating of dry pot or electron beam heating;
5) method one layer of SiO of growth of PECVD is utilized at upper electrode2As protective layer, technological parameter is: Base vacuum is less than 10-5Pa, operating pressure are 0.1-5Pa, radio-frequency power is 50-300W, reacting gas is SiH4And N2O, SiH4Flow is 50-600sccm, N2O flow is 20-50sccm.
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CN107634139A (en) * 2017-08-30 2018-01-26 西安理工大学 A kind of preparation method for resisting big voltage oxide silicon resistance changing film
CN109461813A (en) * 2018-10-09 2019-03-12 河北大学 A kind of resistance-variable storing device and preparation method thereof based on tungsten sulfide nanometer sheet
CN110071215A (en) * 2018-04-03 2019-07-30 东北师范大学 A kind of bipolarity/nonpolarity reversible mutual transition resistance-variable storing device and preparation method thereof
CN110364622A (en) * 2019-07-05 2019-10-22 国家纳米科学中心 Based on stratiform α-MoO3Sandwich of nanometer sheet and preparation method thereof
CN110379922A (en) * 2019-08-20 2019-10-25 西安工业大学 A kind of flexibility Ag/MoS2The preparation method of/Cu resistive formula memory
CN110491991A (en) * 2019-08-20 2019-11-22 西安工业大学 It is a kind of to prepare hydro-thermal method MoS2The method of multistage resistance-variable storing device
CN111883655A (en) * 2020-06-10 2020-11-03 广东工业大学 In2S3Thin-film memristor and application thereof
CN111933794A (en) * 2020-07-02 2020-11-13 北京航空航天大学 MoS based on coexistence of analog type and digital type2Base memristor and preparation method thereof
CN113328036A (en) * 2021-05-21 2021-08-31 西安工业大学 Ag/[ SnS2/PMMA]/Cu low-power-consumption resistive random access memory and preparation method thereof
CN114931864A (en) * 2021-05-08 2022-08-23 淮阴师范学院 Two-dimensional material composite separation membrane, preparation method and application

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CN107634139B (en) * 2017-08-30 2020-01-14 西安理工大学 Preparation method of large-voltage-resistant silicon oxide resistance change film
CN107634139A (en) * 2017-08-30 2018-01-26 西安理工大学 A kind of preparation method for resisting big voltage oxide silicon resistance changing film
CN110071215A (en) * 2018-04-03 2019-07-30 东北师范大学 A kind of bipolarity/nonpolarity reversible mutual transition resistance-variable storing device and preparation method thereof
CN110071215B (en) * 2018-04-03 2022-08-09 东北师范大学 Bipolar/non-polar reversible mutual transformation type resistive random access memory and preparation method thereof
CN109461813A (en) * 2018-10-09 2019-03-12 河北大学 A kind of resistance-variable storing device and preparation method thereof based on tungsten sulfide nanometer sheet
CN109461813B (en) * 2018-10-09 2022-08-19 河北大学 Resistive random access memory based on tungsten sulfide nanosheet and preparation method thereof
CN110364622A (en) * 2019-07-05 2019-10-22 国家纳米科学中心 Based on stratiform α-MoO3Sandwich of nanometer sheet and preparation method thereof
CN110491991B (en) * 2019-08-20 2022-11-08 西安工业大学 Preparation of MoS by hydrothermal method 2 Method for multi-level resistive random access memory
CN110379922A (en) * 2019-08-20 2019-10-25 西安工业大学 A kind of flexibility Ag/MoS2The preparation method of/Cu resistive formula memory
CN110491991A (en) * 2019-08-20 2019-11-22 西安工业大学 It is a kind of to prepare hydro-thermal method MoS2The method of multistage resistance-variable storing device
CN110379922B (en) * 2019-08-20 2023-01-31 西安工业大学 Flexible Ag/MoS 2 Preparation method of/Cu resistive random access memory
CN111883655A (en) * 2020-06-10 2020-11-03 广东工业大学 In2S3Thin-film memristor and application thereof
CN111933794A (en) * 2020-07-02 2020-11-13 北京航空航天大学 MoS based on coexistence of analog type and digital type2Base memristor and preparation method thereof
CN111933794B (en) * 2020-07-02 2023-08-01 北京航空航天大学 MoS based on coexistence of analog type and digital type 2 Base memristor and preparation method thereof
CN114931864A (en) * 2021-05-08 2022-08-23 淮阴师范学院 Two-dimensional material composite separation membrane, preparation method and application
CN114931864B (en) * 2021-05-08 2023-11-24 淮阴师范学院 Two-dimensional material composite separation membrane, preparation method and application
CN113328036B (en) * 2021-05-21 2022-11-08 西安工业大学 Ag/[ SnS 2 /PMMA]/Cu low-power-consumption resistive random access memory and preparation method thereof
CN113328036A (en) * 2021-05-21 2021-08-31 西安工业大学 Ag/[ SnS2/PMMA]/Cu low-power-consumption resistive random access memory and preparation method thereof

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