CN105808405B - A kind of high-performance pipeline ADC frequency domain parameter assessment system based on SoPC - Google Patents
A kind of high-performance pipeline ADC frequency domain parameter assessment system based on SoPC Download PDFInfo
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- CN105808405B CN105808405B CN201610225902.4A CN201610225902A CN105808405B CN 105808405 B CN105808405 B CN 105808405B CN 201610225902 A CN201610225902 A CN 201610225902A CN 105808405 B CN105808405 B CN 105808405B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
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Abstract
The present invention relates to a kind of high-performance pipeline ADC frequency domain parameter assessment systems with SoPC cores in order to control, including sample collection and processing SoPC, ADC chips daughter board, Graphic Interface Control end, signal source and clock source to be assessed.Sample collection and processing SoPC configure ADC daughter boards to be assessed using Microblaze processors by daughterboard interface, cache the sample from ADC chips daughter board to be assessed using asynchronous FIFO module, are stored sample to DDR3 memories by dma controller.ADC chips daughter board to be assessed receives signal source with the signal of clock source generation as input sample signal and clock signal.Graphic Interface Control end is communicated with Microblaze processors by serial ports, receives sample, and frequency domain parameter assessment is completed in Graphic Interface Control end.The present invention uses modular method, shortens the frequency domain Performance Evaluation period, has the advantages that at low cost, easy to operate.
Description
Technical field
The invention belongs to integrated circuit testing fields, are related to a kind of high-performance pipeline ADC frequency domain parameter based on SoPC
Assessment system.
Background technology
With the fast development of microelectric technique and Digital Signal Processing, analog-digital converter (Analog-to-
Digital Converter, ADC) as the interface for connecting simulated world and digital display circuit, effect is more and more obvious.Wherein
High-performance pipeline ADC is with increasingly wide in the application of the field of signal processing such as military radar communication the characteristics of its high-speed, high precision
It is general；As the core component of system, the frequency domain characteristic of ADC often directly determines system performance.But, all by manufacturing process etc.
The influence of more extraneous factors, the actual parameter performance of high-performance pipeline ADC are extremely difficult to the ideal value of design, therefore, in order to ensure that
The performance of ADC is met the requirements, it is necessary to carry out Performance Evaluation to it.
Currently, offshore company is all based on greatly dedicated automation assessment equipment to the Performance Evaluation of high-performance pipeline ADC,
Such as the special ADC performance evaluation system of the PXIe measurement series assessment systems of NI companies, ADI companies, such equipment price are high
It is high, complicated for operation, often make the equipment cost of project and human cost excessively high, and as the performance of pipeline ADC is constantly promoted,
Its Performance Evaluation needs assessment system to have higher processing capacity.Microcontroller and DSP (Digital Signal
) etc. Processor programming device can simplify performance parameter evaluation flow.But SCM Based assessment system, clock
Frequency is relatively low, cannot be satisfied fast high-performance pipeline ADC speed, high resolution, generates the big feature of sample number；DSP has height
Fast processing capacity, powerful and flexible interface and communication capacity, but simultaneously DSP is wasted there is also weakness such as control deficiencies
Valuable calculation resources.FPGA disclosure satisfy that system needs because of the features such as its clock frequency is fast, control is flexible, interface resource is abundant
It asks.Therefore, it is important to realize that the high-performance pipeline ADC performance evaluation system based on SoPC has using FPGA as carrier for structure
Practice significance.
Invention content
In view of the shortcomings of the prior art, the purpose of the present invention is intended to provide a kind of high-performance assembly line based on SoPC
ADC frequency domain parameter assessment systems may be implemented data acquisition, data reduction of speed, carry the functions such as storage, made using modular method
The ADC for obtaining different indexs can carry out actual frequency domain parameter assessment in a common sample collection and processing SoPC.
The present invention is achieved through the following technical solutions：
A kind of high-performance pipeline ADC frequency domain parameter assessment system with SoPC cores in order to control, it is characterised in that：Including
Sample collection and processing SoPC, ADC chips daughter board, Graphic Interface Control end, signal source and clock source to be assessed.The sample is adopted
Collection and processing SoPC include Microblaze processors, serial communication modular, asynchronous FIFO module, dma controller, DDR3 storages
Device and daughterboard interface.The sample collection and processing SoPC are connected with the ADC chips daughter board to be assessed carries out logic control, sample
This acquisition and processing are connected with the Graphic Interface Control end and carry out communication and frequency domain parameter assessment.The ADC chips to be assessed
Daughter board includes ADC chips, analog input circuit, clock management circuits and motherboard interface to be assessed, receives signal source and clock source
The signal of generation is as input sample signal and clock signal.The Graphic Interface Control end, including serial communication modular, parameter
Evaluation module, data memory module, the main two-way communication and control for realizing with the sample collection and handling SoPC.Assessment step
Suddenly it is：Microblaze processors configure the ADC chips daughter board to be assessed by daughterboard interface and carry out sample collection, and utilization is different
It walks fifo module and caches the sample from the ADC chips daughter board to be assessed, sample is stored to DDR3 by dma controller and is deposited
Sample is then sent to the Graphic Interface Control end and carries out parameter evaluation by reservoir.
Description of the drawings
Fig. 1 is the structural representation of the high-performance pipeline ADC frequency domain parameter assessment system provided by the invention based on SoPC
Figure.
Fig. 2 is data storage path schematic diagram provided by the invention.
Fig. 3 is ADC chips daughter board high-level schematic functional block diagram to be assessed provided by the invention.
Fig. 4 is control estimation flow schematic diagram provided by the invention.
Fig. 5 is control terminal assessment interface schematic diagram provided by the invention.
Specific implementation mode
With reference to specific attached drawing and case study on implementation, the invention will be further described.
Embodiments of the present invention are related to a kind of high-performance pipeline ADC frequency domain parameter assessment system based on SoPC, such as
Shown in Fig. 1, which includes at least：Sample collection and processing SoPC, ADC chips daughter board to be assessed, Graphic Interface Control end, letter
Number source and clock source.It is as follows：Microblaze processors configure daughter board to be assessed by daughterboard interface and carry out sample
Acquisition caches the sample from ADC chips daughter board to be assessed using asynchronous FIFO module, is stored sample by dma controller
To DDR3 memories, then sample is sent to Graphic Interface Control end and carries out parameter evaluation.
Sample collection described in SoPC and processing SoPC include Microblaze processors, serial communication modular, asynchronous FIFO
Module, dma controller, DDR3 memories and daughterboard interface.Microblaze processors are the insertions applied to Xilinx FPGA
The soft core of formula controls sample collection and processing as the control core of sample collection and processing SoPC by AXI4 bus interface
The other parts of SoPC specifically include control ADC chips daughter board to be assessed, for being communicated with Graphic Interface Control end, together
When control asynchronous FIFO module, dma controller, DDR3 memories carry out sample storage.Daughterboard interface is for extending sample collection
With the I/O of processing SoPC, it is connect respectively with sample collection and the motherboard interface of processing SoPC and ADC chips daughter board to be assessed, by
68 user-defined single-ended signals or 34 user-defined differential pairs, serial transceiver constitute, clock, for supporting
Data transmission of the ADC chips daughter board to be assessed to sample collection and processing SoPC.Serial communication modular, using USB-UART interfaces
It realizes, wherein USB port is connect with Graphic Interface Control end, and UART is connected with the sample collection and processing SoPC, is used for figure
Communication and debugging between Interface Control end and the sample collection and processing SoPC.SoPC is due to ADC chips to be assessed
Clock frequency when plate sample collection can not be matched with the AXI4 Bus Speeds of the sample collection and processing SoPC, it is therefore desirable to
Asynchronous FIFO module caches the sample of high-speed time domain state ADC chips daughter board generation to be assessed to meet AXI4 Bus Speeds.DMA
Controller take over Microblaze processors in sample collection procedure carry out data transmission, for controlling asynchronous FIFO module extremely
The memory channel of DDR memory, so as to which Microblaze processors can be freed from the carrying of heavy data；
DDR3 memories are additionally operable to store the sample that ADC chips daughter board to be assessed generates other than providing running space for code.Sample
Path from generating storage is as shown in Figure 2：The single-ended analog signal that clock source generates enters analog input circuit and generates simulation
Differential signal subsequently enters ADC chips to be assessed, digital difference signal is exported after carrying out A/D conversions, after certain delay
It is combined into final required numerical data；After asynchronous FIFO module caching, DDR3 memories are sent by dma controller
In.Every piece of ADC chips daughter board to be assessed has respective DMA channel, only need to be each there are when multiple ADC chips to be assessed
ADC chips to be assessed add respective dedicated channel.
The function module connection relation of the ADC chips daughter board to be assessed is as shown in figure 3, include ADC chips to be assessed, mould
Quasi- input circuit, clock management circuits；The ADC chips daughter board to be assessed passes through motherboard interface and the sample collection and processing
SoPC is connected, and receives the signal from signal source and clock source as sampled signal and clock signal；Analog input circuit, as
The buffer of ADC chips to be assessed, it is defeated by simulating by the single-ended analog signal of signal generator input high-purity after filtered
Output difference signal to ADC chips to be assessed carry out A/D conversions after entering the conversion of circuit, amplification；Clock management circuits, and it is to be evaluated
Estimate ADC chips with clock source to be connected, programmable clock signal is provided for ADC chips to be assessed.
The Graphic Interface Control end is developed using Labview, including the storage of serial communication modular, evaluation module, data
Module, be used for and the sample collection and processing SoPC communicated, the acquisition of data, transmission and Performance Evaluation, control stream
Journey is as shown in Figure 4.Serial communication modular initializes, after progress relevant communication parameter setting, at this time Graphic Interface Control end and institute
It states sample collection and processing SoPC starts to communicate, if receiving the sample collection and the processing ready signals of SoPC, just
Subsequent operation can be carried out in the graphical interfaces at Graphic Interface Control end；The specific interface in Graphic Interface Control end as shown in figure 5,
Before program starts, the related setting that data sampling is set, including conversion accuracy, sample rate, assessment algorithm etc. are needed；Startup program
Afterwards, it waits for the ADC chips daughter board to be assessed to initialize successful information, can be shown with the reception time-domain diagram part of sampled data
Show corresponding sine wave figure, clicks performance evaluating and frequency domain characteristic assessment can be completed.
Finally illustrate, the above examples are only used to illustrate the technical scheme of the present invention and are not limiting, although with reference to compared with
Good embodiment describes the invention in detail, it will be understood by those of ordinary skill in the art that, it can be to the skill of the present invention
Art scheme is modified or replaced equivalently, and without departing from the objective and range of technical solution of the present invention, should all be covered at this
In the right of invention.
Claims (1)
1. a kind of high-performance pipeline ADC frequency domain parameter assessment system with SoPC cores in order to control, it is characterised in that：Including sample
This acquisition and processing SoPC, ADC chips daughter board, Graphic Interface Control end, signal source and clock source to be assessed；
The sample collection and processing SoPC include Microblaze processors, serial communication modular, asynchronous FIFO module, DMA
Controller, DDR3 memories and daughterboard interface；The asynchronous FIFO module is for caching high-speed time domain state ADC chips to be assessed
The sample that daughter board generates so that clock frequency when the ADC chips daughter board sample collection to be assessed and the sample collection and
Handle the AXI4 Bus Speeds matching of SoPC；The dma controller is deposited for controlling the asynchronous FIFO module to the DDR3
The memory channel of reservoir, take over Microblaze processors carry out data transmission in sample collection procedure；The daughterboard interface
For extending sample collection and handling the I/O of SoPC, by 68 user-defined single-ended signals or 34 user-defined differences
Point to and serial transceiver, clock is constituted, for support the ADC chips daughter board to be assessed to the sample collection with
Handle the data transmission of SoPC；
The ADC chips daughter board to be assessed includes that ADC chips, analog input circuit, clock management circuits and motherboard to be assessed connect
Mouthful, receive signal source with the signal of clock source generation as input sample signal and clock signal；The analog input circuit is made
For the buffer of ADC chips to be assessed, the single-ended analog signal of high-purity is inputted after filtered by signal generator, by simulation
Output difference signal to ADC chips to be assessed carry out analog-to-digital conversion after the conversion of input circuit, amplification；The Clock management electricity
Road is connected with ADC chips to be assessed and clock source, and programmable clock signal is provided for ADC chips to be assessed；Figure circle
Face control terminal, including serial communication modular, parameter evaluation module, data memory module；The Graphic Interface Control end, assessment
When ADC chips, parameter setting, including conversion accuracy, sample rate, assessment algorithm first are carried out to the ADC chips daughter board to be assessed,
It then waits for the ADC chips daughter board to be assessed and initializes successful information, sampled data is then received by serial ports, data connect
By after, clicks performance evaluating and frequency domain characteristic assessment can be completed；
The sample collection and processing SoPC are connected by daughterboard interface with the motherboard interface of the ADC chips daughter board to be assessed,
Realize logic control, sample collection and the processing to carrying out the ADC chips daughter board to be assessed；
The serial communication modular phase of the serial communication modular and the Graphic Interface Control end of the sample collection and processing SoPC
Even, it realizes the sample collection and handles the two-way communication and control of SoPC and the Graphic Interface Control end；
Appraisal procedure is：Microblaze processors configure the ADC chips daughter board to be assessed by daughterboard interface and carry out sample
Acquisition caches the sample from the ADC chips daughter board to be assessed using the asynchronous FIFO module, is controlled by the DMA
Device stores sample to the DDR3 memories, then send sample to the Graphic Interface Control end and carries out parameter evaluation.
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| CN108616279A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of low jitter multichannel intermediate-freuqncy signal acquisition clock circuit |
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| CN103441762A (en) * | 2013-09-09 | 2013-12-11 | 江南大学 | ADC dynamic parameter testing method based on Blackman window three-spectrum-line interpolation |
| CN104459518A (en) * | 2014-11-27 | 2015-03-25 | 北京时代民芯科技有限公司 | Function automation testing system and testing method based on SoPC chip |
| CN104504975A (en) * | 2014-12-29 | 2015-04-08 | 清华大学 | Portable comprehensive electronic experimental platform on basis of field programmable gate arrays |
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| US8823850B2 (en) * | 2010-12-30 | 2014-09-02 | Hynix Semiconductor Inc. | Image processing system with on-chip test mode for column ADCs |
| CN102768336A (en) * | 2012-07-20 | 2012-11-07 | 中国科学院深圳先进技术研究院 | Built-in self-test system based on on-chip system or system-in-package |
| US9240798B2 (en) * | 2014-02-28 | 2016-01-19 | Texas Instruments Incorporated | On-chip analog-to-digital converter (ADC) linearity text for embedded devices |
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| CN101893684A (en) * | 2010-02-10 | 2010-11-24 | 哈尔滨工业大学 | BIST general basic test module based on system on chip SOC and test system thereof and test method applying same |
| CN103441762A (en) * | 2013-09-09 | 2013-12-11 | 江南大学 | ADC dynamic parameter testing method based on Blackman window three-spectrum-line interpolation |
| CN104459518A (en) * | 2014-11-27 | 2015-03-25 | 北京时代民芯科技有限公司 | Function automation testing system and testing method based on SoPC chip |
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