CN105807752A - Test system suitable for MMC valve base controller gathering control unit - Google Patents
Test system suitable for MMC valve base controller gathering control unit Download PDFInfo
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Abstract
The invention provides a test system suitable for an MMC valve base controller gathering control unit. The test system operates through an upper computer and a lower computer. The upper computer comprises an operation layer. The lower computer comprises an interface layer, a model layer and a control layer. The interface layer is connected with a gathering unit and the model layer. The model layer constructs a digital model. The control layer reports the state of the digital model to the operation layer. The operation layer controls the control layer to operate the digital model. Compared with the prior art, the test system suitable for the MMC valve base controller gathering control unit, which is provided by the invention has the advantages that the gathering unit of the valve base controller is used as the test object; the gathering unit is used as the object to carry out in-depth test on the valve base controller; the valve base controller in a secondary system has the capacity of continuous and stable operation; the hardware reliability and safety of the whole set of the valve base controller VBC are ensured; and a converter valve is well controlled and protected.
Description
Technical field
The present invention relates to flexible direct-current transmission field, in particular to a kind of test system collecting control unit suitable in MMC valve base controller.
Background technology
In flexible DC power transmission engineering, collection unit is responsible for controlling the bridge wall intersegmental balance of submodule voltage, applies to one of most important ingredient in MMC valve base controller VBC, must have continuous, stable service ability.The current method of testing to collection unit mainly set up in the lab low-voltage, small area analysis flexible direct current converter station dynamic model platform to simulate the working condition of current conversion station in Practical Project; by the integrated testability to VBC, collection unit hardware reliability, control strategy, Preservation tactics etc. are verified.
But, VBC is the secondary device of cooperation between a huge structure, multi-functional unit；Each collection unit needs to coordinate lower work with multiple segmenting units and current unit.Current dynamic model platform has the limitation such as complicated operation, very flexible, VBC overall performance can only be made assessment, and being but difficult to collection unit is that object does more deep test.Accordingly, it would be desirable to a kind of more flexibly, easily operation, device that versatility is good collection unit is carried out comprehensive, deep test.But do not find VBC collection unit is carried out the device design of depth test at present both at home and abroad.
Therefore, development along with flexible DC power transmission engineering, how to design a kind of more flexibly, valve base controller collection unit is carried out comprehensive, deep test by easily operation, test system that versatility is good, is those skilled in the art's technical problems urgently to be resolved hurrily.
Summary of the invention
In view of this, the present invention provides a kind of test system collecting control unit suitable in MMC valve base controller, and this test system is with collection unit for test object；Corresponding mathematical model is set up according to the operating characteristic of segmenting unit, current unit；Mathematical model can be observed by host computer, control；The peripheral environment of collection unit is simulated with mathematical model；And then launch comprehensive, deep test.
A kind of test system collecting control unit suitable in MMC valve base controller, described collection unit is the part in valve base controller, its side is connected with current unit, opposite side is connected with segmenting unit, described test system is run by host computer and slave computer, described host computer is provided with operation layer, described slave computer is provided with interface layer, model layer and key-course, described interface layer connects described collection unit and described model layer, described model layer builds mathematical model, described key-course is by the state reporting of described mathematical model to described operation layer, described operation layer controls described key-course and mathematical model is operated.
Preferably, described interface layer includes polylith interface board, and described interface board receives the fiber-optic signal of described collection unit, and converts LVDS signal to and be transferred to described model layer, described interface board is transferred to described collection unit after converting the LVDS signal of the described model layer received to fiber-optic signal.
Preferably, described model layer hardware description language writes the program for building described mathematical model, and described model layer includes 1 current unit and multiple segmenting unit.
Preferably, the operating characteristic of described segmenting unit and current unit simulated by described mathematical model.
Preferably, described key-course controls cycle access every 1 and checks 1 time described mathematical model；When the state that described key-course checks described mathematical model changes, described key-course is generated corresponding SOE data and is sent to described operation layer by Ethernet, described operation layer sends instruction code to described key-course, model layer is operated by described key-course according to described instruction code, is simultaneously generated SOE data and is uploaded to described operation layer；When described key-course checks described mathematical model, when the state of described mathematical model does not change, described key-course continues checking for described mathematical model until the state of described mathematical model changes in lower 1 control cycle.
Preferably, the programming device that described key-course uses is FPGA, and described key-course includes DSP and Ethernet driver.
Preferably, described operation layer includes driver, mastery routine, data base and user interface；Including visualization model in described user interface, described visualization model maps the whole described mathematical model of described model layer；Described mastery routine receives the described SOE data that described driver resolves, and after the content according to described SOE data changes the display result of visualization model, stores SOE data to described data base.
Can be seen that from above-mentioned technical scheme, the invention provides a kind of test system collecting control unit suitable in MMC valve base controller, test system is run by host computer and slave computer, host computer is provided with operation layer, being provided with interface layer, model layer and key-course, interface layer connecting test object and model layer in slave computer, model layer builds mathematical model, key-course is by the state reporting of mathematical model to operation layer, and operation layer controls key-course and mathematical model is operated.A kind of test system suitable in collection unit, this system is with collection unit for test object；Corresponding mathematical model is set up according to the operating characteristic of SM, collection unit；Mathematical model can be observed by host computer, control；The peripheral environment of collection unit is simulated with mathematical model；And then launch comprehensive, deep test.
With immediate prior art ratio, technical scheme provided by the invention has following excellent effect:
1, technical scheme provided by the invention; with the collection unit of valve base controller for test object; achieve and for object, valve base controller is done more deep test with collection unit; the valve base controller in electrical secondary system is made to have continuous, stable service ability; ensure that the hardware reliability of a whole set of valve base controller VBC and safety, be able to better converter valve is controlled and protection.
2, technical scheme provided by the invention, each current unit, segmenting unit mathematical model on host computer screen, have corresponding visualization model；Tester can be configured experimental enviroment by visualization model, be understood Test condition；It is substantially reduced operation easier so that whole test system is easily operated.
3, technical scheme provided by the invention, part test needs to reach 0.1ms level between current unit and segmenting unit and coordinates, and existing test device is difficult to；Each model under operation layer control instruction, can be carried out unified scheduling, control by the key-course of VTS, carries out a series of automatization, operation that sequential is tight.
4, technical scheme provided by the invention, SOE is stored in data base by operation layer；According to historical data, it is possible to the process of the test regained one's integrity, the present invention is suitable for the functional unit (or mini system of several unit composition) in VBC and similar electrical secondary system huge, complicated is carried out depth test, it is ensured that the integrity of record.
5, technical scheme provided by the invention, is widely used, and has significant Social benefit and economic benefit.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be introduced briefly below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the system schematic of the test system collecting control unit suitable in MMC valve base controller of the present invention；
The MMC valve base controller that is applicable to that Fig. 2 is the present invention collects the slave computer of test system of control unit and the structural representation of slave computer；
Fig. 3 be the test system collecting control unit suitable in MMC valve base controller of the present invention slave computer interface layer, model layer, key-course schematic diagram.
Fig. 4 be the test system collecting control unit suitable in MMC valve base controller of the present invention host computer operation layer structural representation.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.Based on embodiments of the invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
If Fig. 1 is to shown in 2, a kind of test system collecting control unit suitable in MMC valve base controller of the present invention, collection unit is the part in valve base controller, its one end current unit connects, the other end is connected with segmenting unit: collection unit is for receiving the control command that current unit issues, as brachium pontis should put into level number etc.；And these control instructions are handed down to each segmenting unit；Receive the state that each segmenting unit reports, and collect, be uploaded to current unit；Wherein, current unit, collection unit all carry out closed loop control, adjustment control command according to the state of segmenting unit feedback.
Test system is run by host computer and slave computer, is provided with operation layer, is provided with interface layer, model layer and key-course in slave computer in host computer, and interface layer connects collection unit and model layer, is the tie between physical signalling and logical signal；
Model layer builds mathematical model, and the state reporting of mathematical model to operation layer, by each model of command operating so that it is cooperate, is simulated the working environment of collection unit by key-course；Read each model duty and generate SOE and report operation layer with the resolution of 0.1ms；Operation layer controls key-course and mathematical model is operated, and maps mathematical model, convenient operation and analysis by visualization model；Record SOE, later stage can carry out finer analysis by enquiry of historical data；Model layer hardware description language writes the program for building mathematical model, and model layer includes 1 current unit and multiple segmenting unit；
Wherein, collection unit cooperates with multiple segmenting units and current unit in systems.VTS configuration is as follows: collection unit is connected by (1) optical fiber with VTS slave computer, (2) FPGA comprises the mathematical model of segmenting unit and current unit, (3) comprising corresponding control, communication program in controller, (4) host computer comprises the visualization model of segmenting unit, current unit mathematical model.In test, tester passes through upper computer selecting content of the test, and slave computer performs operation and returns test data；Tester passes through data analysis result of the test.
As shown in Figure 3, interface layer includes polylith interface board, to be provided with 10 pieces of interface boards in the present embodiment, interface board receives the fiber-optic signal of collection unit, and convert LVDS signal to and be transferred to model layer, interface board is transferred to test object after converting the LVDS signal of the model layer received to fiber-optic signal.Mathematical model want can the primary operating characteristics of simulator, even if in the hands off situation of key-course, also can drive collection unit continuous service.Hardware description language (HardwareDescriptionLanguage is called for short HDL) has the feature of parallel running.FPGA may insure that separate operation between different model with the HDL mathematical model write, simulate the situation of multiple ancillary equipment Collaboration more really, it might even be possible to clock drift phenomenon between simulation distinct device.
Wherein, key-course is made up of DSP and Ethernet driver.Key-course controls cycle access every 1 and checks 1 pass word model；The control cycle is 100us.When the state that key-course checks mathematical model changes, key-course is generated corresponding SOE data and is sent to operation layer by Ethernet, operation layer sends instruction code to key-course, and model layer is operated by key-course according to instruction code, is simultaneously generated SOE data and is uploaded to operation layer；When key-course checks mathematical model, when the state of mathematical model does not change, key-course continues checking for mathematical model until the state of mathematical model changes in lower 1 control cycle.
As shown in Figure 4, operation layer includes driver, mastery routine, data base and user interface；User interface includes visualization model, whole mathematical models of visualization model mapping model layer；Namely each SM, collection unit mathematical model on the visualization screen of host computer, have corresponding visualization model；Tester can be configured experimental enviroment by visualization model, be understood Test condition；It is substantially reduced operation easier.Mastery routine receives the SOE data that driver resolves, and after the content according to SOE data changes the display result of visualization model, stores SOE data to data base；SOE is stored in data base by operation layer；According to historical data, it is possible to the process of the test regained one's integrity.
Wherein, FPGA is FieldProgrammableGateArray field programmable gate array；
MMC is Multi-levelModularConverter many level blockization changer；
LVDS is LowVoltageDifferentialSignal low-voltage differential level signal；
SOE is SequenceofEvent sequence of events recording；
DSP is DigitalSignalProcessor digital signal processor；
SM is Sub-modular submodule.
Above example is only in order to illustrate that technical scheme is not intended to limit; although the present invention being described in detail with reference to above-described embodiment; the specific embodiment of the present invention still can be modified or equivalent replacement by those of ordinary skill in the field; and these without departing from any amendment of spirit and scope of the invention or equivalent are replaced, within the claims of its present invention all awaited the reply in application.
Claims (7)
1. the test system collecting control unit suitable in MMC valve base controller, described collection unit is the part in valve base controller, its side is connected with current unit, opposite side is connected with segmenting unit, it is characterized in that, described test system is run by host computer and slave computer, described host computer is provided with operation layer, described slave computer is provided with interface layer, model layer and key-course, described interface layer connects described collection unit and described model layer, described model layer builds mathematical model, described key-course is by the state reporting of described mathematical model to described operation layer, described operation layer controls described key-course and mathematical model is operated.
2. test system as claimed in claim 1, it is characterized in that, described interface layer includes polylith interface board, described interface board receives the fiber-optic signal of described collection unit, and convert LVDS signal to and be transferred to described model layer, described interface board is transferred to described collection unit after converting the LVDS signal of the described model layer received to fiber-optic signal.
3. testing system as claimed in claim 1, it is characterised in that described model layer hardware description language writes the program for building described mathematical model, described model layer includes 1 current unit and multiple segmenting unit.
4. test system as claimed in claim 1, it is characterised in that the operating characteristic of described segmenting unit and current unit simulated by described mathematical model.
5. test system as claimed in claim 1, it is characterised in that described key-course controls cycle access every 1 and checks 1 time described mathematical model；When the state that described key-course checks described mathematical model changes, described key-course is generated corresponding SOE data and is sent to described operation layer by Ethernet, described operation layer sends instruction code to described key-course, model layer is operated by described key-course according to described instruction code, is simultaneously generated SOE data and is uploaded to described operation layer；When described key-course checks described mathematical model, when the state of described mathematical model does not change, described key-course continues checking for described mathematical model until the state of described mathematical model changes in lower 1 control cycle.
6. test system as claimed in claim 1, it is characterised in that the programming device that described key-course uses is FPGA, and described key-course includes DSP and Ethernet driver.
7. test system as claimed in claim 1, it is characterised in that described operation layer includes driver, mastery routine, data base and user interface；Including visualization model in described user interface, described visualization model maps the whole described mathematical model of described model layer；Described mastery routine receives the described SOE data that described driver resolves, and after the content according to described SOE data changes the display result of visualization model, stores SOE data to described data base.
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| CN201410855793.5A CN105807752A (en) | 2014-12-31 | 2014-12-31 | Test system suitable for MMC valve base controller gathering control unit |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964543A (en) * | 2010-09-20 | 2011-02-02 | 中国电力科学研究院 | HVDC thyristor valve base electronic equipment system |
| CN102023627A (en) * | 2010-11-24 | 2011-04-20 | 中国电力科学研究院 | Monitoring system for high-voltage sub-module test |
| WO2011073466A1 (en) * | 2009-12-18 | 2011-06-23 | Ingeteam Technology, S.A. | Modular converter based on multi-level distributed circuits with a capacitive mid-point |
| CN102130452A (en) * | 2011-03-16 | 2011-07-20 | 中国电力科学研究院 | Control system, valve base control equipment and submodule integration method |
| CN103713214A (en) * | 2013-12-24 | 2014-04-09 | 国家电网公司 | Intelligent transformer station relay protection closed loop test system |
-
2014
- 2014-12-31 CN CN201410855793.5A patent/CN105807752A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011073466A1 (en) * | 2009-12-18 | 2011-06-23 | Ingeteam Technology, S.A. | Modular converter based on multi-level distributed circuits with a capacitive mid-point |
| CN101964543A (en) * | 2010-09-20 | 2011-02-02 | 中国电力科学研究院 | HVDC thyristor valve base electronic equipment system |
| CN102023627A (en) * | 2010-11-24 | 2011-04-20 | 中国电力科学研究院 | Monitoring system for high-voltage sub-module test |
| CN102130452A (en) * | 2011-03-16 | 2011-07-20 | 中国电力科学研究院 | Control system, valve base control equipment and submodule integration method |
| CN103713214A (en) * | 2013-12-24 | 2014-04-09 | 国家电网公司 | Intelligent transformer station relay protection closed loop test system |
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Effective date of registration: 20170524 Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Applicant after: State Grid Corporation of China Applicant after: China-EPRI Electric Power Engineering Co., Ltd. Applicant after: State Grid Zhejiang Electric Power Company Address before: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Applicant before: State Grid Corporation of China Applicant before: State Grid Smart Grid Institute Applicant before: China-EPRI Electric Power Engineering Co., Ltd. Applicant before: State Grid Zhejiang Electric Power Company |
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