CN105789069B - The method for stacking silicon chip is formed using the hybrid bonding technology of pressure welding point - Google Patents
The method for stacking silicon chip is formed using the hybrid bonding technology of pressure welding point Download PDFInfo
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- CN105789069B CN105789069B CN201610164465.XA CN201610164465A CN105789069B CN 105789069 B CN105789069 B CN 105789069B CN 201610164465 A CN201610164465 A CN 201610164465A CN 105789069 B CN105789069 B CN 105789069B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 84
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 78
- 239000010703 silicon Substances 0.000 title claims abstract description 78
- 238000003466 welding Methods 0.000 title claims abstract description 78
- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000005516 engineering process Methods 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 51
- 239000012790 adhesive layer Substances 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 239000005997 Calcium carbide Substances 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- CLZWAWBPWVRRGI-UHFFFAOYSA-N tert-butyl 2-[2-[2-[2-[bis[2-[(2-methylpropan-2-yl)oxy]-2-oxoethyl]amino]-5-bromophenoxy]ethoxy]-4-methyl-n-[2-[(2-methylpropan-2-yl)oxy]-2-oxoethyl]anilino]acetate Chemical compound CC1=CC=C(N(CC(=O)OC(C)(C)C)CC(=O)OC(C)(C)C)C(OCCOC=2C(=CC=C(Br)C=2)N(CC(=O)OC(C)(C)C)CC(=O)OC(C)(C)C)=C1 CLZWAWBPWVRRGI-UHFFFAOYSA-N 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 9
- 239000000945 filler Substances 0.000 abstract description 2
- 238000002360 preparation method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Pressure Sensors (AREA)
Abstract
The present invention provides a kind of the method for stacking silicon chip is formed using the hybrid bonding technology of pressure welding point, first the groove structure that intermediate width is more than the pressure welding point region of top width is formed using anisotropic lithographic method, then by subsequent pressure welding point metal along the characteristic of sidewall growth, cavity is reserved in pressure welding point metal, finally by between silicon substrate stacking and heat treatment, make the extension of pressure welding point metal and the cavity that intumescent filler is reserved, the corner location for avoiding metal pressure-welding point forms metal cavity and defect, ultimately form two pressure welding point structures for stacking the zero defect with curved wall and cavity between silicon chip, improve the reliability of the quality and product of pressure welding point bonding.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of formed using the hybrid bonding technology of pressure welding point is stacked
The method of silicon chip.
Background technology
In general, in semi-conductor silicon chip manufacture, a piece of silicon chip includes hundreds of or thousands of identical tube cores, these tube cores
In contain the electronic components such as transistor, diode, resistance and circuit, the combination of these components forms certain specific function
Silicon chip.And the maximum area of silicon chip is limited by maximum single exposure area and application environment in semiconductor manufacturing simultaneously, with
The universal of the portable devices such as mobile phone, laptop, the tube core needed increasingly minimizes, but function becomes increasingly complex
With it is comprehensive.In order to meet the requirement for realizing sophisticated functions in certain silicon area, stack silicon chip knot may be used in we
Structure, i.e., by being bonded between silicon chip, be thinned and the silicon chip of different function is stacked by the techniques such as scribing, thus can be with
The silicon chip of different function is combined in the case where not increasing silicon area, silicon chip Stack Technology can save silicon simultaneously
The area and raising performance of piece, the technology i.e. 3D (Three that two or more this silicon chip is stacked
Dimension silicon chip technology) is stacked.
By taking cmos image sensor silicon chip as an example, generally include for photosensitive image sensor array, signal control,
The logic circuits such as reading and processing stack silicon chip technology using 3D, we can form on one piece of silicon chip is used for photosensitive picture
Plain cell array structure forms signal control, reading and processing circuit, then by both different silicon on another piece of silicon chip
Piece is stacked by hybrid bonding technology, forms one piece of complete cmos image sensor silicon chip.Certain 3D stacks work
Skill is also applied in the arbitrary application for needing different silicon chips being stacked.
In hybrid bonding technology, being pressed for the conduction in conductive pressure welding point and another piece of silicon chip in one piece of tube core
Solder joint Direct Bonding is together.It is as shown in Figure 1 the stacking silicon chip formed using traditional hybrid bonded technique of pressure welding point, in pressure welding
During point bonding, generally use melts conductive the pressing of bonding or heat treatment process by this two pieces of silicon chips of upper silicon chip and lower silicon slice
Solder joint is bound up to form the conductive path between two silicon chips, but due to being bonded using heat treatment process, leads
The metal material used on voltage solder joint can extend and expand in technical process, finally between two pressure welding points, especially
The corner location of metal pressure-welding point forms metal cavity as shown in Figure 1 and defect, and then influences the quality and product of bonding
Reliability.
Invention content
In order to overcome problem above, the present invention is intended to provide one kind, which prevents 3D from stacking Gold In Silicon Wafers category pressure welding point, forms cavity
With the method for defect, to improve the reliability of bonding quality and product.
In order to achieve the above object, the present invention provides a kind of formed using the hybrid bonding technology of pressure welding point to stack silicon chip
Method comprising：
Step 01：Two silicon chips with semiconductor devices are provided；Wherein, there is preceding road technique system on each silicon chip
The semiconductor device structure made, the interconnection structure of postchannel process manufacture；Then, be formed on entire silicon chip top layer dielectric layer and
Adhesive layer；There is pressure welding point region in the top layer dielectric layer and the adhesive layer；
Step 02：Using anisotropic etch process, forms intermediate width in the pressure welding point region and be more than top width
Groove structure；
Step 03：Pressure welding point metal is grown in the groove structure, wherein the pressure welding point metal is by the groove knot
It is closed at the top of structure, and forms reserved cavity among the groove structure；
Step 04：The pressure welding point metal top is ground to the bonding layer surface；
Step 05：Two silicon chips for completing the step 04 are stacked, and are served as a contrast two silicon by the adhesive layer
Bottom is bonded together；
Step 06：The pressure welding point metal is bonded using heat treatment process, the metal heated expansion of pressure welding point
And extension, it is filled with the reserved cavity in the groove structure.
Preferably, the groove structure has curved wall.
Preferably, the material of the top layer dielectric layer is silica.
Preferably, the thickness of the top layer dielectric layer is
Preferably, the material of the adhesive layer is one or more in silicon oxynitride, silica, silicon nitride, calcium carbide
Composite construction.
Preferably, the thickness of the adhesive layer is
Preferably, in the step 03, pressure welding point metallic copper is grown in the groove structure using copper electroplating technology.
Preferably, in the step 04, the pressure welding point metal top is ground using CMP process to institute
State bonding layer surface.
Preferably, the process of lapping monitors grinding endpoint by endpoint Detection, and stops on the adhesive layer.
Preferably, the semiconductor device structure includes pixel cell structure；The interconnection structure of the postchannel process manufacture
Including metal layer and via layer.
The present invention forms the pressure welding point region that intermediate width is more than top width using anisotropic lithographic method first
Groove structure, then by subsequent pressure welding point metal along the characteristic of sidewall growth, in pressure welding point metal reserve cavity, most
Afterwards by stacking between silicon substrate and heat treatment, makes the extension of pressure welding point metal and the reserved cavity of intumescent filler, avoid
The corner location of metal pressure-welding point forms metal cavity and defect, ultimately forms two and stacks the nothing with curved wall between silicon chip
The pressure welding point structure of defect and cavity improves the reliability of the quality and product of pressure welding point bonding.
Description of the drawings
Fig. 1 is the schematic diagram of the stacking silicon chip formed using traditional hybrid bonded technique of pressure welding point
Fig. 2 is the structural schematic diagram of the stacking silicon chip prepared by the preferred embodiment of the present invention
Fig. 3 is the flow diagram that the formation of the preferred embodiment of the present invention stacks the method for silicon chip
Fig. 4~9 are each preparation process schematic diagram that the formation of the preferred embodiment of the present invention stacks the method for silicon chip
Specific implementation mode
To keep present disclosure more clear and easy to understand, below in conjunction with Figure of description, present disclosure is made into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, the general replacement known to those skilled in the art
Cover within the scope of the present invention.
Below in conjunction with attached drawing 2~9 and specific embodiment, invention is further described in detail.It should be noted that attached drawing
Be all made of very simplified form, using non-accurate ratio, and only to it is convenient, clearly reach aid illustration the present embodiment
Purpose.
Fig. 2 is please referred to, the hybrid bonding technology of the use pressure welding point in the present embodiment, which is formed, stacks silicon chip structure, including：
Semiconductor devices on one silicon chip 500 is for photosensitive pixel unit array；Semiconductor device structure is pixel unit knot
Structure, including photodiode, transmission tube grid etc.；The post-channel interconnection structure of postchannel process manufacture includes metal layer and via layer,
Post-channel interconnection structure includes first layer metal, first layer through-hole, second layer metal and second layer through-hole；On another silicon chip 600
Semiconductor devices be pixel unit control and reading circuit, semiconductor device structure include the active devices such as metal-oxide-semiconductor and electricity
Hinder the passive devices such as capacitance；There is top layer dielectric layer 502, adhesive layer 503 on entire silicon chip 500 and be located at 503 and of adhesive layer
Pressure welding point region (dotted line frame) in top layer dielectric layer 502 has pressure welding point metal M in pressure welding point region；In entire silicon chip 600
The upper pressure welding point region (dotted line frame) in top layer dielectric layer 602, adhesive layer 603 and top layer dielectric layer 602, pressure welding point region
In have pressure welding point metal M '；The pressure welding point metal 501 and 601 in the pressure welding point region being located in silicon chip 500 and 600 has
There is curved wall, pressure welding point metal 501,601 is without cavity and defect.
The description of preparation process is carried out with the partial enlarged view with pressure welding point region in Fig. 2 below, but this does not have to
In limiting the scope of the invention；Referring to Fig. 3, being formed using the hybrid bonding technology of pressure welding point for the present embodiment stacks silicon chip
Method, including：
Step 01：Two silicon chip substrates with semiconductor devices are provided；Wherein, there is preceding road work in each silicon chip substrate
The semiconductor device structure of skill manufacture, the interconnection structure of postchannel process manufacture；Then, it is formed with top layer in entire silicon chip substrate
Dielectric layer and adhesive layer；There is pressure welding point region in top layer dielectric layer and adhesive layer；
Specifically, silicon chip substrate structure may refer to the description of Fig. 2, for the ease of expression, only show that there is pressure welding in Fig. 4
The partial structurtes in region are put to describe, as shown in figure 4, in silicon chip 500, using chemical vapor deposition method in entire silicon chip substrate
Deposited top layer dielectric layer 502 and adhesive layer 503 on 501；The material of top layer dielectric layer 502 can be the media materials such as silica
Material, thickness is different according to the difference of technique, and the thickness of top layer dielectric layer 502 can beAdhesive layer 503
Material be silicon oxynitride, silica, silicon nitride, one or more composite constructions in calcium carbide, the thickness of adhesive layer 503
Can be The bonding stacked between silicon chip for follow-up two.
Step 02：Using anisotropic etch process, the ditch that intermediate width is more than top width is formed in pressure welding point region
Slot structure；
Specifically, referring to Fig. 5, by taking the preparation of a silicon chip 500 as an example, the groove structure of formation has curved wall S,
The top width W1 of curved wall S is less than intermediate width W2；
Step 03：Pressure welding point metal is grown in groove structure, wherein pressure welding point metal will be closed at the top of groove structure,
And reserved cavity is formed among groove structure；
Specifically, referring to Fig. 6, by taking the preparation of a silicon chip 500 as an example, given birth in groove structure using copper electroplating technology
Long pressure welding point metallic copper M adds the top of groove structure since metallic copper is electroplate with the characteristic grown along side wall copper seed layer
Portion's width is less than intermediate width, and therefore, the top area of groove structure can be first closed so that subsequent copper galavanic growth can only silicon
Piece surface carries out, and cannot be carried out inside groove structure, so as to form the internal pressure welding point metal M with reserved cavity K.
Step 04：Grinding pressure welding point metal top is to bonding layer surface；
Specifically, referring to Fig. 7, by taking the preparation of a silicon chip 500 as an example, pressure is ground using CMP process
Solder joint metal top is to 503 surface of adhesive layer, to remove the metallic copper on 500 surface of silicon chip, due to chemically-mechanicapolish polishing work
Skill there is difference, process of lapping to monitor grinding endpoint by endpoint Detection the grinding rate of metallic copper and adhesive layer, and
It stops on adhesive layer 503；In order to ensure that 500 surface of silicon chip does not have pressure welding point metallic copper M residuals, adhesive layer 503 to allow above
HaveIt arrivesThickness damage, and pressure welding point metallic copper only retains in groove structure；
Step 05：Two silicon chip substrates for completing step 04 are stacked, and are glued two silicon substrates by adhesive layer
It is combined；
Specifically, common process may be used with adhesion process referring to Fig. 8, being stacked about silicon chip substrate, here no longer
It repeats.Above-mentioned steps 01~04 describe a silicon chip 500, here another silicon chip 600 in Fig. 7 be also using step 01~
04 prepares, and repeats no more；There is silicon chip substrate 601, dielectric layer 602, adhesive layer 603 and pressure welding point region, pressure welding in silicon chip 600
There is pressure welding point metal M ' in point region, there is reserved cavity K in pressure welding point metal M '；It should be noted that can each silicon chip
It prepares simultaneously, preparation that can also be one by one；
Step 06：Pressure welding point metal is bonded using heat treatment process, the metal heated expansion of pressure welding point and extension are filled out
The reserved cavity in groove structure is filled.
Specifically, referring to Fig. 9, by heat treatment pressure welding point metallic copper M and M ' are bonded, pressure welding point metal M and
M ' expanded by heating and extend, be filled with reserved cavity K, avoiding the corner location of metal pressure-welding point, to form metal empty
And defect；To form the pressure welding point of zero defect and cavity with curved wall between the stacking silicon chip 500 and 600 at two
Metal M and M ' structure improves the reliability of the quality and product of pressure welding point bonding.
Although the present invention disclosed with preferred embodiment it is as above, the right embodiment illustrate only for the purposes of explanation and
, it is not limited to the present invention, if those skilled in the art can make without departing from the spirit and scope of the present invention
Dry changes and retouches, and the protection domain that the present invention is advocated should be subject to described in claims.
Claims (10)
1. a kind of forming the method for stacking silicon chip using the hybrid bonding technology of pressure welding point, which is characterized in that including：
Step 01：Two silicon chips with semiconductor devices are provided；Wherein, with the manufacture of preceding road technique on each silicon chip
Semiconductor device structure, the interconnection structure of postchannel process manufacture；Then, it is formed on the entire silicon chip of each silicon chip
Top layer dielectric layer and adhesive layer；There is pressure welding point region in the top layer dielectric layer and the adhesive layer；
Step 02：Using anisotropic etch process, the ditch that intermediate width is more than top width is formed in the pressure welding point region
Slot structure；
Step 03：Pressure welding point metal is grown in the groove structure, wherein the pressure welding point metal is by the groove structure top
Portion is closed, and reserved cavity is formed among the groove structure；
Step 04：The pressure welding point metal top is ground to the bonding layer surface；
Step 05：Two silicon chips for completing the step 04 are stacked, and are glued two silicon substrates by the adhesive layer
It is combined；
Step 06：The pressure welding point metal is bonded using heat treatment process, the pressure welding point is metal heated to be expanded and prolong
Exhibition, is filled with the reserved cavity in the groove structure.
2. according to the method described in claim 1, it is characterized in that, the groove structure has curved wall.
3. according to the method described in claim 1, it is characterized in that, the material of the top layer dielectric layer is silica.
4. according to the method described in claim 3, it is characterized in that, the thickness of the top layer dielectric layer is
5. according to the method described in claim 1, it is characterized in that, the material of the adhesive layer is silicon oxynitride, silica, nitrogen
One or more composite constructions in SiClx, calcium carbide.
6. according to the method described in claim 5, it is characterized in that, the thickness of the adhesive layer is
7. according to the method described in claim 1, it is characterized in that, in the step 03, using copper electroplating technology in the ditch
Pressure welding point metallic copper is grown in slot structure.
8. according to the method described in claim 1, it is characterized in that, in the step 04, using CMP process come
The pressure welding point metal top is ground to the bonding layer surface.
9. according to the method described in claim 8, it is characterized in that, the process of lapping monitors grinding by endpoint Detection
Terminal, and stop on the adhesive layer.
10. according to the method described in claim 1, it is characterized in that, the semiconductor device structure includes pixel cell structure；
The interconnection structure of the postchannel process manufacture includes metal layer and via layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610164465.XA CN105789069B (en) | 2016-03-22 | 2016-03-22 | The method for stacking silicon chip is formed using the hybrid bonding technology of pressure welding point |
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| CN201610164465.XA CN105789069B (en) | 2016-03-22 | 2016-03-22 | The method for stacking silicon chip is formed using the hybrid bonding technology of pressure welding point |
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| CN110875203B (en) * | 2018-09-04 | 2021-11-09 | 中芯集成电路（宁波）有限公司 | Wafer level packaging method and packaging structure |
| CN110945652A (en) | 2019-04-15 | 2020-03-31 | 长江存储科技有限责任公司 | Stacked three-dimensional heterogeneous memory device and forming method thereof |
| CN115602556A (en) * | 2021-07-09 | 2023-01-13 | 长鑫存储技术有限公司（Cn） | Chip bonding method and semiconductor chip structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101069457A (en) * | 2005-07-07 | 2007-11-07 | 揖斐电株式会社 | Multilayer printed wiring board |
| CN101197297A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Wafer press welding and bonding method and structure thereof |
| CN106229322A (en) * | 2016-07-27 | 2016-12-14 | 上海集成电路研发中心有限公司 | A kind of back-illuminated stack overall situation exposing pixels cellular construction and forming method thereof |
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| US8847366B1 (en) * | 2013-03-12 | 2014-09-30 | Jung-Chi HSIEN | Rectifier diode |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101069457A (en) * | 2005-07-07 | 2007-11-07 | 揖斐电株式会社 | Multilayer printed wiring board |
| CN101197297A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Wafer press welding and bonding method and structure thereof |
| CN106229322A (en) * | 2016-07-27 | 2016-12-14 | 上海集成电路研发中心有限公司 | A kind of back-illuminated stack overall situation exposing pixels cellular construction and forming method thereof |
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