CN1057649C - Frequency state discriminating device with hysteresis - Google Patents
Frequency state discriminating device with hysteresis Download PDFInfo
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- CN1057649C CN1057649C CN93116475A CN93116475A CN1057649C CN 1057649 C CN1057649 C CN 1057649C CN 93116475 A CN93116475 A CN 93116475A CN 93116475 A CN93116475 A CN 93116475A CN 1057649 C CN1057649 C CN 1057649C
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Abstract
The present invention relates to a frequency state discriminating device with hysteresis, which is used for discriminating the frequency of an input signal. The device comprises a present state circuit and a next state control circuit, wherein the present state circuit responds to a clock signal and a control signal and outputs a present state value signal having a plurality of bits, and a frequency discriminating signal; the next state control circuit responds to the present state value signal and the input signal, and outputs a control signal so that the relation between frequency discriminating signal and the frequency of the input signal has histeresis.
Description
The present invention relates to a frequency discrimination circuit, and more particularly, to a state machine having hysteresis.
Environmental protection is a consistent goal of the world-wide visual industry, and energy conservation is also one of the important measures for environmental protection. In the monitor industry, power saving monitors have been the subject of full force from various manufacturers.
In the interface control signal Standard currently set by the Video Equipment Standard Association-VESA (Video Equipment Standard Association-VESA), a frequency of a Video horizontal synchronization signal of more than 10 khz indicates that a signal is present, and if less than 10 hz, the signal is not present. Meanwhile, a vertical synchronization signal frequency of more than 20 Hz indicates the presence of a signal, and less than 10 Hz indicates the absence of a signal. This standard specification, as shown by the state of the vertical synchronization signal in fig. 1, has a hysteresis. That is, it is determined to be present when the frequency of the vertical synchronization signal is discriminated to exceed 20 hz (state 1), and is determined to be absent later when it is discriminated to be below 10 hz (state 0).
When the control circuit in the monitor identifies that the horizontal or vertical synchronous signal is absent, most of the power supply can be turned off, so that the monitor is in a sleep state, and the energy is saved.
Linear circuits with hysteresis are extremely difficult to implement, require many and complex parts, and are also costly.
In the known linear frequency discrimination circuit, an integrating circuit is adopted, and a comparator is used for discriminating the voltage obtained by integration, so that a plurality of parts are required and the circuit is complex. The digital frequency discrimination circuit can use a counter to count the number of signal pulses within a certain time, and then use a logic circuit to solve the requirement of hysteresis.
The invention aims to provide a State machine (State machine) which can achieve the effects and purposes of frequency discrimination and hysteresis by a State switching mode.
The object of the present invention is achieved by a frequency discrimination state device having a hysteresis late image for discriminating a frequency of an input signal, comprising:
a present state circuit responsive to a clock signal and a control signal for outputting a present state value signal having a plurality of bits and a frequency discrimination signal; the present state circuit includes a first flip-flop responsive to the clock signal and the control signal to output a first bit of a present state value signal; the present state circuit comprises a second flip-flop, responsive to the clock signal and the control signal, outputting a second bit of the present state value signal; the present state circuit includes a counter responsive to the clock signal, control signal and input signal to output other bits of the present state value signal;
and the secondary state control circuit at least comprises three AND gates, and the three AND gates respond to a current state value signal and the input signal and output the control signal so that the relation between the frequency discrimination signal and the frequency of the input signal has hysteresis.
The basic concept of the present invention and its preferred embodiments will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings. Wherein,
fig. 1 shows the criteria for VESA to vertical synchronization signal.
FIG. 2 is a functional block diagram of a state device of the present invention.
Fig. 3 shows a preferred embodiment of the present invention.
The state transitions corresponding to four different input signal frequencies are disclosed in fig. 4.
Referring to fig. 2, the frequency discrimination state device with hysteresis of the present invention includes a current state circuit 21 and a first state control circuit 22. The present status circuit 21 outputs a present status value signal 25 and a frequency discrimination signal 26 in response to a clock signal 23 and a control signal 24. The present state value signal 25 has a plurality of binary bits.
The sub-state control circuit 22 outputs the control signal 24 in response to the present state value signal 25 and the input signal 27 so that the relationship between the frequency discrimination signal 26 and the frequency of the input signal 27 has hysteresis as shown in fig. 1.
The operation of the present invention is described below in terms of an actual state transition table. It is assumed that the frequency of the clock signal 23 is 128 hz.
For convenience of the following description, the most significant bit, the second most significant bit, and the least significant bit of the state values in table one are simply referred to as the first bit, the least significant bit is simply referred to as the second bit, and the other bits are simply referred to as the least significant bit. For example, 0 in 01B is the first bit, 1 is the second bit, and B is the other bit.
When the frequency of the clock signal 23 is 128 hz, every 12 clock pulses is about 100 microseconds, i.e. 12 clock pulses correspond to one cycle of a signal having a frequency of 10 hz. And 6 clock pulses correspond to one period of a 20 hz signal.
When the input signal 27 is not active, the current state circuit 21 is controlled by the control signal 24 and the clock signal 23, and the output value of the current state signal 25 is cycled between 000-00B. I.e., 000 → 001 → … → 00B → 000 …, and so on.
When the input signal 27 is asserted for the first time, regardless of the value of the current state signal 25, the control signal 24 is asserted, and the current state signal transitions to 010, as shown in the third column of Table one, and begins cycling through 010-01B. That is, from 010 → 011 → …, if the input signal 27 is not active again while the current state signal 25 is cycled to 01B, the current state signal 25 transitions back to 000, as indicated by the last row in the fifth column. This situation indicates that the frequency of the input signal 27 is now close to zero.
If the input signal 27 is operating for the second time between the state values of the current state value signal 016-01B, indicating that the input signal frequency is 10-20 Hz, under the influence of the control signal 24, the current state value signal 25 transitions to 010 as shown in the last six rows of the sixth column and begins cycling through the state values between 010-01B, i.e., 010 → 011 → ….
If the input signal 27 is active a second time between the state values of 010-015, indicating that the input signal is greater than 20 hz, the current state signal 25 transitions to 110 as shown in the sixth row under the influence of the control signal 24 and begins cycling between the state values between 110-11B. I.e., 110 → 111 → … 11A.
If the input signal 27 is again active before the current state value signal is 11B (excluding 11B), indicating that the input signal frequency is greater than 10 hz, under the influence of the control signal 24, the current state value signal 25 transitions to 110 as shown in the ninth column and cycles back through the state values of 110-11B, etc., creating hysteresis. The frequency discrimination signal 26 is 1 even if the frequency is less than 20 hz.
If the input signal 27 is not active again until the current state value signal is 11B (excluding 11B), indicating that the input signal frequency is less than 10 Hz, the current state value transitions to 000, as indicated by the last column of the eighth row, and cycles back through the state values of 000-00B.
The frequency discrimination signal 26 is obtained by performing a NOR (NOR) operation on the inverted values of the first two bits of the current state signal value 25, and for example, the frequency discrimination signal 26 is 1 and is in the present state only when the first two bits of the state value are both 1. Otherwise, the frequency discrimination signals 26 are all 0 and are in the non-existent state, as shown in FIG. 1.
The above description of FIG. 2 and Table one may be further understood in conjunction with a preferred embodiment of the present invention, as illustrated in FIG. 3.
As shown in FIG. 3, the present state circuit of the preferred embodiment of the present invention includes a first flip-flop 211, a second flip-flop 211, a counter 213, and a NOR gate. The output of the Q terminal of the first flip-flop 211 is the first bit of the current state signal 25, the output of the Q terminal of the second flip-flop 212 is the second bit of the current state signal 25, the QD, QC, QB, QA output terminals of the counter 213 output other bit values 0-B (hexadecimal), i.e., 0 (hexadecimal) is equal to 0000 output of the counter 213, and B (hexadecimal) is equal to 1011 output value of the counter 213. Counter 213 is controlled by signal terminal B, and is zeroed every 12 clock pulses. After the input signal 27 is activated, the counter 213 is also reset to zero once when the next clock signal 27 enters.
The two inputs of the nor gate 214 are connected to the-Q outputs of the first flip-flop 211 and the second flip-flop 212, respectively, and the output frequency discrimination signal 26 of the nor gate 214 is 1 (present) only when the first and second bits of the present status signal are 11, which indicates that the frequency of the input signal 27 is greater than 20 hz. When the first and second bits are 00 or 01, the output frequency discrimination signal 26 is 0 (not present).
When the present state circuit 21 employs the components shown in FIG. 3, the sub-state control circuit 22 can be designed as the right half circuit in FIG. 3 to achieve the frequency discrimination and hysteresis of the present invention. Such design is intended to be within the scope of the present invention as it would appear to those skilled in the art upon reading the present specification in equivalents thereof.
In addition, the detailed design of the present state circuit in FIG. 3 can be varied within a wide range of equivalents, and should fall within the intended scope of the present invention.
In addition, the state transition table such as table one is only an example of the idea of the present invention, and different designers can design other state value transitions, so as to achieve the purpose and efficacy of the present invention. For example, when the frequency of the input signal 27 is greater than 20 Hz, the state may be defined as 100, rather than 110 of Table one. If so, the detailed design of the present state circuit 21 and the sub-state circuit 22 in FIG. 3 need to be changed, but the spirit still does not depart from the concept of the present invention, as shown in FIG. 2.
In fig. 4, the different changes of the state of the present state value signal 25 are illustrated in the case of four different input signals 27.
In fig. 4(a), when the input signal 27 is activated once when the current state value signal 27 is 002, the next current state value transitions to 010 and starts to cycle between 010-01B, and since no input signal 27 is activated again thereafter, the frequency discrimination signal 26 is not activated (absent), which corresponds to the input signal frequency approaching zero.
In FIG. 4(B), the first action of the input signal 27 occurs when the current state value signal is 002, the next current state value transitions to 010 and begins cycling between 010-01B, but since no second input signal 27 has occurred during the cycle to 01B, the current state value transitions to 000 and cycles again between 000-00B. However, during the loop, when the current state value is 003, the input signal 27 is activated again, and the current state value signal 25 immediately transitions to 010. This situation indicates that the frequency of the input signal 27 is less than 10 hz and the frequency discrimination signal 26 is not active (not present).
In fig. 4(c), the input signal 27 is first activated when the current state value signal is 002, the current state value transitions to 010 and begins cycling through 010-01B, and when cycling to 018, the input signal 27 is second activated, the current state value transitions to 010 and re-cycles, and the input signal 27 is activated for the third time when the current state value is 016. This situation indicates that the frequency of the input signal 27 is greater than 10 hz but less than 20 hz and the frequency discrimination signal 26 is not active (absent).
In fig. 4(d), when the current state value signal is 004, the input signal 27 is activated for the first time, the current state value changes to 010 and starts to cycle between 010-01B, when the loop reaches 014, the input signal 27 is activated for the second time, the current state value changes to 110 and starts to cycle between 110-11B, when the input signal 27 is activated again at the current state value 113, the current state value changes to 110 and is cycled again. The input signal 27 is again active when the current state value cycles to 114. This situation indicates that the frequency of the input signal 27 is greater than 20 hz and the frequency discrimination signal 26 is active (present).
If the upper and lower limit frequencies of the hysteresis are to be changed, the clock signal 23 can start with without changing other variables. For example, if the clock signal is raised from 128 hz to 1280 hz, and the state transition table of table one is still used, then the lower limit in fig. 1 is 100 hz and the upper limit is 200 hz.
If only the lower limit frequency of the hysteresis is to be changed, the other variables are not changed, but the number of states in the first table is changed, for example, the lower limit is 5 Hz when the number of states in the first table is changed from 12 (0-B) to 24.
If only the upper limit frequency of the hysteresis is to be changed, other variables may not be changed, and the number of the state values in the sixth row of the table I is only required to be changed to 110. For example, if the 110 value corresponding to the status value 015 in the fourth column of the table is changed to 010 and the others are maintained, the upper limit frequency is increased to 25 Hz.
The above-described variations are intended to be within the scope of the present invention.
It should be noted that once the state transition table in table one is redefined, the detailed design in fig. 3 must be changed to accomplish the purpose of different state transitions.
Claims (13)
1. A frequency discrimination state machine having hysteresis for discriminating the frequency of an input signal, comprising:
a present state circuit responsive to a clock signal and a control signal for outputting a present state value signal having a plurality of bits and a frequency discrimination signal; the present state circuit includes a first flip-flop responsive to the clock signal and the control signal to output a first bit of a present state value signal; the present state circuit comprises a second flip-flop, responsive to the clock signal and the control signal, outputting a second bit of the present state value signal; the present state circuit includes a counter responsive to the clock signal, control signal and input signal to output other bits of the present state value signal;
and the secondary state control circuit at least comprises three AND gates, and the three AND gates respond to a current state value signal and the input signal and output the control signal so that the relation between the frequency discrimination signal and the frequency of the input signal has hysteresis.
2. The state machine of claim 1, wherein the frequency discrimination signal is active when the frequency of the input signal exceeds a high limit and inactive when the frequency is less than a low limit.
3. The state machine of claim 2, wherein the upper limit is not equal to the lower limit.
4. The state machine of claim 2, wherein the upper limit is 20 hz and the lower limit is 10 hz.
5. The state machine of claim 2, wherein the upper limit is 10 khz and the lower limit is 10 hz.
6. The state machine of claim 4, wherein the clock signal has a frequency of 128 Hz.
7. The state machine of claim 6, wherein the current state value signal comprises different state values of 000, 001, 002, 003, 004, 005, 006, 007, 008, 009, 00A, 00B, 010, 011, 012, 013, 014, 015, 016, 017, 018, 019, 01A, 01B, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 11A, 11B.
8. The state machine of claim 7, wherein the present state value signal cycles between state values of 000-00B when the input signal is not active.
9. The state machine of claim 7, wherein when the input signal is first asserted, the present state value signal transitions to 010 and begins cycling through state values of 010-01B, etc.
10. The state device of claim 9, wherein when the input signal is asserted a second time between the current state value signal being 010-015, the current state value signal transitions to 110 and begins cycling through 110-11B, etc. state values.
11. The state machine of claim 9, wherein when said input signal is activated a second time between states of current state value signal 016-01B, the current state value signal transitions to 010 and re-cycles between state values of 010-01B.
12. The state machine of claim 10, wherein when the input signal is activated again without 11B prior to the current state value signal 11B, the current state value signal transitions to 110 and cycles back through 110-11B state values.
13. The state machine of claim 10, wherein when the input signal is not active again until the current state value signal is 11B, but does not contain 11B, the current state value transitions to 000 and cycles back through the state values of 000-00B.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN93116475A CN1057649C (en) | 1993-08-19 | 1993-08-19 | Frequency state discriminating device with hysteresis |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN93116475A CN1057649C (en) | 1993-08-19 | 1993-08-19 | Frequency state discriminating device with hysteresis |
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| Publication Number | Publication Date |
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| CN1099213A CN1099213A (en) | 1995-02-22 |
| CN1057649C true CN1057649C (en) | 2000-10-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN93116475A Expired - Fee Related CN1057649C (en) | 1993-08-19 | 1993-08-19 | Frequency state discriminating device with hysteresis |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN86105323A (en) * | 1986-08-29 | 1987-12-09 | 陈策沾 | Full-automatic electric shock safety equipment |
| CN1051465A (en) * | 1989-11-02 | 1991-05-15 | 孙东红 | A kind of general protective circuit for electric motor |
| CN1016033B (en) * | 1987-08-07 | 1992-03-25 | 三井石油化学工业株式会社 | Signal discriminator and method of signal discrimination |
-
1993
- 1993-08-19 CN CN93116475A patent/CN1057649C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN86105323A (en) * | 1986-08-29 | 1987-12-09 | 陈策沾 | Full-automatic electric shock safety equipment |
| CN1016033B (en) * | 1987-08-07 | 1992-03-25 | 三井石油化学工业株式会社 | Signal discriminator and method of signal discrimination |
| CN1051465A (en) * | 1989-11-02 | 1991-05-15 | 孙东红 | A kind of general protective circuit for electric motor |
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| Publication number | Publication date |
|---|---|
| CN1099213A (en) | 1995-02-22 |
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