CN105762103A - Semiconductor structure and forming method therefor - Google Patents
Semiconductor structure and forming method therefor Download PDFInfo
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- CN105762103A CN105762103A CN201610130582.4A CN201610130582A CN105762103A CN 105762103 A CN105762103 A CN 105762103A CN 201610130582 A CN201610130582 A CN 201610130582A CN 105762103 A CN105762103 A CN 105762103A
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 150000002500 ions Chemical class 0.000 claims abstract description 148
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 238000002955 isolation Methods 0.000 claims abstract description 67
- 239000002019 doping agent Substances 0.000 claims description 77
- -1 phosphonium ion Chemical class 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 229910001439 antimony ion Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 238000002347 injection Methods 0.000 abstract description 3
- 239000007924 injection Substances 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 17
- 238000005468 ion implantation Methods 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000002939 deleterious effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910001449 indium ion Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a semiconductor structure and a forming method therefor. The method comprises the steps: providing a substrate; forming an isolation structure on the substrate, wherein the isolation structure is used for dividing the substrate into a first region and a second region; forming a first well region in the first region of the substrate; forming a second well region in the second region of the substrate, wherein the doping type of the second well region is different from the doping type of the first well region; forming a pseudo grid structure located on the isolation structure; taking the pseudo grid structure as a mask, and forming a second heavily-doped region in the second well region, wherein the doping type of the second heavily-doped region is the same as the doping type of the second well region; taking the pseudo grid structure as the mask, and forming a first heavily-doped region in the first well region, wherein the doping type of the first heavily-doped region is the same as the doping type of the first well region. The method forms the pseudo grid structure on the isolation structure at the junction of the first and second regions, and the pseudo grid structure can serve as an ion injection mask during the forming of the doped regions, thereby preventing doping ions in the heavily-doped regions from entering the adjacent well region or heavily-doped region, and improving the breakdown voltage of an adjacent device.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of semiconductor structure and forming method thereof.
Background technology
In fabrication of semiconductor device, frequently with fleet plough groove isolation structure (ShallowTrenchIsolation, or local oxidation of silicon structure (LocalOxidationofSilicon STI), LOCOS) as the well region isolation structure between p-well (Pwell) and N trap (Nwell), to realize the isolation of device.Two adjacent well regions are formed in substrate, are also formed with heavily doped region in corresponding well region, be formed with isolation structure, and the degree of depth of described adjacent well region is more than the degree of depth of described isolation structure between described adjacent well region.By described well region isolation structure, it is possible to suppress the break-through of adjacent devices, reduce the electric leakage of device.
But, the problem that the well region isolation structure of prior art declines easily caused by semiconductor device electric property.
Summary of the invention
The problem that this invention address that is to provide a kind of semiconductor structure and forming method thereof, optimizes the electric property of semiconductor device.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure, comprises the steps: to provide substrate；Described substrate forms isolation structure, for described substrate being divided into first area and second area；The first well region is formed in the substrate of described first area；Forming the second well region in described second area substrate, the doping type of described second well region is different from the dopant ion type of described first well region；Form the pseudo-grid structure being positioned on described isolation structure；With dummy gate structure for mask, forming the second heavily doped region in described second well region, described second heavily doped region is identical with the dopant ion type of described second well region；With dummy gate structure for mask, forming the first heavily doped region in described first well region, described first heavily doped region is identical with the dopant ion type of described first well region.
Optionally, the feature sizes of dummy gate structure is less than the feature sizes of described isolation structure.
Optionally, the step forming described first heavily doped region includes: carry out N-type ion doping；The step forming described second heavily doped region includes: carry out P type ion doping；Or, the step forming described first heavily doped region includes: carry out P type ion doping；The step forming described second heavily doped region includes: carry out N-type ion doping；The step carrying out N-type ion doping includes: the ion of doping is phosphonium ion, arsenic ion or antimony ion, and ion energy is 2Kev to 80Kev, and ion dose is 3E13 to 8E15 atom per square centimeter；The step carrying out P type ion doping includes: the ion of doping is boron ion, and ion energy is 2Kev to 120Kev, and ion dose is 3E13 to 5E15 atom per square centimeter.
Optionally, the step forming the pseudo-grid structure being positioned on described isolation structure includes: form gate oxidation films at described substrate surface；Gate electrode film is formed on described gate oxidation films surface；Graph layer is formed on described gate electrode film surface；With described graph layer for mask, adopt dry plasma etch technique, etching removes the part of grid pole film on described first well region and on the second well region and part gate oxidation films, retain the gate electrode film on described isolation structure and gate oxidation films, form pseudo-gate oxide and pseudo-gate electrode layer, dummy gate oxide layer and pseudo-gate electrode layer to be used for constituting pseudo-grid structure；Remove described graph layer.
Optionally, described forming method also includes: before forming described first heavily doped region, with dummy gate structure for mask, the first light doped region is formed in described first well region, described first light doped region is identical with the dopant ion type of described first heavily doped region, and the degree of depth of the described first light doped region is less than the degree of depth of described first heavily doped region；Before forming described second heavily doped region, with dummy gate structure for mask, the second light doped region is formed in described second well region, described second light doped region is identical with the dopant ion type of described second heavily doped region, and the degree of depth of the described second light doped region is less than the degree of depth of described second heavily doped region.
Accordingly, the present invention also provides for a kind of semiconductor structure, including: substrate；It is arranged in the isolation structure of described substrate, for described substrate being divided into first area and second area；First well region, is positioned at described first area substrate；Second well region, is positioned at described second area substrate, and the doping type of described second well region is different from the doping type of described first well region；Pseudo-grid structure, is positioned on described isolation structure；First heavily doped region, is positioned at the first well region of dummy gate structure side；Second heavily doped region, is positioned at the second well region of dummy gate structure opposite side.
Optionally, the feature sizes of dummy gate structure is less than the feature sizes of described isolation structure.
Optionally, the dopant ion type of described first heavily doped region is n-type doping ion, and the dopant ion of described second heavily doped region is P type dopant ion；Or, the dopant ion type of described first heavily doped region is P type dopant ion, and the dopant ion of described second heavily doped region is n-type doping ion；Described n-type doping ion is phosphonium ion, arsenic ion or antimony ion, and the concentration of dopant ion is 1E17 atoms per cubic centimeter to 5E20 atoms per cubic centimeter；Described P type dopant ion is boron ion, and the concentration of dopant ion is 5E16 atoms per cubic centimeter to 5E20 atoms per cubic centimeter.
Optionally, dummy gate structure includes: is positioned at the pseudo-gate oxide on described isolation structure and is positioned at the pseudo-gate electrode layer on dummy gate oxide layer surface.
Optionally, described semiconductor structure also includes the first light doped region and the second light doped region that are positioned at dummy gate structure both sides；Described first light doped region is positioned at described first heavily doped region, and the described first light doped region is identical with the dopant ion type of described first heavily doped region, and the degree of depth of the described first light doped region is less than the degree of depth of described first heavily doped region；Described second light doped region is positioned at described second heavily doped region, and the described second light doped region is identical with the dopant ion type of described second heavily doped region, and the degree of depth of the described second light doped region is less than the degree of depth of described second heavily doped region.
Compared with prior art, technical scheme has the advantage that
The present invention by forming pseudo-grid structure on the isolation structure of first area and second area intersection, dummy gate structure can as formed heavily doped region time ion implantation mask, the dopant ion avoiding the first heavily doped region enters in the second well region or the second heavily doped region, or the dopant ion avoiding the second heavily doped region enters in the first well region or the first heavily doped region, such that it is able to improve the breakdown voltage of adjacent devices, optimize and electrically isolate effect, and then improve the electric property of semiconductor device.
In alternative, dummy gate structure does not possess electrical functionality, therefore the electric property of semiconductor device will not produce impact, have processing compatibility.
Accompanying drawing explanation
Fig. 1 and Fig. 2 is the structural representation that forming method one embodiment of prior art semiconductor structure is corresponding；
Fig. 3 to Figure 10 is the structural representation that forming method one embodiment of semiconductor structure of the present invention is corresponding.
Detailed description of the invention
By background technology it can be seen that the problem that declines easily caused by semiconductor device electric property of the well region isolation structure of prior art.Analyze its reason to be in that:
As it is shown in figure 1, the structure of well region isolation structure one embodiment includes: substrate 100；It is positioned at adjacent N trap (Nwell) 120 and the p-well (Pwell) 130 of described substrate 100；Being formed with isolation structure 110 (such as ShallowTrenchIsolation, STI) between described N trap 120 and p-well 130, described isolation structure 110 is the well region isolation structure between adjacent described N trap 120 and p-well 130；It is formed with N-type heavily doped region 140 near described isolation structure 110 side in described N trap 120, is used for forming N-type device；It is formed with P type heavily doped region 150 near described isolation structure 110 side in described p-well 130, is used for forming P-type device.By described well region isolation structure, it is possible to suppress the break-through of adjacent devices.
Reduction along with device feature size, the electric property of semiconductor device is also more and more sensitive to the spacing of the heavily doped region in heavily doped region to adjacent well region or adjacent well region, the characteristic size of well region isolation structure (such as STI) is increasing on the impact of the electric property of semiconductor device, when well region isolation structure feature size downsizing to such an extent as to can comparable with lithography alignment deviation nargin time, the Alignment Process error of heavily doped region photoetching may result in the ion of described heavily doped region and is injected into adjacent well region mistakenly.
As in figure 2 it is shown, illustrate to form N-type heavily doped region 140.When the Alignment Process generation deviation forming N-type heavily doped region 140, when forming position such as photoresist layer 200 offsets A1, accordingly, the forming position of described N-type heavily doped region 140 can offset A2, and A1 and A2 is equal, cause that part described N-type heavily doped region 140 is positioned at described p-well 130 or P type heavily doped region 150.
Additionally, before forming described N-type heavily doped region 140, also include: by the light doping process 142 of N-type, in described N trap 120, form the light doped region (not shown) of N-type.Accordingly, the Alignment Process of the light doped region photoetching of described N-type is also susceptible to deviation, thus causing that the forming position of the light doped region of described N-type is also susceptible to skew, and owing to forming the ion implanting direction of the light doped region of described N-type and described substrate 100 surface there is angle, and then it is easily caused the part light doped region of described N-type 160 and is positioned at described P type heavily doped region 150.
To sum up, precision controlling difficulty owing to forming the Alignment Process of doped region is bigger, it is easily caused heavily doped region and light doped region is formed in adjacent well region or heavily doped region, thus causing the resistance decrease of adjacent heavily doped region, and then reduce well region isolation structure electrically isolate effect, reduce the breakdown voltage between adjacent devices.
In order to solve described technical problem, the present invention provides the manufacture method of a kind of flash memory structure, including: substrate is provided；Described substrate forms isolation structure, for described substrate being divided into first area and second area；The first well region is formed in the substrate of described first area；Forming the second well region in described second area substrate, the doping type of described second well region is different from the dopant ion type of described first well region；Form the pseudo-grid structure being positioned on described isolation structure；With dummy gate structure for mask, forming the second heavily doped region in described second well region, described second heavily doped region is identical with the dopant ion type of described second well region；With dummy gate structure for mask, forming the first heavily doped region in described first well region, described first heavily doped region is identical with the dopant ion type of described first well region.
The present invention by forming pseudo-grid structure on the isolation structure of first area and second area intersection, dummy gate structure can as formed heavily doped region time ion implantation mask, the dopant ion avoiding the first heavily doped region enters in the second well region or the second heavily doped region, or the dopant ion avoiding the second heavily doped region enters in the first well region or the first heavily doped region, such that it is able to improve the breakdown voltage of adjacent devices, optimize and electrically isolate effect, and then improve the electric property of semiconductor device.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Fig. 3 to Figure 10 is the structural representation that forming method one embodiment of semiconductor structure of the present invention is corresponding.
With reference to Fig. 3, it is provided that substrate 300.
Described substrate 300 provides technique platform for being subsequently formed device.
The material of described substrate 300 can be silicon, germanium, SiGe, carborundum, GaAs or gallium indium, and described substrate 300 can also be the silicon substrate on insulator or the germanium substrate on insulator.In the present embodiment, described substrate 300 is silicon substrate.
With reference to Fig. 4, described substrate 300 forms isolation structure 310, for described substrate 300 being divided into first area I and second area II.
In the present embodiment, described first area I substrate 300 is used for being formed N-type device, and described second area II substrate 300 is used for forming P-type device.
In another embodiment, described first area substrate can be also used for forming P-type device, and described second area substrate can be also used for forming N-type device.In another embodiment, described first area substrate and second area substrate can be also used for forming same kind of device.
Described isolation structure 310 is as well region isolation structure, for follow-up the first well region formed in described first area I substrate 300 and the second well region formed in described second area II substrate 300 are isolated.
It should be noted that in the present embodiment, described isolation structure 310 is shallow groove isolation layer, but is not limited to shallow groove isolation layer.
Specifically, the step forming described isolation structure 310 includes: by etching technics, forms groove (not shown) in described substrate 300；Spacer material layer (not shown) is filled in described groove；Described spacer material layer also covers described substrate 300 surface；Removing the spacer material layer higher than described substrate 300 surface, form isolation structure 310, described substrate 300 is divided into first area I and second area II by described isolation structure 310.
The material of described isolation structure 310 can be silicon oxide, silicon nitride or silicon oxynitride.In the present embodiment, the material of described isolation structure 310 is silicon oxide.
In the present embodiment, in order to improve filling perforation (gap-filling) ability of spacer material layer, adopt mobility chemical vapour deposition (CVD) (FCVD, FlowableCVD) or high vertical wide ratio chemical vapor deposition method (HARPCVD), form described spacer material layer；Chemical mechanical milling tech is adopted to remove the spacer material layer higher than described substrate 300 surface.
With reference to Fig. 5, in described first area I substrate 300, form the first well region 320.
In the present embodiment, described first area I is used for forming N-type device, and accordingly, described first well region 320 is N-type well region, namely has N-type ion in described first well region 320, and described N-type ion includes phosphonium ion or arsenic ion.
In another embodiment, described first area is used for being formed P-type device, and described first well region can also is that P type trap zone.
Specifically, the step forming described first well region 320 includes: form the first graph layer (not shown) on substrate 300 surface of described second area II；With described first graph layer for mask, the substrate 300 of described first area I is carried out the first trap injection technology, forms the first well region 320；Remove described first graph layer.
With continued reference to Fig. 5, forming the second well region 330 in described second area II substrate 300, the doping type of described second well region 330 is different from the dopant ion type of described first well region 320.
In the present embodiment, described second area II is used for forming P-type device, and accordingly, described second well region 330 is P type trap zone, namely has P type ion in described second well region 330, and described P type ion includes boron ion or indium ion.
In another embodiment, described second area is used for being formed N-type device, and described second well region can also is that N-type well region.
Specifically, the step forming described second well region 330 includes: form second graph layer (not shown) on substrate 300 surface of described first area I；With described second graph layer for mask, the substrate 300 of described second area II is carried out the second trap injection technology, forms the second well region 330；Remove described second graph layer.
It should be noted that in the present embodiment, form described first well region 320 and be subsequently formed described second well region 330.In another embodiment, described second well region can also be previously formed being formed described first well region.
With reference to Fig. 6, form the pseudo-grid structure 340 being positioned on described isolation structure 310.
Dummy gate structure 340 is as being subsequently formed heavily doped region and the ion implantation mask of light doped region.
Specifically, the step forming dummy gate structure 340 includes: form gate oxidation films on described substrate 300 surface；Gate electrode film is formed on described gate oxidation films surface；The 3rd graph layer (not shown) is formed on described gate electrode film surface；With described 3rd graph layer for mask, adopt dry plasma etch technique, etching removes the part of grid pole film on described first well region 320 and on the second well region 330 and part gate oxidation films, retain the gate electrode film on described isolation structure 310, form pseudo-gate oxide (not shown) and pseudo-gate electrode layer (not shown), dummy gate oxide layer and pseudo-gate electrode layer to be used for constituting pseudo-grid structure 340；Remove described 3rd graph layer.
The material of dummy gate oxide layer is silicon oxide, and the material of dummy gate electrode layer is polysilicon, silicon oxide, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon.In the present embodiment, the material of dummy gate electrode layer is polysilicon.
It should be noted that the feature sizes of dummy gate structure 340 is unsuitable excessive, also unsuitable too small.nullOwing to dummy gate structure 340 is as being subsequently formed heavily doped region and the ion implantation mask of light doped region，If the feature sizes of dummy gate structure 340 is too small，The DeGrain of ion implantation mask，In the follow-up process forming the first light doped region or the first heavily doped region in described first well region 320，The dopant ion being easily caused the described first light doped region or the first heavily doped region is injected in described second well region 330，Or，In the follow-up process forming the second light doped region or the second heavily doped region in described second well region 330，Be easily caused the described second light doped region or the second heavily doped region dopant ion be injected in described first well region 320，Particularly in ion implanting Alignment Process occur skew serious when，Light doped region or heavily doped region are also easy to be formed in adjacent heavily doped region，Thus causing the decline of adjacent devices breakdown voltage，Make to electrically isolate deleterious；If the feature sizes of dummy gate structure 340 is excessive, easily affect the distribution of shallow doped region or heavily doped region, cause that the region formed in hope is formed without described shallow doped region or heavily doped region, the first heavily doped region or the second heavily doped region that even result in dummy gate structure 340 and be subsequently formed overlap, thus affecting the electric property of device.
In the present embodiment, the feature sizes of dummy gate structure 340 is less than the feature sizes of described isolation structure 310, and the distance on the border of dummy gate structure 340 and the border of adjacent described isolation structure 310 is 50nm to 70nm.In a specific embodiment, the feature sizes of dummy gate structure 340 is 0.13 μm.
Also, it should be noted formed on described isolation structure 310 in the step of dummy gate structure 340, in device region substrate (not shown), also form the grid structure (not shown) of semiconductor device.Therefore, the formation process of dummy gate structure 340, reduce extra process costs.
It should be noted that after forming dummy gate structure 340, described forming method also includes: form side wall (sign) at dummy gate structure 340 sidewall.In the present embodiment, the material of described side wall is the laminated construction of silicon oxide layer-silicon nitride-silicon oxide layer (ONO, Oxide-Nitride-Oxide).In another embodiment, the material of described side wall can also be the laminated construction of silicon oxide layer-silicon nitride layer (ON, Oxide-Nitride).
In conjunction with reference to Fig. 7 and Fig. 8, after forming described side wall (sign), described forming method also includes: with dummy gate structure 340 for mask, adopt the first light doping process 351 (as shown in Figure 7), described second well region 330 is carried out ion doping, in described second well region 330, forms the second light doped region (not shown)；With dummy gate structure 340 for mask, adopt the second light doping process 341 (as shown in Figure 8), described first well region 320 is carried out ion doping, in described first well region 320, form the first light doped region (not shown).
It should be noted that, in forming the technical process of the described first light doped region and the second light doped region, dummy gate structure 340 is as ion implantation mask, therefore, the dopant ion that can avoid the described first light doped region is injected in described second well region 330 mistakenly, and the dopant ion of the described second light doped region is injected in described first well region 340 mistakenly.
With reference to Fig. 9, with dummy gate structure 340 for mask, forming the second heavily doped region 350 in described second well region 330, described second heavily doped region 350 is identical with the dopant ion type of described second well region 330.
Specifically, the step forming described second heavily doped region 350 includes: form the 4th graph layer 400 on substrate 300 surface, described first area I, described 4th graph layer 400 also covers the sidewall of dummy gate structure 340；With described 4th graph layer 400 and pseudo-grid structure 340 for mask, adopt the first heavy doping technique 352, described second well region 330 is carried out ion doping, forms the second heavily doped region 350；Remove described 4th graph layer 400.
Wherein, the step forming described second heavily doped region 350 includes: described second well region 330 is carried out N-type ion doping or P type ion doping.In the present embodiment, described second well region 330 being carried out P type ion doping, the dopant ion type of described second heavily doped region 350 is P type ion.The step carrying out described P type ion doping includes: the ion of doping is boron ion, and ion energy is 2Kev to 120Kev, and ion dose is 3E13 to 5E15 atom per square centimeter.
It should be noted that the dopant ion type of described second heavily doped region 350 is identical with the dopant ion type of the described second light doped region, the degree of depth of described second heavily doped region 350 is the degree of depth of light doped region more than described second.
Also, it should be noted in the technical process forming described second heavily doped region 350, dummy gate structure 340 is as ion implantation mask, it can thus be avoided the dopant ion of described second heavily doped region 350 is injected in described first well region 340 mistakenly.
With reference to Figure 10, with dummy gate structure 340 for mask, forming the first heavily doped region 360 in described first well region 320, described first heavily doped region 360 is identical with the dopant ion type of described first well region 320.
Specifically, the step forming described first heavily doped region 360 includes: form the 5th graph layer 410 on described second area II substrate 300 surface, described 5th graph layer 410 also covers the sidewall of dummy gate structure 340；With described 5th graph layer 410 and pseudo-grid structure 340 for mask, adopt the second heavy doping technique 342, described first well region 320 is carried out ion doping, forms the first heavily doped region 360；Remove described 5th graph layer 410.
Wherein, the step forming described first heavily doped region 360 includes: described first well region 320 is carried out N-type ion doping or P type ion doping.In the present embodiment, the doping type of described second well region 330 is different from the dopant ion type of described first well region 320, described second heavily doped region 350 is identical with the dopant ion type of described second well region 330, described first heavily doped region 360 is identical with the dopant ion type of described first well region 320, and the dopant ion type of described second heavily doped region 350 is P type ion, therefore, described first well region 320 is carried out N-type ion doping, and the dopant ion type of described first heavily doped region 360 is N-type ion.The step carrying out described N-type ion doping includes: the ion of doping is phosphonium ion, arsenic ion or antimony ion, and ion energy is 2Kev to 80Kev, and ion dose is 3E13 to 8E15 atom per square centimeter.
In another embodiment, the step forming described second heavily doped region includes: described second well region is carried out N-type ion doping, and accordingly, the step forming described first heavily doped region includes: described first well region is carried out P type ion doping.
It should be noted that the dopant ion type of described first heavily doped region 360 is identical with the dopant ion type of the described first light doped region, the degree of depth of described first heavily doped region 360 is the degree of depth of light doped region more than described first.
It can further be stated that, in the technical process forming described first heavily doped region 360, dummy gate structure 340 is as ion implantation mask, it can thus be avoided the dopant ion of described first heavily doped region 360 is injected in described second well region 330 or the second heavily doped region 350 mistakenly.
By forming pseudo-grid structure 340 on the isolation structure 310 of described first area I and second area II intersection, dummy gate structure 340 can as formed doped region time ion implantation mask, the dopant ion avoiding the described first light doped region or the first heavily doped region 360 enters in the region of described second well region 330 or the second heavily doped region 350, or, the dopant ion avoiding the described second light doped region or the second heavily doped region 350 enters in described first well region 320 or the first heavily doped region 360, such that it is able to improve the breakdown voltage of adjacent devices, optimize and electrically isolate effect, and then improve the electric property of semiconductor device.
With continued reference to Figure 10, accordingly, the present invention also provides for a kind of semiconductor structure, including:
Substrate 300；
It is arranged in the isolation structure 310 of described substrate 300, for described substrate 300 being divided into first area I and second area II；
First well region 320, is positioned at described first area I substrate 300；
Second well region 330, is positioned at described second area II substrate 300, and the doping type of described second well region 330 is different from the doping type of described first well region 320；
Pseudo-grid structure 340, is positioned on described isolation structure 310；
First heavily doped region 360, is positioned at the first well region 320 of dummy gate structure 340 side；
Second heavily doped region 350, is positioned at the second well region 330 of dummy gate structure 340 opposite side.
In the present embodiment, described first area I substrate 300 is used for being formed N-type device, and described second area II substrate 300 is used for forming P-type device.Accordingly, described first well region 320 is N-type well region, namely has N-type ion in described first well region 320, and described N-type ion includes phosphonium ion or arsenic ion；Described second well region 330 is P type trap zone, namely has P type ion in described second well region 330, and described P type ion includes boron ion or indium ion.
In another embodiment, described first area substrate can be also used for forming P-type device, and described second area substrate can be also used for forming N-type device.Accordingly, described first well region can also is that P type trap zone, and described second well region can also is that N-type well region.
In another embodiment, described first area substrate and second area substrate can be also used for being formed same kind of device, and described first well region and the second well region are same kind of well region.
The dopant ion type of described first heavily doped region 360 is n-type doping ion, and the dopant ion of described second heavily doped region 350 is P type dopant ion；Or, the dopant ion type of described first heavily doped region 360 is P type dopant ion, and the dopant ion type of described second heavily doped region 350 is n-type doping ion.Specifically, described n-type doping ion is phosphonium ion, arsenic ion or antimony ion, and the concentration of dopant ion is 1E17 atoms per cubic centimeter to 5E20 atoms per cubic centimeter；Described P type dopant ion is boron ion, and the concentration of dopant ion is 5E16 atoms per cubic centimeter to 5E20 atoms per cubic centimeter.
In the present embodiment, described first area I substrate 300 is used for being formed N-type device, and described second area II substrate 300 is used for forming P-type device.Accordingly, the dopant ion type of described first heavily doped region 360 is N-type ion, and the dopant ion type of described second heavily doped region 350 is P type ion.
It should be noted that described semiconductor structure also includes the first light doped region (not shown) and the second light doped region (not shown) that are positioned at dummy gate structure 340 both sides；Described first light doped region is positioned at described first heavily doped region 360, and the described first light doped region is identical with the dopant ion type of described first heavily doped region 360, and the degree of depth of the described first light doped region is less than the degree of depth of described first heavily doped region 360；Described second light doped region is positioned at described second heavily doped region 350, and the described second light doped region is identical with the dopant ion type of described second heavily doped region 350, and the degree of depth of the described second light doped region is less than the degree of depth of described second heavily doped region 350.
In the present embodiment, dummy gate structure 340 includes: is positioned at the pseudo-gate oxide (not shown) on described isolation structure 310 and is positioned at the pseudo-gate electrode layer (not shown) on dummy gate oxide layer surface.
The material of dummy gate oxide layer is silicon oxide, and the material of dummy gate electrode layer is polysilicon, silicon oxide, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon.In the present embodiment, the material of dummy gate electrode layer is polysilicon.
Dummy gate structure 340 is as the ion implantation mask in the described first light doped region, the first light doped region of heavily doped region 360, second and the second heavily doped region 350 forming process.
It should be noted that the feature sizes of dummy gate structure 340 is unsuitable excessive, also unsuitable too small.Owing to dummy gate structure 340 is as the described first light doped region, first heavily doped region 360, ion implantation mask in second light doped region and the second heavily doped region 350 forming process, if the feature sizes of dummy gate structure 340 is too small, the DeGrain of ion implantation mask, the dopant ion being easily caused the described first light doped region or described first heavily doped region 360 is injected in described second well region 330 or the second heavily doped region 350, or, the dopant ion being easily caused the described second light doped region or described second heavily doped region 350 is injected into described first well region 320 or the first heavily doped region 360, thus causing the decline of adjacent devices breakdown voltage, make to electrically isolate deleterious；If the feature sizes of dummy gate structure 340 is excessive, the dopant ion distribution of the described first light doped region, the first light doped region of heavily doped region 360, second and the second heavily doped region 350 is affected, even result in dummy gate structure 340 to overlap with described first heavily doped region 360 or the second heavily doped region 350, thus affecting the electric property of device.
In the present embodiment, the feature sizes of dummy gate structure 340 is less than the feature sizes of described isolation structure 310, and the distance on the border of dummy gate structure 340 and the border of adjacent described isolation structure 310 is 50nm to 70nm.In a specific embodiment, the feature sizes of dummy gate structure 340 is 0.13 μm.
By being positioned at the pseudo-grid structure 340 on described first area I and second area II intersection isolation structure 310, can avoid in the forming process of the described first light doped region, the first light doped region of heavily doped region 360, second and the second heavily doped region 350, the dopant ion that ionic type is contrary will not be doped into, such that it is able to improve the breakdown voltage of adjacent devices, optimize and electrically isolate effect, and then improve the electric property of semiconductor device.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. the forming method of a semiconductor structure, it is characterised in that including:
Substrate is provided；
Described substrate forms isolation structure, for described substrate being divided into first area and second area；
The first well region is formed in the substrate of described first area；
Forming the second well region in described second area substrate, the doping type of described second well region is different from the dopant ion type of described first well region；
Form the pseudo-grid structure being positioned on described isolation structure；
With dummy gate structure for mask, forming the second heavily doped region in described second well region, described second heavily doped region is identical with the dopant ion type of described second well region；
With dummy gate structure for mask, forming the first heavily doped region in described first well region, described first heavily doped region is identical with the dopant ion type of described first well region.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the feature sizes of dummy gate structure is less than the feature sizes of described isolation structure.
3. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the step forming described first heavily doped region includes: carry out N-type ion doping；The step forming described second heavily doped region includes: carry out P type ion doping；Or, the step forming described first heavily doped region includes: carry out P type ion doping；The step forming described second heavily doped region includes: carry out N-type ion doping；
The step carrying out N-type ion doping includes: the ion of doping is phosphonium ion, arsenic ion or antimony ion, and ion energy is 2Kev to 80Kev, and ion dose is 3E13 to 8E15 atom per square centimeter；
The step carrying out P type ion doping includes: the ion of doping is boron ion, and ion energy is 2Kev to 120Kev, and ion dose is 3E13 to 5E15 atom per square centimeter.
4. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the step forming the pseudo-grid structure being positioned on described isolation structure includes: form gate oxidation films at described substrate surface；
Gate electrode film is formed on described gate oxidation films surface；
Graph layer is formed on described gate electrode film surface；
With described graph layer for mask, adopt dry plasma etch technique, etching removes the part of grid pole film on described first well region and on the second well region and part gate oxidation films, retain the gate electrode film on described isolation structure and gate oxidation films, form pseudo-gate oxide and pseudo-gate electrode layer, dummy gate oxide layer and pseudo-gate electrode layer to be used for constituting pseudo-grid structure；
Remove described graph layer.
5. the forming method of semiconductor structure as claimed in claim 1, it is characterized in that, described forming method also includes: before forming described first heavily doped region, with dummy gate structure for mask, the first light doped region is formed in described first well region, described first light doped region is identical with the dopant ion type of described first heavily doped region, and the degree of depth of the described first light doped region is less than the degree of depth of described first heavily doped region；
Before forming described second heavily doped region, with dummy gate structure for mask, the second light doped region is formed in described second well region, described second light doped region is identical with the dopant ion type of described second heavily doped region, and the degree of depth of the described second light doped region is less than the degree of depth of described second heavily doped region.
6. a semiconductor structure, it is characterised in that including:
Substrate；
It is arranged in the isolation structure of described substrate, for described substrate being divided into first area and second area；
First well region, is positioned at described first area substrate；
Second well region, is positioned at described second area substrate, and the doping type of described second well region is different from the doping type of described first well region；
Pseudo-grid structure, is positioned on described isolation structure；
First heavily doped region, is positioned at the first well region of dummy gate structure side；
Second heavily doped region, is positioned at the second well region of dummy gate structure opposite side.
7. semiconductor structure as claimed in claim 6, it is characterised in that the feature sizes of dummy gate structure is less than the feature sizes of described isolation structure.
8. semiconductor structure as claimed in claim 6, it is characterised in that the dopant ion type of described first heavily doped region is n-type doping ion, and the dopant ion of described second heavily doped region is P type dopant ion；Or, the dopant ion type of described first heavily doped region is P type dopant ion, and the dopant ion of described second heavily doped region is n-type doping ion；
Described n-type doping ion is phosphonium ion, arsenic ion or antimony ion, and the concentration of dopant ion is 1E17 atoms per cubic centimeter to 5E20 atoms per cubic centimeter；Described P type dopant ion is boron ion, and the concentration of dopant ion is 5E16 atoms per cubic centimeter to 5E20 atoms per cubic centimeter.
9. semiconductor structure as claimed in claim 6, it is characterised in that dummy gate structure includes: is positioned at the pseudo-gate oxide on described isolation structure and is positioned at the pseudo-gate electrode layer on dummy gate oxide layer surface.
10. semiconductor structure as claimed in claim 6, it is characterised in that described semiconductor structure also includes the first light doped region and the second light doped region that are positioned at dummy gate structure both sides；
Described first light doped region is positioned at described first heavily doped region, and the described first light doped region is identical with the dopant ion type of described first heavily doped region, and the degree of depth of the described first light doped region is less than the degree of depth of described first heavily doped region；
Described second light doped region is positioned at described second heavily doped region, and the described second light doped region is identical with the dopant ion type of described second heavily doped region, and the degree of depth of the described second light doped region is less than the degree of depth of described second heavily doped region.
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| CN111834228A (en) * | 2020-07-30 | 2020-10-27 | 上海华虹宏力半导体制造有限公司 | Preparation method of LDMOS device |
| CN112509971A (en) * | 2019-09-13 | 2021-03-16 | 杭州士兰集昕微电子有限公司 | Method for manufacturing isolation structure |
| CN113611606A (en) * | 2021-07-28 | 2021-11-05 | 上海华虹宏力半导体制造有限公司 | Voltage stabilizing diode and manufacturing method thereof |
| WO2023130584A1 (en) * | 2022-01-10 | 2023-07-13 | 长鑫存储技术有限公司 | Capacitance measurement structure and forming method thereof |
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