CN105761747B - Static RAM bit line precharging circuit - Google Patents

Static RAM bit line precharging circuit Download PDF

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Publication number
CN105761747B
CN105761747B CN201610086783.9A CN201610086783A CN105761747B CN 105761747 B CN105761747 B CN 105761747B CN 201610086783 A CN201610086783 A CN 201610086783A CN 105761747 B CN105761747 B CN 105761747B
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bit line
precharge
voltage
enable signal
static ram
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CN105761747A (en
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杨光华
孔蔚然
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

The invention discloses a kind of Static RAM bit line precharging circuits, comprising: bit line balancing circuitry, for complementary first and two the voltage of bit line to be balanced and make the voltage of the bit line after balance be all balanced voltage；Voltage decision circuitry judges signal for being compared to balanced voltage and pre-charge threshold voltage and forming precharge according to comparison result signal and precharge enable signal；Switching circuit is connected to precharge potential source and first and two between bit line.In precharge cycle, when balanced voltage is more than or equal to pre-charge threshold voltage, the voltage of the first and second bit lines all remains the balanced voltage；When balanced voltage be less than pre-charge threshold voltage when, first and two bit line charging precharge potential source provide pre-charge pressure.The present invention can reduce bit line preliminary filling power consumption.

Description

Static RAM bit line precharging circuit
Technical field
The present invention relates to a kind of semiconductor integrated circuit, are pre-charged more particularly to a kind of Static RAM bit line Road.
Background technique
As shown in Figure 1, being the circuit diagram of the existing Static RAM with bit line precharging circuit；Static random storage The storage unit (cell) 1 of device is arranged in array structure, and the word line end of each storage unit 1 connects corresponding wordline WLx, even It is connected to collinear storage unit 1 to be in line, the x in wordline WLx indicates any a line；The first row wordline be WL0, i.e., this Locating x is 0.Since the storage unit 1 of Static RAM can store the signal of the reverse phase each other latched mutually simultaneously, therefore store Unit 1 includes two complementary bit line ends, and two complementary bit line ends of storage unit 1 are connected respectively to the first of logical complement Y in bit line BLy and the second bit line BL_y, the first bit line BLy and the second bit line BL_y indicates any one column；The first of first row Bit line is BL0 and the second bit line is BL_0, i.e., y herein is 0.Input signal Din passes through a buffer 2 and a switch CSy It is connected to the first bit line Bly, the input signal Din_ of reverse phase is connected to second by a buffer 2 and a switch CSy The control terminal for the buffer 2 that line BL_y is connected with input signal all connects write enable signal WENB, and switch CS0 is indicated and first The connected switch of the bit line of column.The the first bit line Bly respectively arranged passes through a switch CSy respectively and is connected to bit line sense amplifier (SA) 3 input terminal, the second bit line BL_y respectively arranged pass through a switch CSy respectively and are connected to bit line sense amplifier (SA) 3 another input terminal, when signal is read, the first bit line BLy's and the second bit line BL_y of the storage unit 1 selected Signal by bit line sense amplifier 3 amplify after by the way that output signal Dout is exported after a buffer.
A bit line precharging circuit 101 is all connected between the first bit line BLy and the second bit line BL_y of each column.Fig. 1 Shown in existing bit line precharging circuit 101 be made of PMOS tube PM101, PM102 and PM103, the source-drain electrode of PMOS tube PM103 Be connected between the first bit line BLy and the second bit line BL_y, the source electrode of PMOS tube PM101 and PM102 all connect it is described it is static with The working power voltage VCC of machine memory, the grid of PMOS tube PM101, PM102 and PM103 link together and all connect pre- Charge enable signal Precharge_enb.
As shown in Fig. 2, being the signal waveforms of existing Static RAM shown in FIG. 1；Including write cycle time (Write Cycle), precharge cycle (pre-charge cycle) and read cycle (Read cycle):
It is shown so that the storage unit 1 to the first row first row carries out one writing as an example in write cycle time, it can be seen that write In period, the first bit line is that BL0 remains working power voltage VCC, and the second bit line is that BL_0 is pulled down to ground GND；Write cycle time After enter precharge cycle.
It is enabled for low level that enable signal Precharge_enb is pre-charged in precharge cycle, the first bit line of all column BLy and the second bit line BL_y are charged to working power voltage VCC；The second bit line for being wherein pulled down to ground GND is BL_0 Charging amplitude it is larger, i.e., from ground GND to working power voltage VCC.
In read cycle, there is a bit line single by storage in the first bit line BLy and the second bit line BL_y of the column being read The information that member 1 is stored drags down, if the information that storage unit 1 stores is " 1 ", the second bit line BL_y can be pulled low certain Value, the voltage difference that the first bit line Bly remains working power voltage VCC, the first bit line BLy and the second bit line BL_y pass through bit line Sense amplifier 3 exports after amplifying；If the information that storage unit 1 stores is " 0 ", the first bit line Bly can be pulled low centainly Value, the voltage difference that the second bit line BL_y remains working power voltage VCC, the first bit line BLy and the second bit line BL_y passes through Bit line sense amplifier 3 exports after amplifying；Read cycle can enter precharge cycle after terminating again.
From the foregoing, it will be observed that in available circuit, after each read-write operation, require the first bit line BLy at the both ends Cell and Second bit line BL_y_ is charged to working power voltage VCC in advance.After write operation, one end bit line in Cell such as second in Fig. 2 Bit line is that BL_0 needs to be charged to working power voltage VCC in advance from ground GND, and in the case that bit-line load is big, preliminary filling power consumption is big.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of Static RAM bit line precharging circuits, can reduce position Line preliminary filling power consumption.
In order to solve the above technical problems, Static RAM bit line precharging circuit provided by the invention be connected to it is static with Between the first bit line and the second bit line of the logical complement of the storage unit of machine memory, the bit line precharging circuit is being pre-charged Enable signal works when enabled, and the precharge enable signal enables after the completion of read-write operation, do not make during read-write operation Can, the bit line precharging circuit includes:
Bit line balancing circuitry, control terminal connection position line balance enable signal, for first bit line and described the The voltage of two bit lines is balanced and the voltage of first bit line and second bit line after balance is made all to be balanced voltage.
Voltage decision circuitry, for being compared and the balanced voltage and pre-charge threshold voltage according to comparison result Signal and the precharge enable signal form precharge and judge signal.
Switching circuit, the control terminal connection precharge judge that signal, the switching circuit are connected to precharge potential source Between first bit line and second bit line.
When the precharge enable signal is enabled: when the balanced voltage is more than or equal to the pre-charge threshold voltage When, the switching circuit makes first bit line and the connection for being pre-charged potential source and second bit line and the preliminary filling The connection of voltage source all disconnects, so that the voltage of first bit line and second bit line be made all to remain the balance electricity Pressure；When the balanced voltage is less than the pre-charge threshold voltage, the switching circuit makes first bit line and described pre- The connection of the connection of charging potential source and second bit line and the precharge potential source is all connected, to make first bit line The pre-charge pressure that the precharge potential source provides is charged to the voltage of second bit line；
When the precharge enable signal is not enabled, the switching circuit makes first bit line and the pre-charge pressure The connection of the connection in source and second bit line and the precharge potential source all disconnects.
A further improvement is that the bit line balancing circuitry includes the first MOS transistor, first MOS transistor Grid connection position line balance enable signal, the source electrode and drain electrode of first MOS transistor are connected to first bit line and institute It states between the second bit line, the switch that first MOS transistor is connected as first bit line with second bit line passes through The bit line balance enable signal controls the conducting and disconnection of first MOS transistor.
A further improvement is that first MOS transistor is made of PMOS tube；The bit line balance enable signal is low The conducting of first MOS transistor described in when level, when bit line balance enable signal is high level described in the first MOS transistor it is disconnected It opens.
A further improvement is that enable when the precharge enable signal is high level, do not enabled in low level, it is described Bit line balances the inversion signal that enable signal is the precharge enable signal.
A further improvement is that the voltage decision circuitry includes comparator, the normal phase input end connection of the comparator The pre-charge threshold voltage, inverting input terminal connect the balanced voltage.
A further improvement is that the inverting input terminal of the comparator is by connecting first bit line or the second Line connects the balanced voltage.
A further improvement is that the voltage decision circuitry further includes dual input NAND gate, the output end of the comparator It is connected to the first input end of the dual input NAND gate, the precharge enable signal is connected to the dual input NAND gate Second input terminal is enabled when the precharge enable signal is high level, is not enabled in low level；The dual input NAND gate Output end output it is described precharge judge signal.
A further improvement is that the switching circuit includes the second PMOS tube and third PMOS tube, second PMOS tube Grid and the third PMOS tube grid all connect it is described precharge judge signal, the source electrode of second PMOS tube and institute The source electrode for stating third PMOS tube all connects the precharge potential source, and the drain electrode of second PMOS tube connects first bit line, The drain electrode of the third PMOS tube connects second bit line.
A further improvement is that the switching circuit includes the second NMOS tube and third NMOS tube, second NMOS tube Grid and the grid of the third NMOS tube all connect described be pre-charged and judge the inversion signal of signal, second NMOS tube Drain electrode and the drain electrode of the third NMOS tube all connect the precharge potential source, described in the source electrode connection of second NMOS tube The source electrode of first bit line, the third NMOS tube connects second bit line.
A further improvement is that first MOS transistor is made of NMOS tube；The bit line balance enable signal is low First MOS transistor described in when level disconnects, when bit line balance enable signal is high level described in the first MOS transistor lead It is logical.
A further improvement is that enable when the precharge enable signal is high level, do not enabled in low level, it is described Bit line balances enable signal and uses the precharge enable signal.
A further improvement is that the pre-charge threshold voltage is more than or equal to the precharge that the precharge potential source provides Pressure, the pre-charge threshold voltage are less than the working power voltage of the Static RAM.
A further improvement is that the pre-charge pressure that the precharge potential source provides is less than or equal to the Static RAM Working power voltage half.
A further improvement is that the storage unit of the Static RAM includes multiple and each storage unit row Array structure is arranged into, the first output end of each storage unit of same row connects first bit line, second output terminal connects It connects between second bit line, the signal of the first output end and the second output terminal output of each storage unit is reverse phase each other Complementary signal.
Bit line precharging circuit of the present invention is provided with bit line balancing circuitry and voltage decision circuitry, passes through bit line balancing circuitry pair After complementary bit line carries out the balance of voltage, then voltage decision circuitry is used to determine the need for being pre-charged bit line, needed When charging switching circuit opening make bit line be connected to precharge potential source be pre-charged；The wherein precharge in voltage decision circuitry Threshold voltage and precharge potential source are the values different from working power voltage, compared to the prior art, the present invention do not need by Bit line is charged to the value of working power voltage in advance, but is charged to the voltage for the precharge potential source being separately provided in advance, and works as bit line If balanced voltage is more than or equal to pre-charge threshold voltage after balance, no longer need to carry out bit line additional precharge, I.e. the present invention, which is able to achieve, can be achieved with required pre-charge level by the balance between bit line, does not need additionally to be pre-charged, institute Bit line preliminary filling power consumption can be substantially reduced with the present invention.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the circuit diagram of the existing Static RAM with bit line precharging circuit；
Fig. 2 is the signal waveforms of existing Static RAM shown in FIG. 1；
Fig. 3 is the circuit diagram of Static RAM of the embodiment of the present invention with bit line precharging circuit；
Fig. 4 is the circuit diagram of the bit line precharging circuit in Fig. 3；
Fig. 5 is the circuit diagram of the bit line precharging circuit of present pre-ferred embodiments；
Fig. 6 is the signal waveforms using the Static RAM of present pre-ferred embodiments bit line precharging circuit.
Specific embodiment
As shown in figure 3, being the circuit diagram of Static RAM of the embodiment of the present invention with bit line precharging circuit；It is static The storage unit 1 of random access memory is arranged in array structure, and the word line end of each storage unit 1 connects corresponding wordline WLx, It is connected to collinear storage unit 1 to be in line, the x in wordline WLx indicates any a line；The first row wordline is WL0, i.e., X is 0 herein.Since the storage unit 1 of Static RAM can store the signal of the reverse phase each other latched mutually simultaneously, therefore deposit Storage unit 1 includes two complementary bit line ends, and two complementary bit line ends of storage unit 1 are connected respectively to the of logical complement Y in one bit line BLy and the second bit line BL_y, the first bit line BLy and the second bit line BL_y indicates any one column；The of first row One bit line is BL0 and the second bit line is BL_0, i.e., y herein is 0.Input signal Din passes through a buffer 2 and a switch CSy is connected to the first bit line Bly, and the input signal Din_ of reverse phase is connected to second by a buffer 2 and a switch CSy The control terminal for the buffer 2 that bit line BL_y is connected with input signal all connects write enable signal WENB, and switch CS0 is indicated and the The connected switch of the bit line of one column.The the first bit line Bly respectively arranged passes through a switch CSy respectively and is connected to bit line sense amplifier 3 input terminal, the second bit line BL_y respectively arranged pass through a switch CSy respectively and are connected to bit line sense amplifier (SA) 3 Another input terminal, signal read when, the signal of the first bit line BLy and the second bit line BL_y of the storage unit 1 selected By exporting output signal Dout after a buffer after being amplified by bit line sense amplifier 3.
Above structure is that the circuit structure of of Static RAM itself is identical with available circuit structure shown in FIG. 1.
Above structure is that the circuit structure of of Static RAM itself is identical with available circuit structure shown in FIG. 1. Static RAM bit line of embodiment of the present invention precharging circuit 201 is connected to the logic of the storage unit of Static RAM Between complementary the first bit line BLy and the second bit line BL_y, i.e., between the first bit line BLy and the second bit line BL_y of each column all It is connected with a bit line precharging circuit 201.As shown in figure 4, being the circuit diagram of the bit line precharging circuit 201 in Fig. 3；
The bit line precharging circuit 201 works when being pre-charged enable signal Precharge_en and enabling, the precharge Enable signal Precharge_en is enabled after the completion of read-write operation, is not enabled during read-write operation, the bit line precharge Road 201 includes:
Bit line balancing circuitry 202, control terminal connection position line balance enable signal BALENB, for the first bit line BLy With the voltage of the second bit line BL_y be balanced and make balance after the voltage of the first bit line BLy and the second bit line BL_y be all Balanced voltage.
Voltage decision circuitry 203, for being compared to the balanced voltage and pre-charge threshold voltage VCC_pcg_com And precharge judgement letter is formed according to the comparison result signal Comp_out and precharge enable signal Precharge_en Number Pcg_out.
Switching circuit 204, the control terminal connection precharge judge that signal Pcg_out, the switching circuit 204 are connected Between precharge potential source VCC_pcg and the first bit line BLy and the second bit line BL_y.
When the precharge enable signal Precharge_en is enabled: when the balanced voltage is more than or equal to the preliminary filling When electric threshold voltage VCC_pcg_com, the switching circuit 204 makes the first bit line BLy and the precharge potential source VCC_ The connection of the connection of pcg and the second bit line BL_y and the precharge potential source VCC_pcg all disconnect, to make described the The voltage of one bit line BLy and the second bit line BL_y all remain the balanced voltage；When the balanced voltage is less than the preliminary filling When electric threshold voltage VCC_pcg_com, the switching circuit 204 makes the first bit line BLy and the precharge potential source VCC_ The connection of the connection of pcg and the second bit line BL_y and the precharge potential source VCC_pcg are all connected, to make described the The voltage of one bit line BLy and the second bit line BL_y are charged to the pre-charge pressure that the precharge potential source VCC_pcg is provided.
When the precharge enable signal Precharge_en is not enabled, the switching circuit 204 makes described first The connection of line BLy and the precharge potential source VCC_pcg and the second bit line BL_y and precharge potential source VCC_pcg Connection all disconnect.
As shown in figure 5, being the circuit diagram of the bit line precharging circuit of present pre-ferred embodiments；In present pre-ferred embodiments Bit line precharging circuit 201a in:
The bit line balancing circuitry 202a includes that the grid of the first MOS transistor M1, the first MOS transistor M1 connects Bit line balances enable signal BALENB, and the source electrode and drain electrode of the first MOS transistor M1 is connected to first bit line and institute It states between the second bit line, the switch that the first MOS transistor M1 is connected as first bit line with second bit line, leads to Cross conducting and disconnection that the bit line balance enable signal BALENB controls the first MOS transistor M1.
In present pre-ferred embodiments, the first MOS transistor M1 is made of PMOS tube；The enabled letter of bit line balance The conducting of first MOS transistor M1 described in when number BALENB is low level, the bit line balance enable signal BALENB is high level Shi Suoshu the first MOS transistor M1 is disconnected.It is enabled when the precharge enable signal Precharge_en is high level, in low electricity It does not enable usually, the reverse phase letter that the bit line balance enable signal BALENB is the precharge enable signal Precharge_en Number.Again in other preferred embodiments, also can are as follows: the first MOS transistor M1 is made of NMOS tube；The bit line balance is enabled First MOS transistor M1 described in when signal BALENB is low level is disconnected, and the bit line balance enable signal BALENB is high electricity Usually the first MOS transistor M1 conducting；The bit line balance enable signal BALENB uses the precharge enable signal Precharge_en。
In a preferred embodiment of the present invention, the voltage decision circuitry 203 includes comparator 205, the comparator 205 Normal phase input end connects the pre-charge threshold voltage VCC_pcg_com, inverting input terminal connects the balanced voltage；The ratio The balanced voltage is connected by connecting first bit line or second bit line compared with the inverting input terminal of device 205.It is described The output end of comparator 205 exports comparison result signal Comp_out.
The voltage decision circuitry 203 further includes dual input NAND gate 206, and the output end of the comparator 205 is connected to The first input end of the dual input NAND gate 206, the precharge enable signal Precharge_en are connected to the lose-lose Enter the second input terminal of NAND gate 206；The output end output precharge of the dual input NAND gate 206 judges signal Pcg_ out。
The switching circuit 204 includes the second PMOS tube M2 and third PMOS tube M3, the grid of the second PMOS tube M2 The precharge, which is all connected, with the grid of the third PMOS tube M3 judges signal Pcg_out, the source of the second PMOS tube M2 The source electrode of pole and the third PMOS tube M3 all connect the precharge potential source VCC_pcg, the drain electrode of the second PMOS tube M2 The first bit line BLy is connected, the drain electrode of the third PMOS tube M3 connects the second bit line BL_y.In other preferable implementations In example, the second PMOS tube M2 and third PMOS tube M3 can also be replaced with NMOS tube respectively, specifically: the switching circuit 204 Including the second NMOS tube and third NMOS tube, the grid of the grid of second NMOS tube and the third NMOS tube all connects institute State the inversion signal that precharge judges signal Pcg_out, the drain electrode of second NMOS tube and the drain electrode of the third NMOS tube The precharge potential source VCC_pcg is all connected, the source electrode of second NMOS tube connects the first bit line BLy, the third The source electrode of NMOS tube connects the second bit line BL_y.
In present pre-ferred embodiments, the pre-charge threshold voltage VCC_pcg_com is more than or equal to the pre-charge pressure The pre-charge pressure that source VCC_pcg is provided, the pre-charge threshold voltage VCC_pcg_com are less than the Static RAM Working power voltage；More preferably be selected as, the pre-charge pressure that the precharge potential source VCC_pcg is provided be less than or equal to it is described it is static with The half of the working power voltage of machine memory.
As shown in fig. 6, being the signal wave using the Static RAM of present pre-ferred embodiments bit line precharging circuit Shape figure；Including write cycle time, precharge cycle and read cycle:
Write cycle time: it is shown so that the storage unit 1 to the first row first row carries out one writing as an example, it can be seen that write In period, the first bit line is that the voltage that BL0 is formed from the precharge cycle before write operation rises to working power voltage VCC, Second bit line is the voltage pull-down that is formed from the precharge cycle before write operation of BL_0 to ground GND；Enter after write cycle time Precharge cycle.At this, it also can be big in other situations that the voltage formed in the precharge cycle before write operation, which is VCC_pcg, In the balanced voltage for being equal to VCC_pcg_comp.
Precharge cycle: being illustrated by taking the storage unit 1 of the first row first row as an example, is pre-charged enable signal Precharge_enb is enabled for high level, and the first bit line BL0 and the second bit line BL_0 mutually balance each other, in the write cycle time that Fig. 6 is shown In precharge cycle later, the balanced voltage after balance is greater than pre-charge threshold voltage VCC_pcg_comp, so when open Powered-down road 204a does not have to open not having to carry out additional precharge, namely only with the first bit line BL0 and the second bit line BL_ Mutually balancing each other between 0 can obtain enough pre-charge voltages.
Read cycle: being illustrated by taking the storage unit 1 of the first row first row as an example, the first bit line BL0 being read and The information that two bit line BL_0 are stored according to storage unit 1 is promoted or is dragged down accordingly, if the letter that storage unit 1 stores When breath is " 1 ", the second bit line BL_0 can be pulled low certain value, and the first bit line Bl0 can promote certain value, is i.e. show in Fig. 6 The voltage difference of the situation shown, the first bit line BL0 and the second bit line BL_0 export after being amplified by bit line sense amplifier 3；If When the information that storage unit 1 stores is " 0 ", then the first bit line Bl0 can be pulled low certain value, and the second bit line BL_0 can promote one The voltage difference of fixed value, the first bit line BL0 and the second bit line BL_0 export after being amplified by bit line sense amplifier 3.
Compare shown in Fig. 2 and Fig. 6 it is found that present pre-ferred embodiments do not need to carry out additionally after write cycle time Precharge, and then occur being charged to working power voltage VCC in advance from ground GND in available circuit shown in Fig. 2, so the present invention is preferable Embodiment can substantially reduce precharging power dissipation.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered It is considered as protection scope of the present invention.

Claims (14)

1. a kind of Static RAM bit line precharging circuit, which is characterized in that bit line precharging circuit is connected to static random and deposits Between the first bit line and the second bit line of the logical complement of the storage unit of reservoir, the bit line precharging circuit is enabled in precharge Signal works when enabled, and the precharge enable signal is enabled after the completion of read-write operation, do not enabled during read-write operation, institute Rheme line precharging circuit includes:
Bit line balancing circuitry, control terminal connection position line balance enable signal, for first bit line and the second The voltage of line is balanced and the voltage of first bit line and second bit line after balance is made all to be balanced voltage；
Voltage decision circuitry, for being compared to the balanced voltage and pre-charge threshold voltage and according to comparison result signal And the precharge enable signal forms precharge and judges signal；
Switching circuit, the control terminal connection precharge judge that signal, the switching circuit are connected to precharge potential source and institute It states between the first bit line and second bit line；
When the precharge enable signal is enabled: when the balanced voltage is more than or equal to the pre-charge threshold voltage, institute Stating switching circuit makes first bit line and the connection for being pre-charged potential source and second bit line and the pre-charge pressure The connection in source all disconnects, so that first bit line and the voltage of second bit line be made all to remain the balanced voltage；When When the balanced voltage is less than the pre-charge threshold voltage, the switching circuit makes first bit line and the pre-charge pressure The connection of the connection in source and second bit line and the precharge potential source is all connected, to make first bit line and described The voltage of second bit line is charged to the pre-charge pressure that the precharge potential source provides；
When the precharge enable signal is not enabled, the switching circuit makes first bit line and the precharge potential source The connection of connection and second bit line and the precharge potential source all disconnects.
2. Static RAM bit line precharging circuit as described in claim 1, it is characterised in that: the bit line balancing circuitry Including the first MOS transistor, the grid connection position line balance enable signal of first MOS transistor, the first MOS crystal The source electrode and drain electrode of pipe is connected between first bit line and second bit line, described in the first MOS transistor conduct The switch that first bit line is connected with second bit line balances enable signal by the bit line and controls the first MOS crystal The conducting and disconnection of pipe.
3. Static RAM bit line precharging circuit as claimed in claim 2, it is characterised in that: the first MOS crystal Pipe is made of PMOS tube；First MOS transistor conducting described in when the bit line balance enable signal is low level, the bit line are flat First MOS transistor described in when the enable signal that weighs is high level disconnects.
4. Static RAM bit line precharging circuit as claimed in claim 3, it is characterised in that: the enabled letter of precharge It is enabled when number being high level, do not enable in low level, the bit line balance enable signal is the precharge enable signal Inversion signal.
5. Static RAM bit line precharging circuit as described in claim 1, it is characterised in that: the voltage decision circuitry Including comparator, the normal phase input end of the comparator connects the pre-charge threshold voltage, inverting input terminal connects described put down Weigh voltage.
6. Static RAM bit line precharging circuit as claimed in claim 5, it is characterised in that: the reverse phase of the comparator Input terminal connects the balanced voltage by connecting first bit line or second bit line.
7. Static RAM bit line precharging circuit as claimed in claim 5, it is characterised in that: the voltage decision circuitry It further include dual input NAND gate, the output end of the comparator is connected to the first input end of the dual input NAND gate, described Precharge enable signal is connected to the second input terminal of the dual input NAND gate, when the precharge enable signal is high level It enables, enabled in low level；The output end output precharge of the dual input NAND gate judges signal.
8. Static RAM bit line precharging circuit as claimed in claim 7, it is characterised in that: the switching circuit includes The grid of second PMOS tube and third PMOS tube, the grid of second PMOS tube and the third PMOS tube all connects described pre- It charging and judges signal, the source electrode of the source electrode of second PMOS tube and the third PMOS tube all connects the precharge potential source, The drain electrode of second PMOS tube connects first bit line, and the drain electrode of the third PMOS tube connects second bit line.
9. Static RAM bit line precharging circuit as claimed in claim 7, it is characterised in that: the switching circuit includes The grid of second NMOS tube and third NMOS tube, the grid of second NMOS tube and the third NMOS tube all connects described pre- Charging judges the inversion signal of signal, and the drain electrode of second NMOS tube and the drain electrode of the third NMOS tube all connect described pre- Charge potential source, and the source electrode of second NMOS tube connects first bit line, the source electrode connection of the third NMOS tube described the Two bit lines.
10. Static RAM bit line precharging circuit as described in claim 2, it is characterised in that: the first MOS is brilliant Body pipe is made of NMOS tube；First MOS transistor described in when the bit line balance enable signal is low level disconnects, the bit line First MOS transistor conducting described in balancing when enable signal is high level.
11. Static RAM bit line precharging circuit as claimed in claim 10, it is characterised in that: the precharge is enabled It enables when signal is high level, enabled in low level, the bit line balance enable signal is believed using the precharge is enabled Number.
12. the Static RAM bit line precharging circuit as described in any claim in claim 1 to 11, feature exist In: the pre-charge threshold voltage is more than or equal to the pre-charge pressure that the precharge potential source provides, the pre-charge threshold voltage Less than the working power voltage of the Static RAM.
13. Static RAM bit line precharging circuit as claimed in claim 12, it is characterised in that: the precharge potential source The pre-charge pressure of offer is less than or equal to the half of the working power voltage of the Static RAM.
14. Static RAM bit line precharging circuit as described in claim 1, it is characterised in that: the static random is deposited The storage unit of reservoir includes that multiple and each storage unit is arranged in array structure, each storage unit of same row First output end connects first bit line, second output terminal connects between second bit line, and the of each storage unit One output end and the signal of second output terminal output are the complementary signal of reverse phase each other.
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CN112102863B (en) * 2020-09-07 2023-04-25 海光信息技术股份有限公司 Static random access memory control circuit, method, memory and processor
CN112259144B (en) * 2020-10-29 2021-04-30 海光信息技术股份有限公司 Static random access memory circuit, memory and electronic equipment
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