CN105761694B - Level translator for array substrate gate driving circuit - Google Patents
Level translator for array substrate gate driving circuit Download PDFInfo
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- CN105761694B CN105761694B CN201610311807.6A CN201610311807A CN105761694B CN 105761694 B CN105761694 B CN 105761694B CN 201610311807 A CN201610311807 A CN 201610311807A CN 105761694 B CN105761694 B CN 105761694B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The present invention provides a kind of level translator for array substrate gate driving circuit, comprising: first input end, the second input terminal, third input terminal, the 4th input, output end, first resistor device and second resistor；The first input end receives logic control signal；Second input terminal receives reference voltage；One end of the first resistor device receives first voltage, and the third input terminal is connected to the other end of first resistor device to receive voltage from first resistor device；One end of the second resistor receives second voltage, and the 4th input terminal is connected to the other end of second resistor to receive voltage from second resistor；The output end alternately exports the received voltage of third input terminal and the 4th received voltage of input terminal according to logic control signal and reference voltage.The slope that the level translator is changed by increasing the output voltage of variable resistance control output end, reduces the ripple of level translator output electric current, while reducing the effect of electromagnetic interference.
Description
Technical field
All things considered of the present invention is related to technical field of liquid crystal display, more particularly, is related to a kind of for array substrate grid
The level translator of pole driving circuit.
Background technique
Array substrate gate driving (Gate Driver On Array, GOA) technology, is a kind of by thin film transistor (TFT)
The gated sweep driving circuit of (Thin Film Transistor, TFT) is produced in array substrate, to substitute external silicon chip
A kind of technology of the driving chip of production.The grid voltage of every a line TFT in liquid crystal display can be mentioned by GOA circuit
For generally generating clock control signal using level translator (Level Shifter) and controlling every a line TFT in GOA circuit
It opens or closes.
The existing level shifting circuit for GOA framework liquid crystal display generally includes: one is set to circuit drives plate
Sequence controller, the sequence controller for generate and sending logic control signal (Logic Control)；One is set to electricity
Level translator in the driving plate of road, the level translator are used to convert the logic control signal sent by sequence controller
Level.Control signal after level conversion is input to gate driving circuit, to drive the TFT in liquid crystal display to carry out work
Make.
Currently, several voltages for using of GOA circuit are during height changes, the difference of maximum voltage and minimum voltage
It is even more big to have 35V, then, level translator is during voltage change, it is easy to cause the variation of voltage too fast, electricity
The ripple of the output electric current of flat turn parallel operation is excessive, causes output electromagnetic interference (EMI) effect worse.
Summary of the invention
The purpose of the present invention is to provide a kind of level translators for array substrate gate driving circuit, pass through increase
Variable resistance controls the slope of level translator output voltage variation, effectively reduces the ripple of level translator output electric current,
The effect of electromagnetic interference is reduced simultaneously.
For achieving the above object, the present invention provides a kind of level conversion for array substrate gate driving circuit
Device, comprising: first input end, the second input terminal, third input terminal, the 4th input terminal and output end, further includes: first resistor device
And second resistor；The first input end receives logic control signal；Second input terminal receives reference voltage；Described
One end of one resistor receives first voltage, and the third input terminal is connected to the other end of the first resistor device with from described
First resistor device receives voltage；One end of the second resistor receives second voltage, and the 4th input terminal is connected to described
The other end of second resistor is to receive voltage from the second resistor；The output end according to the logic control signal and
The reference voltage alternately exports the received voltage of the third input terminal and the received voltage of the 4th input terminal.
If the voltage value of the logic control signal is greater than the voltage value of the reference voltage, the output end output
The received voltage of third input terminal；If the voltage value of the logic control signal is less than the voltage of the reference voltage
Value, then the output end exports the received voltage of the 4th input terminal.
The first resistor device is the first variable resistance, and the second resistor is the second adjustable resistance device.
First variable resistance based on the received the first control parameter and change resistance value, the second adjustable resistance device
Based on the received the second control parameter and change resistance value.
First variable resistance includes multiple resistors and for selecting the first of one of the multiple resistor to select
Select switch.
The first choice switch is according to one of the multiple resistor of the first selection of control parameter, so that the third is defeated
Enter to hold to be connected to the first choice and switchs the resistor of selection to switch the resistor of selection from the first choice and receive electricity
Pressure.
The second adjustable resistance device includes multiple resistors and for selecting the second of one of the multiple resistor to select
Select switch.
The second selection switch is according to one of the multiple resistor of the second selection of control parameter, so that the described 4th is defeated
Enter to hold to be connected to second selection and switchs the resistor of selection to switch the resistor reception electricity of selection from second selection
Pressure.
The logic control signal is periodic logic level.
The output end exports the week of the third input terminal received voltage and the received voltage of the 4th input terminal
Phase is identical as the period of the logic control signal.
The present invention provides a kind of level translator for array substrate gate driving circuit, is received according to first input end
Logic control signal and the received reference voltage of the second input terminal, the period alternately exports third input terminal via first resistor
The received voltage of device and the 4th input terminal are via the received voltage of second resistor.The level translator can power transformation by increasing
The slope for hindering the output voltage variation of device control output end, effectively reduces the ripple of level translator output electric current, reduces simultaneously
The effect of electromagnetic interference.
Detailed description of the invention
Fig. 1 shows the circuit signal of the level translator for array substrate gate driving circuit of the embodiment of the present invention
Figure.
Fig. 2 shows one specific examples of circuit of the level translator of Fig. 1.
Specific embodiment
The electricity for array substrate gate driving circuit of embodiment according to the present invention is described referring to Fig. 1 to Fig. 2
Flat turn parallel operation.
The circuit that Fig. 1 shows the level translator according to an embodiment of the present invention for array substrate gate driving circuit shows
It is intended to.Referring to Fig.1, a kind of level translator for array substrate gate driving circuit is proposed in the embodiment of the present invention, is wrapped
It includes: first input end 10, the second input terminal 20, third input terminal 30, the 4th input terminal 40 and output end 50, further includes: first
Resistor R10With second resistor R20；First input end 10 receives logic control signal Vin；Second input terminal 20 is received with reference to electricity
Press Vref；The first resistor device R10One end receive first voltage VGH, it is electric that the third input terminal 30 is connected to described first
Hinder device R10The other end with from the first resistor device R10Receive voltage；The second resistor R20One end receive second electricity
Press VGL, the 4th input terminal 40 is connected to the second resistor R20The other end with from the second resistor R20It receives
Voltage；The output end 50 is according to the logic control signal VinWith the reference voltage VrefIt is defeated alternately to export the third
Enter 30 received voltages of end and the received voltage of the 4th input terminal 40.
In the present embodiment, logic control signal VinThe periodic logic level that can be generated for sequence controller.Tool
Body is got on very well, as logic control signal VinWhen for high level signal, i.e., the voltage value of the described high level signal is greater than reference voltage Vref
Voltage value, then output end 50 export the received voltage of third input terminal 30, further, the voltage is as gate high-voltage
(Voltage Gate High) is input to gate driving circuit, to drive the TFT in liquid crystal display to open；Work as logic control
Signal VinWhen for low level signal, i.e., the voltage value of the described low level signal is less than reference voltage VrefVoltage value, then output end
The 50 output received voltages of the 4th input terminal 40, further, the voltage is as grid low-voltage (Voltage Gate Low)
It is input to gate driving circuit, to drive the TFT in liquid crystal display to close.
In addition, output end 50 exports the period of the received voltage of third input terminal 30 and the received voltage of the 4th input terminal 40
With logic control signal VinPeriod it is identical.
Preferably, first input end 10 is the non-inverting input terminal of level translator, and the second input terminal 20 is level translator
Inverting input terminal.
In the present embodiment, first voltage VGHWith second voltage VGLIt can be generated by power management chip, first voltage
VGHGreater than second voltage VGL。
As an example, first resistor device R10For the first variable resistance R100, second resistor R20For the second adjustable resistance
Device R200.The first variable resistance R100Based on the received the first control parameter and change resistance value, the second adjustable resistance
Device R200Based on the received the second control parameter and change resistance value.
Fig. 2 shows one specific examples of circuit of the level translator of Fig. 1.
Referring to Fig. 2, in one embodiment, the first variable resistance R100Including multiple resistor (R1, R2…Rn, n is big
In 2 integer) and first choice switch K for selecting one of the multiple resistor1.Preferably, the multiple resistor
(R1, R2…Rn) be different resistance values fixed resister.Wherein, first choice switch K1It can be according to the first selection of control parameter
One of multiple resistors, it is preferable that first control parameter can be preset in a register.It particularly, first can power transformation
Hinder device R100In one end of each resistor be connected to third input terminal 30, the first variable resistance R100In each resistor
The other end be free end, can be by first choice switch K1According to the free end of a certain resistor of the first selection of control parameter, from
And third input terminal 30 is connected to first choice switch K1The resistor of selection is with from first choice switch K1The resistor of selection connects
Receive voltage.
In one embodiment, the second adjustable resistance device R200Including multiple resistor (R1', R2’…Rn', n is greater than 2
Integer) and for selecting the second of one of the multiple resistor to select switch K2.Preferably, the multiple resistor (R1',
R2’…Rn') be different resistance values fixed resister.Wherein, the second selection switch K2It can be more according to the second selection of control parameter
One of a resistor, it is preferable that second control parameter can be preset in another register.It particularly, second can power transformation
Hinder device R200In one end of each resistor be connected to the 4th input terminal 40, the second adjustable resistance device R200In each resistor
The other end be free end, can by second selection switch K2According to the free end of a certain resistor of the second selection of control parameter, from
And the 4th input terminal 40 is connected to the second selection switch K2The resistor of selection is to select switch K from second2The resistor of selection connects
Receive voltage.
The course of work of level translator provided in this embodiment for array substrate gate driving circuit are as follows:
According to the received logic control signal V of first input end 10 of level translatorinCyclically-varying and second defeated
Enter 20 received reference voltage V of endref, make the output V of level translator output end 50outCorresponding cyclically-varying, and pass through
First resistor device R10With second resistor R20It can control the output V of output end 50outVoltage rise/fall slope.Its
In, as logic control signal VinVoltage value be greater than reference voltage VrefWhen, level translator output end 50 exports third input terminal
30 received voltages；As logic control signal VinVoltage value be less than reference voltage VrefWhen, level translator output end 50 exports
The received voltage of 4th input terminal 40.
Particularly, as logic control signal VinWhen becoming high level from low level, level translator output end 50 it is defeated
V outoutThe received voltage of third input terminal 30 is correspondingly become from the received voltage of the 4th input terminal 40, the level translator is defeated
The output V of outlet 50outDuring variation, the output electric current of level translator increases, first resistor device R10Metering function
The increase of output electric current is hindered, and then hinders the output V of output end 50outThird is become from the received voltage of the 4th input terminal 40
The received voltage of input terminal 30, first resistor device R10Resistance value size and the received voltage of the 4th input terminal 40 become third input
It holds the time of 30 received voltages directly proportional, therefore, passes through first resistor device R10It can control the output V of output end 50outElectricity
The slope risen is pressed, output current ripple caused by effectively avoiding the voltage rising of the output of output end too fast is excessive and electromagnetism is dry
The problem of disturbing；With the received logic control signal V of first input end 10inIt is continuously high level, the level translator of increase
It exports electric current to fall after rise close to zero, therefore, flows through first resistor device R10Electric current close to zero, therefore first voltage VGHVia
One resistor R10The pressure drop of generation can be neglected, then the received voltage of third input terminal 30 reaches first voltage close to zero
VGH, i.e. the output V of level translator output end 50outReach first voltage VGHAnd stablize output.
Similarly, as logic control signal VinWhen becoming low level from high level, the output V of level translator output end 50out
The received voltage of 4th input terminal 40, the output of the level translator output end 50 are become from the received voltage of third input terminal 30
VoutDuring variation, the output electric current of level translator reduces, second resistor R20Metering function hinder output electric current
Reduction, and then hinder output end 50 output VoutBecome the 4th input terminal 40 from the received voltage of third input terminal 30 to receive
Voltage, second resistor R20Resistance value size and the received voltage of third input terminal 30 become the received electricity of the 4th input terminal 40
The time of pressure is directly proportional, therefore, passes through second resistor R20It can control the output V of output end 50outVoltage decline it is oblique
Rate avoids the problem that output current ripple is excessive and electromagnetic interference caused by the control signal voltage decline of output is too fast；With
The received logic control signal V of first input end 10inIt is continuously low level, the output electric current rise of reduced level translator connects
It is bordering on zero, therefore, flows through second resistor R20Electric current close to zero, therefore second voltage VGLVia second resistor R20It generates
Pressure drop close to zero, can be neglected, then the received voltage of the 4th input terminal 40 reaches second voltage VGL, i.e. level translator
The output V of output end 50outReach second voltage VGLAnd stablize output.
Using the above-mentioned level translator according to an embodiment of the present invention for array substrate gate driving circuit, pass through increasing
The slope for adding the output voltage of variable resistance control output end to change effectively reduces the ripple of level translator output electric current,
The effect of electromagnetic interference is reduced simultaneously.
Have been combined that specific examples describe the present invention above, but implementation of the invention is without being limited thereto.In the present invention
Spirit and scope in, various modifications can be carried out and modification by those skilled in the art, these modifications and variations will fall into right
It is required that within the protection scope limited.
Claims (8)
1. a kind of level translator for array substrate gate driving circuit, comprising: first input end, the second input terminal,
Three input terminals, the 4th input terminal and output end, which is characterized in that further include: first resistor device and second resistor；
The first input end receives logic control signal；
Second input terminal receives reference voltage；
One end of the first resistor device receives first voltage, and the third input terminal is connected to the another of the first resistor device
End is to receive voltage from the first resistor device；
One end of the second resistor receives second voltage, and the 4th input terminal is connected to the another of the second resistor
End is to receive voltage from the second resistor；
The output end alternately exports the third input terminal according to the logic control signal and the reference voltage and receives
Voltage and the received voltage of the 4th input terminal；
The first resistor device is the first variable resistance, and the second resistor is the second adjustable resistance device；Described first can
Variohm based on the received the first control parameter and change resistance value, the second adjustable resistance device based on the received second control
Parameter and change resistance value.
2. level translator as described in claim 1, which is characterized in that if the voltage value of the logic control signal is greater than
The voltage value of the reference voltage, then the output end exports the received voltage of third input terminal；
If voltage value of the voltage value of the logic control signal less than the reference voltage, described in the output end output
The 4th received voltage of input terminal.
3. level translator as described in claim 1, which is characterized in that first variable resistance includes multiple resistors
With for selecting the first choice of one of the multiple resistor to switch.
4. level translator as claimed in claim 3, which is characterized in that the first choice switch is according to the first control parameter
Select one of the multiple resistor, thus the third input terminal be connected to the first choice switch the resistor of selection with
The resistor for switching selection from the first choice receives voltage.
5. level translator as described in claim 1, which is characterized in that the second adjustable resistance device includes multiple resistors
With for select one of the multiple resistor second select switch.
6. level translator as claimed in claim 5, which is characterized in that the second selection switch is according to the second control parameter
Select one of the multiple resistor, thus the 4th input terminal be connected to second selection switch the resistor of selection with
The resistor for switching selection from second selection receives voltage.
7. level translator as described in claim 1, which is characterized in that the logic control signal is periodic logic electricity
It is flat.
8. level translator as claimed in claim 7, which is characterized in that the output end exports the third input terminal and receives
Voltage and the received voltage of the 4th input terminal period it is identical as the period of the logic control signal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610311807.6A CN105761694B (en) | 2016-05-12 | 2016-05-12 | Level translator for array substrate gate driving circuit |
| PCT/CN2016/089789 WO2017193469A1 (en) | 2016-05-12 | 2016-07-12 | Level shifter for gate driving circuit of array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610311807.6A CN105761694B (en) | 2016-05-12 | 2016-05-12 | Level translator for array substrate gate driving circuit |
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| Publication Number | Publication Date |
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| CN105761694A CN105761694A (en) | 2016-07-13 |
| CN105761694B true CN105761694B (en) | 2019-02-26 |
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|---|---|---|---|
| CN201610311807.6A Active CN105761694B (en) | 2016-05-12 | 2016-05-12 | Level translator for array substrate gate driving circuit |
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| CN (1) | CN105761694B (en) |
| WO (1) | WO2017193469A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107633798B (en) * | 2017-10-11 | 2020-03-17 | 深圳市华星光电半导体显示技术有限公司 | Potential conversion circuit and display panel |
| TWI646516B (en) * | 2018-01-30 | 2019-01-01 | 瑞鼎科技股份有限公司 | Source driver |
| CN109584829B (en) * | 2018-12-25 | 2020-10-30 | 惠科股份有限公司 | Overcurrent protection method, display panel and overcurrent protection device |
| WO2020223970A1 (en) * | 2019-05-09 | 2020-11-12 | 京东方科技集团股份有限公司 | Gate drive circuit and current adjustment method therefor, and display apparatus |
| CN112530350B (en) * | 2020-12-18 | 2023-07-18 | 厦门天马微电子有限公司 | Display panel and display device |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2017193469A1 (en) | 2017-11-16 |
| CN105761694A (en) | 2016-07-13 |
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