CN105761655B - Source electrode drive circuit - Google Patents
Source electrode drive circuit Download PDFInfo
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- CN105761655B CN105761655B CN201410779719.XA CN201410779719A CN105761655B CN 105761655 B CN105761655 B CN 105761655B CN 201410779719 A CN201410779719 A CN 201410779719A CN 105761655 B CN105761655 B CN 105761655B
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Abstract
A kind of source electrode drive circuit, comprising to receive gamma voltage signal and export the multi-task unit of source electrode driving signal.This multi-task unit includes the first switch and the second switch.When first switch is to first time point in frame time, the first output signal is generated according to first control signal and second control signal.When second switch is to the second time point in frame time, the second output signal is generated according to third control signal and the 4th control signal.Source drive signal be the first output signal and the second output signal and.
Description
Technical field
The present invention relates to a kind of source electrode drive circuits, and in particular to one kind can reduce current peak (peak current)
Source electrode drive circuit.
Background technique
With the promotion of the manufacturing technology of display panel, high-resolution display panel, such as resolution ratio be 1920 ×
The large scale display panel of the display panel of 1080 (full HD) or 3840 × 2160 (4K2K) and 50 inches or more may be used
Mass production.However, for high-resolution display panel, because of the increased relationship of number of pixels, to remain original
Frame rate (frame rate), then source electrode driver must shorten the driving time of each pixel column in display panel, make
Its output electric current must be promoted by obtaining source electrode driver, to charge to each of display panel pixel.
For example, Figure 1A and 1B are please referred to, is the relation schematic diagram for being painted stable time and current peak.Such as Figure 1A
With shown in 1B, the area (i.e. the integral of Current versus time) of the oblique line portion of Figure 1A and 1B is identical, represents source electrode driver to picture
The charged electricity of element is identical, and current peak I in figure 1APHigher than current peak I in fig. ibP, and in fig. ib
Stablize time TSIt is longer than stabilization time T in figure 1AS.Lead to display panel in Figure 1A excessive voltage drop (IR drop)
Driving is abnormal, and the inhibitory effect of electromagnetic interference (electromagnetic interference) is bad and power consumption mistake
High problem.Although the current peak I of Figure 1BPIt is small compared with Figure 1A, but stablizes time TSAlso thus increase, may cause in pixel
Uncharged to correct current potential in charging time, and image is caused to show mistake.
Summary of the invention
The purpose of the invention is to provide a kind of source electrode drive circuits, the charging time of pixel can not be significantly increased
In the case of be effectively reduced its export electric current current peak, and then reach reduce voltage drop, reduce electromagnetic interference influence and section
Save the effect of power consumption.
Above-mentioned purpose according to the present invention proposes a kind of source electrode drive circuit to drive display panel.This source electrode drives
Dynamic circuit includes to receive gamma voltage (Gamma voltage) signal and the first source drive signal of output to display panel
The first pixel column multi-task unit.This multi-task unit includes the first switch and the second switch.First switch is used
When with first time point in the first frame time, the first output letter is generated according to first control signal and second control signal
Number, and the first switch has the first output end to export the first output signal.Second switch is in first frame
In the second time point when, generate the second output signal according to third control signal and the 4th control signal, and second cuts
Parallel operation has the first output end to export the second output signal.Wherein, the first output end of the first switch is coupled to
First output end of two switch, and the first source drive signal be the first output signal and the second output signal and.
An embodiment according to the present invention, above-mentioned first switch include the first CMOS to export the first output signal
Transmission gate (CMOS transmission gate), and above-mentioned second switch includes second to export the second output signal
Cmos transmission gate.
Another embodiment according to the present invention, above-mentioned second time point is after above-mentioned first time point, and the second time
There is the first delay time between point and first time point.
Another embodiment according to the present invention, above-mentioned multi-task unit also include third switch.Third switch to
When third time point in the first frame time, signal is controlled according to the 5th and the 6th control signal generates third output signal,
And third switch has the first output end to export third output signal.Wherein, the first output end of third switch
It is coupled to the first output end of the first switch and the first output end of the second switch, and the first source drive signal is first
Output signal, the second output signal and third output signal and.
Another embodiment according to the present invention, above-mentioned third switch include the third to export third output signal
Cmos transmission gate.
Another embodiment according to the present invention, above-mentioned third time point is after above-mentioned second time point, and the third time
There is the second delay time between point and the second time point.
Another embodiment according to the present invention, above-mentioned multi-task unit is also to export the second source drive signal to display
Second pixel column of panel.Above-mentioned first switch is also to the 4th time point in the second frame time after the first frame time
When, the 4th output signal is generated according to first control signal and second control signal, and the first switch also has to defeated
The second output terminal of 4th output signal out.Above-mentioned second switch also to five time point in the second frame time when,
The 5th output signal is generated according to third control signal and the 4th control signal, and the second switch also has to export the 5th
The second output terminal of output signal.Wherein, the second output terminal of the first switch is coupled to the second output terminal of the second switch,
Second source drive signal be the 4th output signal and the 5th output signal and, and the first source drive signal and the second source electrode
The polarity of driving signal is opposite.
Another embodiment according to the present invention, above-mentioned first switch also include the 4th to export the 4th output signal
Cmos transmission gate, and above-mentioned second switch also includes the 5th cmos transmission gate to export the 5th output signal.
Another embodiment according to the present invention, above-mentioned 5th time point is after above-mentioned 4th time point, and the 5th time
There is third delay time between point and the 4th time point.
Another embodiment according to the present invention, above-mentioned source electrode drive circuit also include output buffer, this output buffer
It is coupled to the input terminal of multi-task unit.
Detailed description of the invention
For above and other objects of the present invention, feature, advantage and embodiment can be clearer and more comprehensible, the explanation of attached drawing is such as
Under:
Figure 1A and 1B is the relation schematic diagram for being painted stable time and current peak；
Fig. 2 is the circuit box schematic diagram for being painted the source electrode drive circuit of the embodiment of the present invention；
Fig. 3 A is the circuit diagram for being painted the first switch in Fig. 2；
Fig. 3 B is the circuit diagram for being painted the second switch in Fig. 2；
Fig. 4 is the timing diagram for being painted each signal in Fig. 2；
Fig. 5 A is the curve synoptic diagram for being painted the output electric current and the relationship of time of the embodiment of the present invention and comparative example；
Fig. 5 B is the curve synoptic diagram of the output voltage for being painted comparative example and the relationship of time；
Fig. 5 C is the curve synoptic diagram of the output voltage for being painted the embodiment of the present invention and the relationship of time；
Fig. 6 is the circuit box schematic diagram for being painted the source electrode drive circuit of the embodiment of the present invention；
Fig. 7 is the circuit diagram for being painted third switch in Fig. 6；And
Fig. 8 is the timing diagram for being painted each signal in Fig. 6.
Specific embodiment
The embodiment of the present invention is hashed out below.It is understood, however, that embodiment provides many applicable hairs
Bright concept may be implemented in miscellaneous specific content.The specific embodiment discussed only for explanation, is not limited to
The scope of the present invention.
Referring to figure 2., Fig. 2 is the circuit box schematic diagram for being painted the source electrode drive circuit 100 of the embodiment of the present invention.Source electrode
Driving circuit 100 includes output buffer 110 and multi-task unit 120.Output buffer 110 receives gamma voltage signal VG,
And gamma voltage signal V of the output after bufferingI.Multi-task unit 120 is to control polar output, and it includes first
Switch 121 and the second switch 122.First switch 121 receives gamma voltage signal VIWith control signal C1, C2, and according to
To generate output signal VO1、VO2, and these output signals V is exported by output end O1, O2 respectivelyO1、VO2.Second switch 122
Receive gamma voltage signal VIWith control signal C3, C4, and accordingly generate output signal VO3、VO4, and respectively by output end O3, O4
To export these output signals VO3、VO4.Output signal VO1、VO3And be source drive signal VD1, and output signal VO2、VO4's
With for source drive signal VD2.Source drive signal VD1It is input to the odd pixel column of display panel (figure is not painted), and source electrode
Driving signal VD2It is input to the even pixel column of display panel (figure is not painted).Alternatively, source drive signal VD1It is input to display
The even pixel column of panel (figure is not painted), and source drive signal VD2It is input to the odd pixel of display panel (figure is not painted)
Column.In some embodiments, source drive signal VD1And VD2It is separately input into the two adjacent of display panel (figure is not painted)
Pixel column.In some embodiments, source drive signal VD1And VD2Polarity be opposite.That is, source drive signal VD1And VD2's
Polarity is respectively positive polarity and negative polarity or source drive signal VD1And VD2Polarity be respectively negative polarity and positive polarity.
A referring to figure 3., Fig. 3 A are the circuit diagrams for being painted the first switch 121 in Fig. 2.First switch 121 includes
Cmos transmission gate TG1、TG2.Cmos transmission gate TG1With N-type transistor NM1With P-type transistor PM1.N-type transistor NM1Grid
Pole input control signal C1, and P-type transistor PM1Gate input control signalControl signalTo control signal C1
Inversion signal, in the present embodiment, control signalIt is to pass through phase inverter INV by control signal C11To obtain.At it
In its embodiment, signal is controlledIt is directly to be provided by the circuit outside the first switch 121.N-type transistor NM1Source electrode
With P-type transistor PM1Drain electrode be electrically connected to intersection point PI1, and intersection point PI1To input gamma voltage signal VI.N-type transistor
NM1Drain electrode and P-type transistor PM1Source electrode be electrically connected to intersection point PO1, and intersection point PO1To output signal output VO1.It is similar
Ground, cmos transmission gate TG2With N-type transistor NM2With P-type transistor PM2.N-type transistor NM2Gate input control signal
C2, and P-type transistor PM2Gate input control signalControl signalFor control signal C2 inversion signal,
In the present embodiment, signal is controlledIt is to pass through phase inverter INV by control signal C22To obtain.In other embodiments, it controls
Signal processedIt is directly to be provided by the circuit outside the first switch 121.N-type transistor NM2Source electrode and P-type transistor PM2
Drain electrode be electrically connected to intersection point PI2, and intersection point PI2To input gamma voltage signal VI.N-type transistor NM2Drain electrode and p-type
Transistor PM2Source electrode be electrically connected to intersection point PO2, and intersection point PO2To output signal output VO2。
It should be noted that above-mentioned transmission gate TG1In N-type transistor NM1, P-type transistor PM1With intersection point PI1、PO1Company
The relationship of connecing is corresponding output signal VO1Level be higher than gamma voltage signal VI.Ability preforming technique personnel can be according to different designs
Demand and to above-mentioned transmission gate TG1In the connection relationship of each element carry out corresponding change or change.For example, if making
Gamma voltage signal VILevel be higher than output signal VO1, can be by transmission gate TG1Change into N-type transistor NM1Drain electrode and p-type
Transistor PM1Source electrode be electrically connected to intersection point PI1, and intersection point PI1To input gamma voltage signal VI, and N-type transistor NM1's
Source electrode and P-type transistor PM1Drain electrode be electrically connected to intersection point PO1, and intersection point PO1To output signal output VO1.Similarly, exist
Transmission gate TG2In N-type transistor NM2, P-type transistor PM2With intersection point PI2、PO2Connection relationship also can be according to different designs
Demand and carry out corresponding change or change.
B referring to figure 3., Fig. 3 B are the circuit diagrams for being painted the second switch 122 in Fig. 2.Second switch 122 includes
Cmos transmission gate TG3、TG4.Cmos transmission gate TG3With N-type transistor NM3With P-type transistor PM3.N-type transistor NM3Grid
Pole input control signal C3, and P-type transistor PM3Gate input control signalControl signalTo control signal C3
Inversion signal, in the present embodiment, control signalIt is to be obtained by control signal C3 by phase inverter.In other realities
It applies in example, controls signalIt is directly to be provided by the circuit outside the second switch 122.N-type transistor NM3Source electrode and p-type
Transistor PM3Drain electrode be electrically connected to intersection point PI3, and intersection point PI3To input gamma voltage signal VI.N-type transistor NM3Leakage
Pole and P-type transistor PM3Source electrode be electrically connected to intersection point PO3, and intersection point PO3To output signal output VO3.Similarly, CMOS
Transmission gate TG4With N-type transistor NM4With P-type transistor PM4.N-type transistor NM4Gate input control signal C4, and p-type
Transistor PM4Gate input control signalControl signalFor control signal C4 inversion signal, in the present embodiment
In, control signalIt is to be obtained by control signal C4 by phase inverter.In other embodiments, signal is controlledIt is
It is directly provided by the circuit outside the second switch 122.N-type transistor NM4Source electrode and P-type transistor PM4Drain electrode electrical connection
To intersection point PI4, and intersection point PI4To input gamma voltage signal VI.N-type transistor NM4Drain electrode and P-type transistor PM4Source
Pole is electrically connected to intersection point PO4, and intersection point PO4To output signal output VO4。
Illustrate the operation of source electrode drive circuit 100 below in conjunction with Fig. 4.(this time point when frame time FRAME1 starts
It is defined as t1), control signal C1 is switched to high levle, and controls signal C3 and be maintained low level.At this point, cmos transmission gate TG1It leads
It is logical, so that source drive signal VD1Voltage value begin to ramp up, and export electric current IDIt is increased to current peak IP1.Meanwhile source electrode
Driving signal VD2Voltage value begin to decline.In delay time TSDIn, export electric current IDThe rate of decay, source drive signal
VD1Voltage value the rate of climb and source drive signal VD2The decrease speed of voltage value gradually slow down.In frame time
In FRAME1, electric current I is exportedDCorresponding to source drive signal VD1。
By delay time TSDAfterwards, time point t is then come2.At this point, control signal C3 is switched to high levle, with conducting
Cmos transmission gate TG3.Meanwhile exporting electric current IDAlso because of cmos transmission gate TG3Conducting and be increased to current peak IP2.One
In a little embodiments, stablizing time TS’When output electric current IDThe rate of decay, source drive signal VD1Voltage value rising
Speed and source drive signal VD2Voltage value decrease speed compared in delay time TSDWhen be fast.
Until by stablizing time TS’Afterwards, i.e. arrival time point t3When, source drive signal VD1Rise to high potential, source electrode
Driving signal VD2Low potential is dropped to, and exports electric current IDIt is reduced to and levels off to 0.Delay time TSDWith stablize time TS’It is total
As source drive signal VD1The stabilization time T passed through when being increased to high potential by low potentialS。
In time point t4When, control signal C1 and C3 are switched to low level.When control signal C1 and C3 are high levle
Elapsed time (i.e. time point t2To time point t4) it is defined as full driving time TFD。
Then, when frame time FRAME2 starts, (this time point is defined as t5), control signal C2 is switched to high levle, and
Control signal C4 is maintained low level.At this point, cmos transmission gate TG2Conducting, so that source drive signal VD2Voltage value start
Rise, and exports electric current IDIt is increased to current peak IP3.Meanwhile source drive signal VD1Voltage value begin to decline.Postponing
Time TSDIn, export electric current IDThe rate of decay, source drive signal VD2Voltage value the rate of climb and source drive signal
VD1The decrease speed of voltage value gradually slow down.In frame time FRAME2, electric current I is exportedDCorresponding to source drive signal VD2。
By delay time TSDAfterwards, time point t is then come6.At this point, control signal C4 is switched to high levle, with conducting
Cmos transmission gate TG4.Meanwhile exporting electric current IDAlso because of cmos transmission gate TG4Conducting and be increased to current peak IP4.One
In a little embodiments, stablizing time TS’When output electric current IDThe rate of decay, source drive signal VD2Voltage value rising
Speed and source drive signal VD1Voltage value decrease speed compared in delay time TSDWhen be fast.
Until by stablizing time TS’Afterwards, i.e. arrival time point t7When, source drive signal VD2Rise to high potential, source electrode
Driving signal VD1Low potential is dropped to, and exports electric current IDIt is reduced to and levels off to 0.Delay time TSDWith stablize time TS’It is total
As source drive signal VD2The stabilization time T passed through when being increased to high potential by low potentialS。
In time point t8When, control signal C2 and C4 are switched to low level.When control signal C2 and C4 are high levle
Elapsed time (i.e. time point t6To time point t8) it is full driving time TFD.Then, in time point t9When, start next
Frame time.
Illustrate below in delay time TSDWith stablize time TS’In output electric current ID.It is defeated for frame time FRAME1
Electric current I outDAs shown in formula (1):
Wherein, ID(t) it represents in time t (t1≤t<t3) when output electric current ID, RLFor source drive signal VD1It is inputted
Subsequent conditioning circuit (figure be not painted) equivalent resistance, Vov=VH-VSS+Vtp, VHFor gamma voltage signal VIHigh levle voltage
Value, VSSFor the low level voltage value for controlling signal C1~C4, and VtpFor cmos transmission gate TG1、TG2Threshold voltage
(threshold voltage).In time t between time point t1With t2Between (t1≤t < t2) when, parameter k and voltage difference delta V points
Not as shown in formula (2) and formula (3):
And (2)
Wherein, μnFor cmos transmission gate TG1Carrier mobility (carrier mobility), CoxFor cmos transmission gate
TG1Gate dielectric capacitance, CLFor source drive signal VD1The equivalent electricity of the subsequent conditioning circuit (figure is not painted) inputted
Capacitance,For cmos transmission gate TG1Channel breadth length ratio (channel aspect ratio), and VLFor gamma voltage
Signal VILow level voltage value.Because of current peak IP1Appear in time point t1, therefore current peak IP1It can be by calculating ID(t1) and
It obtains.
In addition, in time t between time point t2With t3Between (t2≤t<t3) when, parameter k and voltage difference delta V are respectively such as formula
(4) and shown in formula (5):
And (4)
Wherein,For cmos transmission gate TG3Channel breadth length ratio.Similarly, because of current peak IP2When appearing in
Between point t2, therefore current peak IP2It can be by calculating ID(t2) and obtain.In the present embodiment, cmos transmission gate TG1And TG3Load
The capacitance for flowing transport factor and gate dielectric is equal.Output electric current I in frame time FRAME2D, parameter k and voltage difference delta
V and current peak IP3And IP4Also can by it is simple change formula (1) to the content of formula (5) after obtain, therefore this will not be repeated here.
It should be noted that current peak IP1~IP4, delay time TSDWith stablize time TS’Value be not intended to be limited to fix.
It can make corresponding adjustment according to design requirement.It for example, can be by change cmos transmission gate TG1Channel breadth length ratio design
And adjust current peak IP1, and can be by change delay time TSDLength come correspond to adjustment current peak IP2With stablize the time
TS’Length.
Fig. 5 A is the curve synoptic diagram for being painted the output electric current and the relationship of time of the embodiment of the present invention and comparative example.This hair
Bright embodiment is using the multi-task unit comprising two switch, and such as the multi-task unit 120 of Fig. 2, and comparative example is to use
It only include the multi-task unit of a switch.Wherein, two switch used in the embodiment of the present invention are made with comparative example
Switch is made of two cmos transmission gates.The channel breadth length ratio of cmos transmission gate used in the embodiment of the present invention
Sum equal to cmos transmission gate used in comparative example channel breadth length ratio.For Fig. 3 A and 3B, cmos transmission gate TG1It is logical
Road breadth length ratio and cmos transmission gate TG3Channel breadth length ratio sum it is long for the channel width of one of cmos transmission gate of comparative example
Than, and cmos transmission gate TG2Channel breadth length ratio and cmos transmission gate TG4Channel breadth length ratio sum for comparative example another
The channel breadth length ratio of cmos transmission gate.Fig. 5 A is the analog result of the embodiment of the present invention and comparative example, and in formula (1) to formula (5)
In, RLIt is set as 10k Ω, CLIt is set as 100pF, VHIt is set as 9V, VLIt is set as 1V, VSSIt is set as 0V, VtpBe set as-
1.65V kSDIt is set as 21.7 μ A/V2, kSDIt is set as 21.7 μ A/V2, kFDIt is set as 86.7 μ A/V2, and delay time TSDSetting
For 0.8 microsecond.
As shown in Figure 5A, when the time is 0, one of cmos transmission gate (such as Fig. 3 A is first connected in the embodiment of the present invention
Cmos transmission gate TG1), so that output electric current is increased to 450 μ A, and the output electric current of comparative example is increased to 700 μ A.Then,
The output electric current of the embodiment of the present invention and comparative example gradually decreases at any time.By 0.8 microsecond (micro-second；μs)
Afterwards, another cmos transmission gate (such as cmos transmission gate TG of Fig. 3 B is connected in the embodiment of the present invention again3), so that output electric current is again
440 μ A are increased to, and the output electric current of comparative example maintains the trend gradually decreased.Later, the embodiment of the present invention and comparative example
Output electric current be gradually decrease to 0 at any time.
By Fig. 5 A it is found that the current peak of the embodiment of the present invention is 450 μ A and 440 μ A, and the current peak of comparative example is
700μA.Therefore, compared to comparative example, the embodiment of the present invention can produce lower current peak.
It is the curve signal of the output voltage for being painted comparative example and the relationship of time referring to Fig. 5 B and 5C, Fig. 5 B
Figure, and Fig. 5 C is output voltage (such as the source drive signal V of Fig. 2 for being painted the embodiment of the present inventionD1Voltage value) and time
Relationship curve synoptic diagram.Compare Fig. 5 B and 5C it is found that the output voltage of the embodiment of the present invention is between 0 second and 0.8 microsecond
The rate of climb compared with the output voltage of comparative example be it is slow, be attributed to the embodiment of the present invention and be only connected between 0 second and 0.8 microsecond
One of cmos transmission gate.In 0.8 microsecond, because another cmos transmission gate is about switched to conducting shape in 0.8 microsecond
State, so that the rate of climb of output voltage increases.By Fig. 5 B and 5C it is found that the output voltage of comparative example is risen to by low level (1V)
It is 5.6059 microseconds the time required to high levle (9V), and the output voltage of the embodiment of the present invention is risen to needed for high levle as low level
Time is 5.8691 microseconds.
Compared to comparative example, although the stabilization time of the embodiment of the present invention, (i.e. output voltage increased supreme standard by low level
Position is reduced to low level required time by high levle) increase about 5% a little, but the current peak of the embodiment of the present invention can be substantially
Reduce about 36%.Therefore, source electrode drive circuit of the invention can be in the case where not being significantly increased the charging time of pixel effectively
Reduce its current peak for exporting electric current.
In source electrode drive circuit of the invention, multi-task unit may include multiple switch, and not two depicted in Fig. 2
A switch is limited.For example, Fig. 6 is please referred to, Fig. 6 is the circuit for being painted the source electrode drive circuit 200 of the embodiment of the present invention
Block schematic diagram.Source electrode drive circuit 200 includes output buffer 210 and multi-task unit 220.Output buffer 210 receives
Gamma voltage signal VG, and export the gamma voltage signal V after bufferingI.Multi-task unit 220 is polar defeated to control
Out, and it includes the first switch 221, the second switch 222 and third switch 223.First switch 221 receives gamma electricity
Press signal VIWith control signal C1, C2, and accordingly generate output signal VO1、VO2, and these are exported by output end O1, O2 respectively
Output signal VO1、VO2.Second switch 222 receives gamma voltage signal VIWith control signal C3, C4, and accordingly generate output letter
Number VO3、VO4, and these output signals V is exported by output end O3, O4 respectivelyO3、VO4.Third switch 223 receives gamma voltage
Signal VIWith control signal C5, C6, and accordingly generate output signal VO5、VO6, and it is defeated to export these by output end O5, O6 respectively
Signal V outO5、VO6.Output signal VO1、VO3、VO5And be source drive signal VD1, and output signal VO2、VO4、VO6Sum be
Source drive signal VD2.Source drive signal VD1It is input to the odd pixel column of display panel (figure is not painted), and source drive
Signal VD2It is input to the even pixel column of display panel (figure is not painted).Alternatively, source drive signal VD1It is input to display panel
The even pixel column of (figure is not painted), and source drive signal VD2It is input to the odd pixel column of display panel (figure is not painted).
In some embodiments, source drive signal VD1And VD2It is separately input into two adjacent pictures of display panel (figure is not painted)
Element column.In some embodiments, source drive signal VD1And VD2Polarity be opposite.That is, source drive signal VD1And VD2Pole
Property is respectively positive polarity and negative polarity or source drive signal VD1And VD2Polarity be respectively negative polarity and positive polarity.
The circuit structure of the first switch 221 and the second switch 222 in Fig. 6 respectively with the first switch in Fig. 2
121 and second switch 122 it is identical, therefore this will not be repeated here for the circuit structure of the first switch 221 and the second switch 222.Please
Referring to Fig. 7, Fig. 7 is the circuit diagram for being painted third switch 223 in Fig. 6.Third switch 223 includes cmos transmission gate
TG5、TG6.Cmos transmission gate TG5With N-type transistor NM5With P-type transistor PM5.N-type transistor NM5Grid input control
Signal C5, and P-type transistor PM5Gate input control signalControl signalFor control signal C5 inversion signal,
In the present embodiment, signal is controlledIt is to pass through phase inverter INV by control signal C55To obtain.In other embodiments,
Control signalIt is directly to be provided by the circuit outside third switch 223.N-type transistor NM5Source electrode and P-type transistor
PM5Drain electrode be electrically connected to intersection point PI5, and intersection point PI5To input gamma voltage signal VI.N-type transistor NM5Drain electrode and P
Transistor npn npn PM5Source electrode be electrically connected to intersection point PO5, and intersection point PO5To output signal output VO5.Similarly, cmos transmission gate
TG6With N-type transistor NM6With P-type transistor PM6.N-type transistor NM6Gate input control signal C6, and P-type transistor
PM6Gate input control signalControl signalFor the inversion signal for controlling signal C6, in the present embodiment, control
SignalIt is to pass through phase inverter INV by control signal C66To obtain.In other embodiments, signal is controlledIt is by
Circuit outside three switch 223 directly provides.N-type transistor NM6Source electrode and P-type transistor PM6Drain electrode be electrically connected best friend
Point PI6, and intersection point PI6To input gamma voltage signal VI.N-type transistor NM6Drain electrode and P-type transistor PM6Source electrode electricity
It is connected to intersection point PO6, and intersection point PO6To output signal output VO6。
Illustrate the operation of source electrode drive circuit 200 below in conjunction with Fig. 8.(this time point when frame time FRAME1 starts
It is defined as t1), control signal C1 is switched to high levle, and controls signal C3 and C5 and be maintained low level.At this point, cmos transmission gate
TG1Conducting, so that source drive signal VD1Voltage value begin to ramp up, and export electric current IDIt is increased to current peak IP1’.Together
When, source drive signal VD2Voltage value begin to decline.In delay time TSD1In, export electric current IDThe rate of decay, source electrode drive
Dynamic signal VD1Voltage value the rate of climb and source drive signal VD2The decrease speed of voltage value gradually slow down.In frame
Between in FRAME1, export electric current IDSystem corresponds to source drive signal VD1。
By delay time TSD1Afterwards, time point t is then come2.At this point, control signal C3 is switched to high levle, with conducting
Cmos transmission gate TG3, and control signal C5 and be maintained low level.Meanwhile exporting electric current IDAlso because of cmos transmission gate TG3Lead
Lead to and is increased to current peak IP2’.In delay time TSD2In, export electric current IDThe rate of decay, source drive signal VD1Electricity
The rate of climb and source drive signal V of pressure valueD2The decrease speed of voltage value gradually slow down.In some embodiments, prolonging
Slow time TSD2When output electric current IDThe rate of decay, source drive signal VD1Voltage value the rate of climb and source drive
Signal VD2Voltage value decrease speed compared in delay time TSD1When be fast.
By delay time TSD2Afterwards, time point t is then come3.At this point, control signal C5 is switched to high levle, with conducting
Cmos transmission gate TG5.Meanwhile exporting electric current IDAlso because of cmos transmission gate TG5Conducting and be increased to current peak IP3’.One
In a little embodiments, stablizing time TS’When output electric current IDThe rate of decay, source drive signal VD1Voltage value rising
Speed and source drive signal VD2Voltage value decrease speed compared in delay time TSD1And TSD2When be fast.
Until by stablizing time TS’Afterwards, i.e. arrival time point t4When, source drive signal VD1Rise to high potential, source electrode
Driving signal VD2Low potential is dropped to, and exports electric current IDIt is reduced to and levels off to 0.Delay time TSD1And TSD2With stablize time TS’
Summation be source drive signal VD1The stabilization time T passed through when being increased to high potential by low potentialS。
In time point t5When, control signal C1, C3 and C5 are switched to low level.Controlling signal C1, C3 and C5 is height
Elapsed time (time point t when level3To time point t5) it is defined as full driving time TFD。
Then, when frame time FRAME2 starts, (this time point is defined as t6), control signal C2 is switched to high levle, and
Control signal C4 and C6 are maintained low level.At this point, cmos transmission gate TG2Conducting, so that source drive signal VD2Voltage value
It begins to ramp up, and exports electric current IDIt is increased to current peak IP4’.Meanwhile source drive signal VD1Voltage value begin to decline.?
Delay time TSD1In, export electric current IDThe rate of decay, source drive signal VD2Voltage value the rate of climb and source drive
Signal VD1The decrease speed of voltage value gradually slow down.In frame time FRAME2, electric current I is exportedDBelieve corresponding to source drive
Number VD2。
By delay time TSD1Afterwards, time point t is then come7.At this point, control signal C4 is switched to high levle, with conducting
Cmos transmission gate TG4, and control signal C6 and be maintained low level.Meanwhile exporting electric current IDAlso because of cmos transmission gate TG4Lead
Lead to and is increased to current peak IP5’.In delay time TSD2In, export electric current IDThe rate of decay, source drive signal VD2Electricity
The rate of climb and source drive signal V of pressure valueD1The decrease speed of voltage value gradually slow down.In some embodiments, prolonging
Slow time TSD2When output electric current IDThe rate of decay, source drive signal VD2Voltage value the rate of climb and source drive
Signal VD1Voltage value decrease speed compared in delay time TSD1When be fast.
By delay time TSD2Afterwards, time point t is then come8.At this point, control signal C6 is switched to high levle, with conducting
Cmos transmission gate TG6.Meanwhile exporting electric current IDAlso because of cmos transmission gate TG6Conducting and be increased to current peak IP6’.One
In a little embodiments, stablizing time TS’When output electric current IDThe rate of decay, source drive signal VD2Voltage value rising
Speed and source drive signal VD1Voltage value decrease speed compared in delay time TSD1And TSD2When be fast.
Until by stablizing time TS’Afterwards, i.e. arrival time point t9When, source drive signal VD2Rise to high potential, source electrode
Driving signal VD1Low potential is dropped to, and exports electric current IDIt is reduced to and levels off to 0.Delay time TSD1And TSD2With stablize time TS’
Summation be source drive signal VD2The stabilization time T passed through when being increased to high potential by low potentialS。
In time point t10When, control signal C2, C4 and C6 are switched to low level.Controlling signal C2, C4 and C6 is height
Elapsed time (time point t when level8To time point t10) it is full driving time TFD.Then, in time point t11When, it opens
Begin next frame time.
Fig. 2 and Fig. 6 is two and three respectively with switch, and to be embodiment explain, and those skilled in the art are when can be according to
It extends to according to the explanation of above-described embodiment and is implemented with three or more switch, therefore the embodiment of three or more switch is also
Covered by the present invention.By taking source electrode drive circuit has M switch as an example, if the circuit structure of this M switch and Fig. 3 A
Depicted circuit structure is identical, the cmos transmission gate in a frame time in this M switch of turn in order, and this M are cut
The time point that cmos transmission gate in parallel operation is switched on state is sequentially t1、t2、…、tM, then electric current such as formula (6) institute is exported
Show:
Wherein 1≤i≤M and i are positive integer, and parameter kiWith voltage difference delta V respectively as shown in formula (7) and formula (8):
And (7)
In conclusion source electrode drive circuit of the invention can be effectively reduced under the charging time for pixel not being significantly increased
Its current peak for exporting electric current, and then reach the effect for reducing voltage drop, the influence for reducing electromagnetic interference and saving power consumption
Fruit.
Although the present invention is disclosed above with embodiment, however, it is not to limit the invention, any art technology
Personnel, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations, therefore protection scope of the present invention
Subject to view appended claims institute defender.
[symbol description]
100,200: source electrode drive circuit
110,210: output buffer
120,220: multi-task unit
121,221: the first switch
122,222: the second switch
223: third switch
C1~C6,Control signal
ID: output electric current
FRAME1, FRAME2: frame time
INV1~INV6: phase inverter
IP、IP1、IP2、IP3、IP4、IP1’、IP2’、IP3’、IP4’、IP5’、IP6': current peak
NM1~NM6: N-type transistor
O1~O6: output end
PI1~PI6、PO1~PO6: intersection point
PM1~PM6: P-type transistor
t1~t11: time point
TFD: full driving time
TS、TS’: stablize the time
TSD、TSD1、TSD2: delay time
TG1~TG6: cmos transmission gate
VD1、VD2: source drive signal
VG、VI: gamma voltage signal
VO1~VO6: output signal
Claims (10)
1. a kind of source electrode drive circuit, to drive display panel, the source electrode drive circuit includes:
Multi-task unit to receive gamma voltage signal, and exports the first source drive signal to the of the display panel
One pixel column, the multi-task unit includes:
First switch, when to first time point in the first frame time, according to first control signal and the second control letter
Number and generate the first output signal, and first switch have to export first output signal first output
End；And
Second switch, when to the second time point in first frame time, according to third control signal and the 4th control
Signal processed and generate the second output signal, and second switch have to export the first of second output signal it is defeated
Outlet；
Wherein, the first output end of first switch is coupled to the first output end of second switch, and described
One source drive signal be first output signal and second output signal and.
2. source electrode drive circuit as described in claim 1, wherein first switch includes defeated to export described first
First cmos transmission gate of signal out, and second switch includes the 2nd CMOS to export second output signal
Transmission gate.
3. source electrode drive circuit as described in claim 1, wherein second time point after the first time point, and
There is the first delay time between second time point and the first time point.
4. source electrode drive circuit as described in claim 1, wherein the multi-task unit also includes:
Third switch when to third time point in first frame time, controls signal and the 6th control according to the 5th
Signal processed and generate third output signal, and the third switch have to export the first of the third output signal it is defeated
Outlet；
Wherein, the first output end of the third switch is coupled to the first output end and described second of first switch
First output end of switch, and the first source drive signal is first output signal, second output signal
With the third output signal and.
5. source electrode drive circuit as claimed in claim 4, wherein the third switch includes defeated to export the third
The third cmos transmission gate of signal out.
6. source electrode drive circuit as claimed in claim 4, wherein the third time point after second time point, and
There is the second delay time between the third time point and second time point.
7. source electrode drive circuit as described in claim 1, in which:
Second pixel column of the multi-task unit also to export the second source drive signal to the display panel；
First switch also to four time point in the second frame time after first frame time when, according to institute
State first control signal and the second control signal and generate the 4th output signal, and first switch also have to
Export the second output terminal of the 4th output signal；And
Second switch also to five time point in second frame time when, according to the third control signal
With it is described 4th control signal and generate the 5th output signal, and second switch also have it is defeated to export the described 5th
The second output terminal of signal out；
Wherein, the second output terminal of first switch is coupled to the second output terminal of second switch, and described second
Source drive signal be the 4th output signal and the 5th output signal and, and the first source drive signal and
The polarity of the second source drive signal is opposite.
8. source electrode drive circuit as claimed in claim 7, wherein first switch also includes to export the described 4th
4th cmos transmission gate of output signal, and second switch also includes the 5 to export the 5th output signal
Cmos transmission gate.
9. source electrode drive circuit as claimed in claim 7, wherein the 5th time point after the 4th time point, and
There is third delay time between 5th time point and the 4th time point.
10. source electrode drive circuit as described in claim 1, also includes output buffer, the output buffer is coupled to institute
State the input terminal of multi-task unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410779719.XA CN105761655B (en) | 2014-12-16 | 2014-12-16 | Source electrode drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410779719.XA CN105761655B (en) | 2014-12-16 | 2014-12-16 | Source electrode drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105761655A CN105761655A (en) | 2016-07-13 |
| CN105761655B true CN105761655B (en) | 2019-07-26 |
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|---|---|---|---|
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4401090B2 (en) * | 2003-03-14 | 2010-01-20 | パナソニック株式会社 | Display device and driving method thereof |
| TWI293447B (en) * | 2005-08-31 | 2008-02-11 | Chunghwa Picture Tubes Ltd | Apparatus for driving a thin-film transistor liquid crystal display |
| KR100795687B1 (en) * | 2006-06-19 | 2008-01-21 | 삼성전자주식회사 | Output circuit and method of source driver |
| TWI367473B (en) * | 2007-07-11 | 2012-07-01 | Novatek Microelectronics Corp | Source driver with charge sharing |
| KR101101112B1 (en) * | 2010-01-19 | 2011-12-30 | 주식회사 실리콘웍스 | Circuit for generating gamma reference voltage of source driver |
| TWI478130B (en) * | 2010-08-13 | 2015-03-21 | Fitipower Integrated Tech Inc | Source driver and display apparatus |
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