CN105760562B

CN105760562B - The IC design framework read based on layering

Info

Publication number: CN105760562B
Application number: CN201410791712.XA
Authority: CN
Inventors: 吴国盛
Original assignee: Qingdao Robei Electronics Co Ltd
Current assignee: Qingdao Robei Electronics Co Ltd
Priority date: 2014-12-19
Filing date: 2014-12-19
Publication date: 2019-05-10
Anticipated expiration: 2034-12-19
Also published as: CN105760562A

Abstract

The present invention provides the IC design framework read based on layering, including at least one module, each module form (n >=0) by n submodule, it is characterized in that, the data information bedding storage of each module, is formed with M layers, every layer of tree (M >=1, N >=1) for having N number of module；When reading/call certain module, selective reading is carried out by the data of the tree, that is, only next straton block code of current block is read in selection, and reading/calling of current block can be completed.The present invention greatly improves the reading efficiency of IC design, improves the speed of service, keeps design more convenient, efficient.

Description

The IC design framework read based on layering

Technical field

The present invention relates to IC design technical fields, specifically, being related to a kind of integrated electricity read based on layering Road design architecture.

Background technique

Currently, the ISE, the Quartus of Altera, MentorGraphics of many integrated circuit design tools such as Xilinx Modelsim etc., mainstream thoughts are the designs of process oriented.Design method includes interface and Code Design.

Interface is based primarily upon component common in the market and is combined line design, and the advantages of interface is that design is non- Chang Zhiguan, but flexibility is inadequate.If newly increasing the device element being not present in interface, generally require to write code, It is packaged, updates to component inventory, from device library lookup and the processes such as using, once component designs wrong, just may require that and return again To code revision and repack.Existing device needs to substitute again in the design.Process is complicated to waste designer A large amount of time, especially source code are accidentally lost, it will directly resulting in module can not modify, and designer needs to redo.

Code Design is current popular design method, and either Component Interface defines, module example or function It is able to achieve, is all realized with language designs such as Verilog, VHDL or SystemC.The advantages of Code Design is flexibly, to want to write assorted Device just writes any device, and defect is not intuitive enough.Engineer, which needs to run through big section code, just will appreciate that its function and structure Information, while when writing example needs to carry out writing example according to code, to compare and check repeatedly interface name and The information such as data width prevent from malfunctioning.The code of exampleization be also it is hand-written based on.

No matter interface or Code Design, can be complicated at one by IC partition at several modules In integrated circuit, the module of substantial amounts is usually contained, reads and call speed to directly affect the design of integrated circuit And operation.Traditional reading manner is traversal, needs all layers of structure all to read out every time, each module will visit It asks, greatly reduces treatment effeciency.

Summary of the invention

In order to solve the disadvantage that reading efficiency is low in IC design framework, the present invention proposes a kind of based on layering reading IC design framework, specific technical solution is as follows:

Based on the IC design framework that layering is read, including at least one module, each module is by n submodule group At n >=0；The data information bedding storage of each module, is formed with M layers, every layer of tree for having N number of module, wherein M >= 1, N >=1；When reading/call certain module, selective reading is carried out by the data of the tree, that is, only current mould is read in selection Next straton block code of block, can be completed reading/calling of current block.

Wherein, several visualizations of the module setting, editable attribute.

Further, respective pins are arranged in the module, are connected the respective pins of disparate modules by connecting line.

Further, the IC design framework further includes algorithm design cell, for being manually entered, editing procedure Source code.

Further, the IC design framework further includes code integrated unit, is used for module, pin, connection The source code of line, and the source code fusion being manually entered, form the model with complete code structure.

Further, the source code is the source code based on Verilog, VHDL or SystemC language.

Method of designing integrated circuit is visualized, is sequentially included the following steps:

Step 1: creating a module in interface unit, and the corresponding attribute of setup module, included module title, Module type, code language, input pin number, output pin number and can not only do input but the pin exported can be done Number；

Step 2: the attribute of the pin of editor module；

Step 3: algorithm routine code is inputted in algorithm design cell；

Step 4: saving and runs, and executes code error inspection and modifies, until all modification is correct by error code.

The IC design framework provided by the present invention read based on layering, is had the advantage that

The present invention is to the module of integrated circuit in such a way that layering is read, if an integrated circuit has M layers, every layer has N number of module, then the access speed of entire project is O (MN), and the scheme that the present invention uses is the speed of Ο (N).It uses tree-shaped Structure stores code in more apparent mode, and the process of reading does not need to be converted into structure from code again, is reading speed Have on degree and is obviously promoted.

Detailed description of the invention

Fig. 1 is that the present invention is based on the IC design configuration diagrams that layering is read；

Fig. 2 is IC design configuration diagram in the embodiment of the present invention 1.

Specific embodiment

The IC design framework read the present invention is based on layering is made with reference to the accompanying drawings and embodiments further detailed Thin explanation.

Altogether include seven modules based on the IC design framework that layering is read in conjunction with Fig. 1, wherein top-level module by Module 1 and module 2 form, and module 1 is made of submodule 1 and submodule 2；Module 2 is made of submodule 3 and submodule 4, each The data information bedding storage of module forms 3 layers of tree-like storage structure.When reading/call certain module, by the tree Data carry out selective reading, that is, only next straton block code of current block is read in selection, and current block can be completed Reading/calling.

Embodiment 1: IC design framework is merged with code in interface:

In conjunction with Fig. 2, the present embodiment uses a kind of hierarchical design mode of object-oriented, design is simplified to simplest Several basic elements, each element possess corresponding attribute, by the modes such as code and interface mutual cooperation, realize integrated The simplification and the visual design of circuit.Specifically: visualization IC design framework, including interface unit, algorithm are set Unit and integrated unit: encapsulated circuit module, pin, connecting line in the interface unit are counted, for being visualized Drag operation design；Code editor is arranged in the algorithm design cell, for inputting, editing procedure code；Integrated unit is raw At the circuit module of interface unit, pin, connecting line source code, and merge to have been formed with the code of algorithm design cell Whole code.

In operating level, the mode of a variety of forms establishes module in image windows, which possesses corresponding attribute, Drawing layout is carried out according to the appearance attribute of each module, is opened up in property window according to the configurable attribute of each module Show, and determine which part attribute can be modified according to shielded feature, user is directly fed back in module after having modified, to mould The data information of block is modified, and updates the display information in all forms.In order to solve modify to which element, if The information for determining the current block that mouse is chosen is shown inside attribute Editor.Selected module is only the mould that can be changed Block.

The code generating method of the IC design framework of the present embodiment, comprising the following steps: A: in interface list Member creates several modules, and the attribute of setup module, generates corresponding statement code according to the attribute of each module, including to more The processing of remaining signal and the processing of data width, such as the pin that bit wide is 8, user can input 8, can also input 7:0, It is correctly converted automatically when code building；B: algorithm routine code is inputted in algorithm design cell, by hand in module The code section of dynamic input is placed on corresponding position in statement code；C: the attribute disparate modules of the pin of editor module according to Correlation is connected by connecting line；D: stating module example, is connected according to the attribute of module with pin each in module Information carry out example block code and automatically generate；E: by the every traveling row number of code segment, after the row number+1 of structure sheaf Base Serial Number as code layer；F: saving and runs, and executes code error inspection and to error code line flag and modifies, until By error code, all modification is correct.

Module reading/calling:

Referring to Fig.1, as currently needed reading/calling module 1, reading submodule 1, submodule 1 and its connection relationship letter are only needed Breath, without traversing top-level module and other module informations, substantially increases reading/calling speed.

Embodiment 2, pure code IC design framework:

Difference from Example 1 is that the information such as module and its pin, connection relationship are all compiled by being manually entered code It writes.

The foregoing is only a preferred embodiment of the present invention, cannot be limited the scope of implementation of the present invention with this, i.e., but It is all according to simple equivalent changes and modifications made by scope of the present invention patent and invention description content, all still belong to it is of the invention specially In the range of benefit covers.

Claims

1. based on the IC design system that layering is read, including at least one module, each module is by n submodule group At n >=0；It is characterized in that, the data information bedding storage of each module, it is formed with M layers, every layer of tree-shaped knot for having N number of module Structure, wherein M >=1, N >=1；When reading/call certain module, selective reading is carried out by the data of the tree, that is, only select The next straton block code for reading current block, can be completed reading/calling of current block.

2. the IC design system according to claim 1 read based on layering, which is characterized in that the module is set Set several visualizations, editable attribute.

3. the IC design system according to claim 2 read based on layering, which is characterized in that the module is set Respective pins are set, are connected the respective pins of disparate modules by connecting line.

4. the IC design system according to claim 3 read based on layering, which is characterized in that the integrated electricity Road design architecture further includes algorithm design cell, for being manually entered, editing procedure source code.

5. the IC design system according to claim 4 read based on layering, which is characterized in that the integrated electricity Road design architecture further includes code integrated unit, for by module, pin, connecting line source code, and source generation being manually entered Code fusion, forms the model with complete code structure.

6. the IC design system according to claim 4 or 5 read based on layering, which is characterized in that the source Code is the source code based on Verilog, VHDL or SystemC language.