CN105740159B - Zadoff-Chu sequence mapping method and device - Google Patents
Zadoff-Chu sequence mapping method and device Download PDFInfo
- Publication number
- CN105740159B CN105740159B CN201610031094.8A CN201610031094A CN105740159B CN 105740159 B CN105740159 B CN 105740159B CN 201610031094 A CN201610031094 A CN 201610031094A CN 105740159 B CN105740159 B CN 105740159B
- Authority
- CN
- China
- Prior art keywords
- zadoff
- chu sequence
- data
- mapping
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Complex Calculations (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
The embodiment of the invention provides a kind of Zadoff-Chu sequence mapping method and devices, it improves and is related to the application of Zadoff-Chu sequence in the prior art, generally the Zadoff-Chu sequence that length is p is stored entirely in memory, the larger problem in occupied space.This method is applied to Zadoff-Chu sequence mapping device, mapping ruler f (k) is preset in the Zadoff-Chu sequence mapping device, the described method includes: the Zadoff-Chu sequence mapping device obtains the index address k, 0≤k of each data in Zadoff-Chu sequence C (k) to be stored and the Zadoff-Chu sequence C (k) to be stored；For the index address k of each data, operation is carried out by the mapping ruler f (k), obtain mapping address n corresponding to the index address k of each data, n=f (k), meet C (k)=C (n)=C (f (k)), wherein, 0≤n≤k；Obtained Zadoff-Chu sequence C (n) is stored.Using this method, occupied space when Zadoff-Chu sequence storage can be significantly reduced, meet actual demand, application easy to spread.
Description
Technical field
The present invention relates to mapping techniques, in particular to a kind of Zadoff-Chu sequence mapping method and device.
Background technique
In the prior art, ZC (Zadoff-Chu) sequence has extraordinary autocorrelation and very low cross correlation, base
It in this performance, is often used to generate synchronization signal, as to time transport related to frequency.Such as: 3GPP long term evolution
(Long Term Evolution, LTE) system just uses ZC sequence as synchronous training sequence.
In general, ZC sequence can be divided into two major classes, and the first kind is generated by basic sequence by cyclic shift；Second class benefit
The characteristic of ZC sequence is remained as with the discrete Fourier transform (Discrete Fourier Transform, DFT) of ZC sequence, letter
The calculation amount for changing Physical Random Access Channel (Physical Random Access Channel, PRACH) signal, first by ZC sequence
Column pass through DFT transform, then do inverse fourier transform IFFT transformation and generate.
Inventor it has been investigated that, be related to the application of ZC sequence, be generally stored entirely in the ZC sequence that length is p
In memory, this storage mode needs the memory space of p unit, and occupied space is larger.
Summary of the invention
In view of this, the embodiment of the present invention is designed to provide a kind of Zadoff-Chu sequence mapping method and device,
It is related to the application of ZC sequence in the prior art to improve, generally the ZC sequence that length is p is stored entirely in memory, institute
The larger problem of occupied space.
To achieve the goals above, technical solution used in the embodiment of the present invention is as follows:
In a first aspect, being applied to Zadoff- the embodiment of the invention provides a kind of Zadoff-Chu sequence mapping method
Chu sequence mapping device is preset with mapping ruler f (k) in the Zadoff-Chu sequence mapping device, which comprises
The Zadoff-Chu sequence mapping device obtains Zadoff-Chu sequence C (k) to be stored and described wait store
The index address k, 0≤k of each data in Zadoff-Chu sequence C (k)；
For the index address k of each data, operation is carried out by the mapping ruler f (k), obtains the index of each data
Mapping address n, n=f (k) corresponding to the k of address meet C (k)=C (n)=C (f (k)), wherein 0≤n≤k；
Obtained Zadoff-Chu sequence C (n) is stored.
With reference to first aspect, the embodiment of the invention provides the first possible embodiments of first aspect, wherein institute
The Zadoff-Chu sequence C (n) that will be obtained is stated to store, comprising:
The corresponding relationship of each data and the mapping address n in Zadoff-Chu sequence C (n) is stored, it is described
On position pointed by mapping address n, each data in the Zadoff-Chu sequence C (n) are store.
With reference to first aspect, the embodiment of the invention provides second of possible embodiments of first aspect, wherein institute
The length for stating Zadoff-Chu sequence C (k) to be stored is p=s*m2, wherein s and m is odd prime number, and s is not equal to m；
The index address k for each data carries out operation by the mapping ruler f (k), obtains each data
Mapping address n, n=f (k) corresponding to index address k, comprising:
It is in Zadoff-Chu sequence C (k) to be stored described in p in length, for the index address k of each data,
Calculate the quadratic residue data n of each index address k, wherein n be with 2k+1 square quadratic residue it is one-to-one
Number, 0≤k≤p, using the quadratic residue data n as mapping address n corresponding to the index address k of each data.
The possible embodiment of second with reference to first aspect, the embodiment of the invention provides the third of first aspect
Possible embodiment, wherein the method also includes:
Obtain the request for the reading Zadoff-Chu sequence C (k) that user to be read sends；
Obtain the quadratic residue data n of the Zadoff-Chu sequence C (k)；
The Zadoff-Chu sequence C (k) is obtained according to the quadratic residue data n inverse operation；
The Zadoff-Chu sequence C (k) is sent to the user to be read.
Second aspect, the embodiment of the invention provides a kind of Zadoff-Chu sequence mapping devices, comprising:
Default unit, for presetting mapping ruler f (k)；
Obtaining unit, for obtaining Zadoff-Chu sequence C (k) to be stored and the Zadoff-Chu sequence C to be stored
(k) the index address k, 0≤k of each data in；
Arithmetic element, the index address k of each data for being obtained for the obtaining unit, by the default list
The preset mapping ruler f (k) of member carries out operation, obtains mapping address n, n=f corresponding to the index address k of each data
(k), meet C (k)=C (n)=C (f (k)), wherein 0≤n≤k；
Storage unit, the Zadoff-Chu sequence C (n) for obtaining the arithmetic element operation are stored.
In conjunction with second aspect, the embodiment of the invention provides the first possible embodiments of second aspect, wherein institute
Storage unit is stated to be specifically used for, by Zadoff-Chu sequence C (n) each data and the mapping address n corresponding relationship into
Row stores, and on position pointed by the mapping address n, stores each data in the Zadoff-Chu sequence C (n).
In conjunction with second aspect, the embodiment of the invention provides second of possible embodiments of second aspect, wherein institute
The length for stating Zadoff-Chu sequence C (k) to be stored is p=s*m2, wherein s and m is odd prime number, and s is not equal to m；
The arithmetic element is specifically used for, and is in Zadoff-Chu sequence C (k) to be stored described in p, for every in length
The index address k of one data calculates the quadratic residue data n of each index address k, wherein n be with 2k+1 square
Quadratic residue counts correspondingly, 0≤k≤p, using the quadratic residue data n as corresponding to the index address k of each data
Mapping address n.
In conjunction with second of possible embodiment of second aspect, the embodiment of the invention provides the third of second aspect
Possible embodiment, wherein the obtaining unit is also used to, and obtains the reading Zadoff-Chu that user to be read sends
The request of sequence C (k)；Obtain the quadratic residue data n of the Zadoff-Chu sequence C (k)；
The arithmetic element is also used to, and obtains the Zadoff-Chu sequence C according to the quadratic residue data n inverse operation
(k)；
Described device further includes transmission unit, and the transmission unit is used for, and the Zadoff-Chu sequence C (k) is sent
To the user to be read.
Method and apparatus provided in the embodiment of the present invention have abandoned the Zadoff- for being in the prior art p by length
Chu sequence is stored in memory, and needs the storage mode of the memory space of p unit, will be more by presetting mapping ruler f (k)
A index address k is mapped in the n of same mapping address so that the data in the Zadoff-Chu sequence C (n) through mapping be less than to
The data in Zadoff-Chu sequence C (k) are stored, thus the data length stored needed for effectively reducing, and then significantly reduce
The memory space occupied needed for Zadoff-Chu sequence.
Further, method and device provided in an embodiment of the present invention, it is easy to implement, have substantive distinguishing features outstanding and
Marked improvement is suitble to large-scale promotion application.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 shows a kind of flow diagram provided by the embodiment of the present invention；
Fig. 2 shows a kind of structural block diagrams of device provided by the embodiment of the present invention；
Fig. 3 shows a kind of structural block diagram of device provided by the embodiment of the present invention；
Fig. 4 shows a kind of structural block diagram of device provided by the embodiment of the present invention.
Specific embodiment
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can be arranged and be designed with a variety of different configurations herein.Cause
This, is not intended to limit claimed invention to the detailed description of the embodiment of the present invention provided in the accompanying drawings below
Range, but it is merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
Embodiment 1
Zadoff-Chu sequence (abbreviation ZC sequence) is a kind of nonbinary sequence of complex numbers of constant amplitude zero auto-correlation, tool
There is very good cross correlation, it is insensitive to frequency departure, thus have a good application prospect in a communications system.Example
Such as: it is 63 ZC sequence as main same that length is just used in Long Term Evolution (Long Term Evolution, LTE)
Walk signal.Since ZC sequence is a kind of sequence of complex numbers of nonbinary, thus it is generated and the complexity of detection is above generally
Binary sequence.Such as: length is the ZC sequence of odd number p is defined as:
The ZC sequence { C (k): 0≤k < p } for being p for a sequence length, k is the index address of ZC sequence, is less than p
Nonnegative integer.It is being related to the application of ZC sequence, such as: in application, working as in ZC sequence generator or ZC sequential detector
Given k, needs to obtain corresponding C (k).Way common now be by length be p ZC sequence be all stored in memory or
In memory, this storage mode needs the storage space of p unit, since the generation and detection of ZC sequence are complex, relates to
And into the calculating of ZC sequence, need individually to handle p data in ZC sequence, so that the operation needed is more, thus, this
Kind ZC sequence storage mode can also cause greatly to bear to subsequent processing while occupying larger memory space.
Based on the studies above, as shown in Figure 1, the embodiment of the invention provides a kind of Zadoff-Chu sequence mapping method,
Applied to Zadoff-Chu sequence mapping device, it is preset with mapping ruler f (k) in the Zadoff-Chu sequence mapping device,
The described method includes:
Step S100: the Zadoff-Chu sequence mapping device obtains Zadoff-Chu sequence C (k) to be stored and described
The index address k, 0≤k of each data in Zadoff-Chu sequence C (k) to be stored；
Step S101: for the index address k of each data, operation is carried out by the mapping ruler f (k), is obtained each
Mapping address n, n=f (k) corresponding to the index address k of data, meet C (k)=C (n)=C (f (k)), wherein and 0≤n≤
k；
Wherein, there are many selections of mapping ruler f (k), as long as the longer Zadoff-Chu to be stored that can be p by length
Sequence C (k) is mapped as the shorter Zadoff-Chu sequence C (n), 0≤n≤k that length is n.In general, it is different to
It is different to store mapping ruler f (k) corresponding to Zadoff-Chu sequence C (k).
Step S102: obtained Zadoff-Chu sequence C (n) is stored.
Wherein, the Zadoff-Chu sequence C (n) that will be obtained is stored, comprising: by Zadoff-Chu sequence C (n)
In each data and the corresponding relationship of the mapping address n stored, on position pointed by the mapping address n, storage
Each data in the Zadoff-Chu sequence C (n).
Based on above method step, if the length of Zadoff-Chu sequence to be stored is p=s*m2, wherein s and m are
Odd prime number, and s is not equal to m, such as: the ZC sequence that the length used in forth generation mobile communication is 63 meets this form,
63=7*32, p=63, s=7, m=3, wherein 7 and 3 be all odd prime number.One of mapping is provided in the embodiment of the present invention
Scheme:
It is Zadoff-Chu sequence C to be stored described in p in length using quadratic residue formula as mapping ruler f (k)
(k) in, for the index address k of each data, calculate the quadratic residue data n of each index address k, wherein n be with
2k+1 square quadratic residue count correspondingly, 0≤k≤p, using the quadratic residue data n as the index of each data
Mapping address n corresponding to the k of address.Such as: length p be 63 Zadoff-Chu sequence C (k) in, k=0,1,2,3,4 ...,
60,61,62, in equivalent sequence C (n), n=0,1,2,3,4,5,6,7,8,9,10,14,15,17,23,24.That is: length is
The length of the equivalent sequence C (n) of 63 original Zadoff-Chu sequence C (k) is 16, far smaller than original Zadoff-Chu sequence
The length of C (k), thus, by storing the equivalent sequence C (n) of Zadoff-Chu sequence C (k), storage can be substantially reduced and opened
Pin.
By above method step, a corresponding mapping address n can be obtained for each index address k, meet C
(k)=C (n)=C (f (k)).This calculation method is a kind of many-to-one mapping, i.e., multiple index address k may map to together
One mapping address n, enabling the possibility value of all n is set Sn.It can guarantee when k is the nonnegative integer less than p, member in Sn
The number of quadratic residue (including 0) in residue class of the number of element equal to p.Since the number of the quadratic residue of p is much smaller than p, institute
In needing to store application of the length for the ZC sequence C (k) of p, it is only necessary to the equivalent sequence C (n) that length is Lp is stored,
To which storage overhead be greatly decreased.
Will Zadoff-Chu sequence C (k) be stored index address k press mapping ruler f (k) operation, obtain equivalent sequence
It arranges C (n), in the case that equivalent sequence C (n) is stored, in the reading Zadoff- for obtaining user's transmission to be read
When the request of Chu sequence C (k), the mapping address n of the Zadoff-Chu sequence is first obtained；According to the quadratic residue
Data n inverse operation obtains the Zadoff-Chu sequence C (k)；The Zadoff-Chu sequence C (k) is sent to described continue
Take family.
Method provided in the embodiment of the present invention has abandoned the Zadoff-Chu sequence for being in the prior art p by length
It is stored in memory, needs the storage mode of the memory space of p unit, by presetting mapping ruler f (k), by multiple indexes
Address k is mapped in the n of same mapping address, so that the data in the Zadoff-Chu sequence C (n) through mapping are less than wait store
Data in Zadoff-Chu sequence C (k), thus the data length stored needed for effectively reducing, and then significantly reduce
The memory space occupied needed for Zadoff-Chu sequence.
Based on above method step, the embodiment of the invention provides realization principles:
According to the definition of ZC sequence:
Cu(k)=e-jπuk(k+1)/p, wherein, p is odd number to k=0 ... p-1, and u and p are relatively prime.
Simply derived available, k (k+1) ≡ n (n+1) is Cu(n)=Cu(k) necessary and sufficient condition, it was demonstrated that mode is such as
Under:
If k (k+1) ≡ n (n+1), and u and p would be relatively prime, then have uk (k+1) ≡ un (n+1), i.e. uk (k+1)-un (n+1)
≡0；
Again because uk (k+1)-un (n+1) is even number, and p is odd number, then has:
Uk (k+1)-un (n+1) ≡ 0, then Cu(n)=Cu(k)。
(meet under the application scenarios of most of ZC sequences) when 4 and p relatively prime, available:
(2k+1)2≡(2n+1)2
It follows that if 2k+1 and 2n+1 belong to the quadratic residue system of the same mould p, Cu(n)=Cu(k)
According to drawer principle, it is known that, Cu(k) number of independent element in, i.e. the number of n is no more than after n=f (k) mapping
The number of the quadratic residue of mould p.
When listing p=63 in the embodiment of the present invention, quadratic residue, k, n and C29(k), wherein the definition of quadratic residue is
(2k+1)2
Above-mentioned listed method for solving is in p=sm2In the case where solve
n(n+1)≡k(k+1)。
Embodiment 2
As shown in Fig. 2, the embodiment of the invention provides a kind of Zadoff-Chu sequence mapping devices, comprising: default unit
200, for presetting mapping ruler f (k)；Obtaining unit 201, for obtain Zadoff-Chu sequence C (k) to be stored and it is described to
Store the index address k, 0≤k of each data in Zadoff-Chu sequence C (k)；Arithmetic element 202, for single for the acquisition
The index address k for each data that member 201 obtains is carried out by the default preset mapping ruler f (k) of unit 200
Operation obtains mapping address n, n=f (k) corresponding to the index address k of each data, meets C (k)=C (n)=C (f (k)),
Wherein, 0≤n≤k；Storage unit 203, Zadoff-Chu sequence C (n) for obtaining 202 operation of arithmetic element into
Row storage.
Wherein, the storage unit 203 is specifically used for, by each data and the mapping in Zadoff-Chu sequence C (n)
The corresponding relationship of address n is stored, and on position pointed by the mapping address n, stores the Zadoff-Chu sequence C
(n) each data in.
The length of Zadoff-Chu sequence C (k) to be stored is p=s*m2, wherein s and m is odd prime number, and s is not equal to
m；Arithmetic element 202 is specifically used for, and is in Zadoff-Chu sequence C (k) to be stored described in p, for each number in length
According to index address k, calculate the quadratic residue data n of each index address k, wherein n be with 2k+1 square it is secondary surplus
Remaining one-to-one number, 0≤k≤p, as mapping corresponding to the index address k of each data using the quadratic residue data n
Location n.
Corresponding with above-mentioned storing process, when carrying out reading data, obtaining unit 201 is also used to, and acquisition, which is continued, takes
The request for the reading Zadoff-Chu sequence C (k) that family is sent；Obtain the described secondary of the Zadoff-Chu sequence C (k)
Remaining data n；Arithmetic element 202 is also used to, and obtains the Zadoff-Chu sequence according to the quadratic residue data n inverse operation
C(k)；As shown in figure 3, described device further includes transmission unit 204, the transmission unit 204 is used for, by the Zadoff-Chu
Sequence C (k) is sent to the user to be read.
The technical effect and preceding method embodiment phase of device provided by the embodiment of the present invention, realization principle and generation
Together, to briefly describe, Installation practice part does not refer to place, can refer to corresponding contents in preceding method embodiment.
As shown in figure 4, the embodiment of the invention also provides a kind of structural schematic diagram of Zadoff-Chu sequence mapping device,
It include: processor 400, memory 404, bus 402 and communication interface 403, the processor 400, communication interface 403 and storage
Device 404 is connected by bus 402.
Wherein, memory 404 may include high-speed random access memory (RAM:Random Access Memory),
It may further include non-labile memory (non-volatile memory), for example, at least a magnetic disk storage.By extremely
A few communication interface 403 (can be wired or wireless) is realized logical between the system network element and at least one other network element
Letter connection, can be used internet, wide area network, local network, Metropolitan Area Network (MAN) etc..
Processor 400 is used to execute the executable module in memory 404, such as computer program 401；Processor 400
Data flow is received by communication interface 403；
Bus 402 can be isa bus, pci bus or eisa bus etc..The bus can be divided into address bus, number
According to bus, control bus etc..Only to be indicated with a four-headed arrow in figure, it is not intended that an only bus convenient for indicating
Or a type of bus.
Wherein, memory 404 is for storing program 401, and the processor 400 executes institute after receiving and executing instruction
Program 401 is stated, method performed by the device that the process that aforementioned any embodiment of the embodiment of the present invention discloses defines can be applied
It is realized in processor 400, or by processor 400.
In the concrete realization, program 401 may include program code, said program code include computer operation instruction and
Algorithm etc.；
Processor 400 may be a kind of IC chip, the processing capacity with signal.It is above-mentioned during realization
Each step of method can be completed by the integrated logic circuit of the hardware in processor 400 or the instruction of software form.On
The processor 400 stated can be general processor, including central processing unit (Central Processing Unit, abbreviation
CPU), network processing unit (Network Processor, abbreviation NP) etc.；It can also be digital signal processor (DSP), dedicated
Integrated circuit (ASIC), ready-made programmable gate array (FPGA) either other programmable logic device, discrete gate or transistor
Logical device, discrete hardware components.It may be implemented or execute disclosed each method, step and the logic in the embodiment of the present invention
Block diagram.General processor can be microprocessor or the processor is also possible to any conventional processor etc..In conjunction with this hair
The step of method disclosed in bright embodiment, can be embodied directly in hardware decoding processor and execute completion, or be handled with decoding
Hardware and software module combination in device execute completion.Software module can be located at random access memory, flash memory, read-only memory,
In the storage medium of this fields such as programmable read only memory or electrically erasable programmable memory, register maturation.This is deposited
Storage media is located at memory 404, and processor 400 reads the information in memory 404, and the step of the above method is completed in conjunction with its hardware
Suddenly.
The computer program product in device, the meter including storing program code are carried out provided by the embodiment of the present invention
Calculation machine readable storage medium storing program for executing, the instruction that said program code includes can be used for executing previous methods method as described in the examples,
Specific implementation can be found in embodiment of the method, and details are not described herein.
It is apparent to those skilled in the art that for convenience and simplicity of description, the device of foregoing description
It with the specific work process of unit, can refer to corresponding processes in the foregoing method embodiment, details are not described herein.
Unless specifically stated otherwise, the opposite step of the component and step that otherwise illustrate in these embodiments, digital table
It is not limit the scope of the invention up to formula and numerical value.
In all examples being illustrated and described herein, any occurrence should be construed as merely illustratively, without
It is as limitation, therefore, other examples of exemplary embodiment can have different values.
In several embodiments provided herein, it should be understood that disclosed device and method can pass through it
Its mode is realized.The apparatus embodiments described above are merely exemplary, for example, the flow chart and block diagram in attached drawing are aobvious
The device of multiple embodiments according to the present invention, architectural framework in the cards, the function of method and computer program product are shown
It can and operate.In this regard, each box in flowchart or block diagram can represent one of a module, section or code
Point, a part of the module, section or code includes one or more for implementing the specified logical function executable
Instruction.It should also be noted that in some implementations as replacements, function marked in the box can also be to be different from attached drawing
The sequence marked occurs.For example, two continuous boxes can actually be basically executed in parallel, they sometimes can also be by
Opposite sequence executes, and this depends on the function involved.It is also noted that each box in block diagram and or flow chart,
And the combination of the box in block diagram and or flow chart, hardware can be based on the defined function of execution or the dedicated of movement
System realize, or can realize using a combination of dedicated hardware and computer instructions.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.
It, can be with if the function is realized in the form of SFU software functional unit and when sold or used as an independent product
It is stored in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially in other words
The part of the part that contributes to existing technology or the technical solution can be embodied in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be a
People's computer, server or network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
And storage medium above-mentioned includes: that USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited
The various media that can store program code such as reservoir (RAM, Random Access Memory), magnetic or disk.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. a kind of Zadoff-Chu sequence mapping method, which is characterized in that it is applied to Zadoff-Chu sequence mapping device, it is described
Mapping ruler f (k) is preset in Zadoff-Chu sequence mapping device, which comprises
The Zadoff-Chu sequence mapping device obtains Zadoff-Chu sequence C (k) to be stored and the Zadoff- to be stored
The index address k, 0≤k of each data in Chu sequence C (k)；
For the index address k of each data, operation is carried out by the mapping ruler f (k), obtains the index address of each data
Mapping address n, n=f (k) corresponding to k meet C (k)=C (n)=C (f (k)), wherein 0≤n≤k；
Obtained Zadoff-Chu sequence C (n) is stored；
The length of the Zadoff-Chu sequence C (k) to be stored is p=s*m2, wherein s and m is odd prime number, and s is not equal to
m；
The index address k for each data carries out operation by the mapping ruler f (k), obtains the index of each data
Mapping address n, n=f (k) corresponding to the k of address, comprising:
It is, for the index address k of each data, to be calculated in Zadoff-Chu sequence C (k) to be stored described in p in length
The quadratic residue data n of each index address k, wherein n be with 2k+1 square quadratic residue count correspondingly, 0≤
K≤p, using the quadratic residue data n as mapping address n corresponding to the index address k of each data.
2. Zadoff-Chu sequence mapping method according to claim 1, which is characterized in that described to obtain
Zadoff-Chu sequence C (n) is stored, comprising:
The corresponding relationship of each data and the mapping address n in Zadoff-Chu sequence C (n) is stored, the mapping
On position pointed by the n of address, each data in the Zadoff-Chu sequence C (n) are store.
3. Zadoff-Chu sequence mapping method according to claim 1, which is characterized in that the method also includes:
Obtain the request for the reading Zadoff-Chu sequence C (k) that user to be read sends；
Obtain the quadratic residue data n of the Zadoff-Chu sequence C (k)；
The Zadoff-Chu sequence C (k) is obtained according to the quadratic residue data n inverse operation；
The Zadoff-Chu sequence C (k) is sent to the user to be read.
4. a kind of Zadoff-Chu sequence mapping device characterized by comprising
Default unit, for presetting mapping ruler f (k)；
Obtaining unit, for obtaining in Zadoff-Chu sequence C (k) to be stored and the Zadoff-Chu sequence C (k) to be stored
The index address k, 0≤k of each data；
Arithmetic element, the index address k of each data for obtaining for the obtaining unit are pre- by the default unit
If the mapping ruler f (k) carry out operation, obtain mapping address n, n=f (k) corresponding to the index address k of each data,
Meet C (k)=C (n)=C (f (k)), wherein 0≤n≤k；
Storage unit, the Zadoff-Chu sequence C (n) for obtaining the arithmetic element operation are stored；
The length of the Zadoff-Chu sequence C (k) to be stored is p=s*m2, wherein s and m is odd prime number, and s is not equal to
m；
The arithmetic element is specifically used for, and is in Zadoff-Chu sequence C (k) to be stored described in p, for each in length
The index address k of data calculates the quadratic residue data n of each index address k, wherein n be with 2k+1 square it is secondary
Remaining one-to-one number, 0≤k≤p, using the quadratic residue data n as mapping corresponding to the index address k of each data
Address n.
5. Zadoff-Chu sequence mapping device according to claim 4, which is characterized in that the storage unit is specifically used
In, the corresponding relationship of each data and the mapping address n in Zadoff-Chu sequence C (n) is stored, the mapping
On position pointed by the n of location, each data in the Zadoff-Chu sequence C (n) are store.
6. Zadoff-Chu sequence mapping device according to claim 4, which is characterized in that the obtaining unit is also used
In obtaining the request for the reading Zadoff-Chu sequence C (k) that user to be read sends；Obtain the Zadoff-Chu sequence
Arrange the quadratic residue data n of C (k)；
The arithmetic element is also used to, and obtains the Zadoff-Chu sequence C (k) according to the quadratic residue data n inverse operation；
Described device further includes transmission unit, and the transmission unit is used for, and the Zadoff-Chu sequence C (k) is sent to institute
State user to be read.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610031094.8A CN105740159B (en) | 2016-01-18 | 2016-01-18 | Zadoff-Chu sequence mapping method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610031094.8A CN105740159B (en) | 2016-01-18 | 2016-01-18 | Zadoff-Chu sequence mapping method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105740159A CN105740159A (en) | 2016-07-06 |
| CN105740159B true CN105740159B (en) | 2019-02-12 |
Family
ID=56247372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610031094.8A Active CN105740159B (en) | 2016-01-18 | 2016-01-18 | Zadoff-Chu sequence mapping method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105740159B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105191367A (en) * | 2013-05-07 | 2015-12-23 | Lg电子株式会社 | Method for determining activation of ISR capability |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011137408A2 (en) * | 2010-04-30 | 2011-11-03 | Interdigital Patent Holdings, Inc. | Determination of carriers and multiplexing for uplink control information transmission |
-
2016
- 2016-01-18 CN CN201610031094.8A patent/CN105740159B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105191367A (en) * | 2013-05-07 | 2015-12-23 | Lg电子株式会社 | Method for determining activation of ISR capability |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105740159A (en) | 2016-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109145080B (en) | Text fingerprint obtaining method and device | |
| Tian | Symmetry, demand types and outer bounds in caching systems | |
| CN106406830B (en) | Quasi-periodic signal processing method and device and computer readable storage medium | |
| CN103309893A (en) | Character string comparing method and device | |
| CN107784073B (en) | Data query method for local cache, storage medium and server | |
| WO2019057097A1 (en) | Convolution operation method and apparatus, computer device, and computer-readable storage medium | |
| KR20160034858A (en) | File scanning method and apparatus | |
| CN110019205A (en) | A kind of data storage, restoring method, device and computer equipment | |
| US9639566B2 (en) | Method, apparatus and computer program product for improved storage of key-value pairs | |
| US10095630B2 (en) | Sequential access to page metadata stored in a multi-level page table | |
| CN105740159B (en) | Zadoff-Chu sequence mapping method and device | |
| CN109800074A (en) | Task data concurrently executes method, apparatus and electronic equipment | |
| CN106776614A (en) | The display methods and device of sharing platform | |
| CN104008116A (en) | File synchronization method and electronic device | |
| CN111178513B (en) | Convolution implementation method and device of neural network and terminal equipment | |
| CN104506271A (en) | Method and device for generating ZC (Zadoff-Chu) sequence | |
| CN105634999B (en) | A kind of aging method and device of Media Access Control address | |
| US20190087451A1 (en) | Database identifier generation in transaction processing systems | |
| CN110083602A (en) | A kind of method and device of data storage and data processing based on hive table | |
| CN108845844A (en) | A kind of state transition method and device | |
| CN109658094A (en) | Random walk, random walk method, apparatus and equipment based on cluster | |
| CN106100790A (en) | A kind of data transmission method and system | |
| CN111026827A (en) | Data service method and device for soil erosion factors and electronic equipment | |
| CN107341136B (en) | Method and device for generating sequence index number and storage medium | |
| CN107645541B (en) | Data storage method and device and server |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210208 Address after: 310000 Room 601, 6th floor, building B, 482 Qianmo Road, Xixing street, Binjiang District, Hangzhou City, Zhejiang Province Patentee after: WEICHENG INTELLIGENT POWER TECHNOLOGY (HANGZHOU) Co.,Ltd. Address before: 650118 main building of hi tech Information Center, No.398, 2nd Ring West Road, Kunming City, Yunnan Province Patentee before: YUNNAN LEIAOMING TECHNOLOGY Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Zadoff Chu Sequence Mapping Method and Device Effective date of registration: 20230720 Granted publication date: 20190212 Pledgee: Hangzhou Gaoxin Financing Guarantee Co.,Ltd. Pledgor: WEICHENG INTELLIGENT POWER TECHNOLOGY (HANGZHOU) CO.,LTD. Registration number: Y2023330001524 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right |