CN105718416A - Method for upgrading configuration file of FPGA (Field Programmable Gate Array) and upgrading device - Google Patents
Method for upgrading configuration file of FPGA (Field Programmable Gate Array) and upgrading device Download PDFInfo
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- CN105718416A CN105718416A CN201610038030.0A CN201610038030A CN105718416A CN 105718416 A CN105718416 A CN 105718416A CN 201610038030 A CN201610038030 A CN 201610038030A CN 105718416 A CN105718416 A CN 105718416A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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- General Engineering & Computer Science (AREA)
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Abstract
The invention relates to the technical field of electronics, in particular to a method for upgrading a configuration file of an FPGA (Field Programmable Gate Array) and an upgrading device, and solves the problem that the FPGA occupies an SPI (Serial Peripheral Interface) bus all the time when the configuration file loaded in the FPGA is corrupted, so that a user cannot upgrade the configuration file through the SPI bus. According to the method and apparatus, after a microcontroller determines that the configuration file of the FPGA needs to be upgraded, an SPI bus between the microcontroller and a configuration chip is conducted and the SPI bus between the FPGA and the configuration chip is disconnected; and after the microcontroller sends the configuration file to the configuration chip, the SPI bus between the microcontroller and the configuration chip is disconnected and the SPI bus between the FPGA and the configuration chip is conducted. The microcontroller can disconnect the SPI bus between the FPGA and the configuration chip, so that the SPI bus can be prevented from being occupied by the FPGA when the configuration file is upgraded.
Description
Technical field
The present invention relates to electronic technology field, particularly to the method for configuration file and the updating apparatus of a kind of FPGA that upgrades.
Background technology
FPGA (Field-ProgrammableGateArray, field programmable gate array) is the control chip of a kind of main flow, has stable performance, the advantage that integrated level is high.The configuration file that the function that FPGA can complete is write by user determines.
After user writes configuration file on computers, send configuration file to microprocessor by USB interface.Configuration file is entered to configure in chip by microprocessor by the total line writing of SPI (SerialPeripheralInterface, Serial Peripheral Interface (SPI)).FPGA loads the configuration file in configuration chip again by spi bus.
Owing to instrument and equipment being commonly present electromagnetic interference, cause microprocessor to configuration chip in write configuration file it is possible that damage phenomenon.When FPGA is arranged in, by spi bus loading, the file that the configuration file configuring chip is damage, FPGA can take always and configure the spi bus that chip is connected, and causes that user cannot pass through spi bus upgrading and configure the configuration file in chip.
Summary of the invention
The present invention provides method and the updating apparatus of the configuration file of a kind of FPGA that upgrades, in order to solve in prior art when FPGA by spi bus load configuration chip in configuration file be damage time, FPGA can take always and configure the spi bus that chip is connected, and causes the problem that user cannot pass through the configuration file in spi bus upgrading configuration chip.
The embodiment of the present invention provides the method for the configuration file of a kind of on-site programmable gate array FPGA of upgrading, including:
Microcontroller, after the configuration file determining FPGA needs upgrading, controls serial peripheral equipment interface SPI bus switch and turns on the spi bus between described microcontroller and configuration chip, and disconnect the spi bus between described FPGA and described configuration chip；
After the configuration file that upgrading is used by described microcontroller is sent to described configuration chip by the spi bus between described microcontroller and configuration chip, control described spi bus and switch off the spi bus between described microcontroller and described configuration chip, and turn on the spi bus between described FPGA and described configuration chip.
Owing to embodiment of the present invention microcontroller is when needing the configuration file of FPGA is upgraded, the spi bus between FPGA and configuration chip can be switched off by control spi bus, therefore spi bus it is possible to prevent to be taken by FPGA, and turning on the spi bus between FPGA and described configuration chip, therefore configuration file can be upgraded by microcontroller by spi bus.
Optionally, described microcontroller determines that the configuration file of described FPGA needs upgrading, including:
Described microprocessor is receiving after the upgrade command of control equipment, it is determined that the configuration file of described FPGA needs upgrading.
Optionally, the configuration file that upgrading is used by described microcontroller also includes before being sent to described configuration chip by conducting spi bus:
Described microcontroller is receiving from after controlling the upgrade command of equipment, receives from the configuration file controlling equipment, and using configuration file that the described configuration file that receives uses as upgrading.
Optionally, the configuration file that upgrading is used by described microcontroller also includes after being sent to described configuration chip by the spi bus between described microcontroller and configuration chip:
Described microcontroller judges that whether described FPGA loading configuration file is failed, and loading result is sent to described control equipment.
Microcontroller in the embodiment of the present invention may determine that FPGA whether can the configuration file that uses of success loading upgrading, therefore can make the configuration file that the more effective loading of FPGA is correct.
Optionally, according to following manner, described microprocessor judges that whether described FPGA loading configuration file is failed:
Described microprocessor is after described FPGA loads described configuration file, it may be judged whether receive the loading pass signal of described FPGA feedback within the setting time；
If it is, determine the success of described FPGA loading configuration file；
Otherwise, it determines the failure of described FPGA loading configuration file.
Embodiment of the present invention microcontroller may determine that whether FPGA loading configuration file is successful, and then control spi bus is used for upgrading or for loading configuration file more accurately.
The embodiment of the present invention provides a kind of updating apparatus, and including microprocessor, spi bus controls switch, FPGA and configuration chip, and described microprocessor is used for:
After the configuration file determining described FPGA needs upgrading, control upgraded module described in spi bus switch conduction and the spi bus between configuration chip, and disconnect the spi bus between described FPGA and described configuration chip；
After configuration file upgrading used is sent to described configuration chip by the spi bus between described upgraded module and configuration chip, control described spi bus and switch off the spi bus between described upgraded module and described configuration chip, and turn on the spi bus between described FPGA and described configuration chip.
Optionally, described microcontroller specifically for:
Receiving after the upgrade command of control equipment, it is determined that the configuration file of described FPGA needs upgrading；Or
After the failure of described FPGA loading configuration file, it is determined that the configuration file of described FPGA needs upgrading.
Optionally, described microcontroller is additionally operable to:
Receiving from after controlling the upgrade command of equipment, reducing the loading clock frequency loaded in failed configuration file, and using the configuration file as upgrading use of the configuration file after reducing.
Optionally, described microcontroller is additionally operable to:
Judge that whether described FPGA loading configuration file is failed, and loading result is sent to described control equipment.
Optionally, described microcontroller is additionally operable to, and judges that whether described FPGA loading configuration file is failed according to following manner:
After described FPGA loads described configuration file, it may be judged whether receive the loading pass signal of described FPGA feedback within the setting time:
If it is, determine the success of described FPGA loading configuration file；
Otherwise, it determines the failure of described FPGA loading configuration file.
Accompanying drawing explanation
Fig. 1 is the method flow schematic diagram of the configuration file of a kind of FPGA that upgrades of the embodiment of the present invention；
Fig. 2 is the overall flow figure of the method for the configuration file of a kind of FPGA that upgrades of the embodiment of the present invention；
Fig. 3 is the structural representation of a kind of updating apparatus of the embodiment of the present invention；
Fig. 4 is the system structure schematic diagram of the configuration file of embodiment of the present invention upgrading FPGA.
Detailed description of the invention
The embodiment of the present invention provides the method for the configuration file of a kind of FPGA that upgrades, in the method, microcontroller is after the configuration file determining FPGA needs upgrading, control microcontroller described in spi bus switch conduction and the serial peripheral equipment interface SPI bus between configuration chip, and disconnect the spi bus between described FPGA and described configuration chip；After the configuration file that upgrading is used by described microcontroller is sent to described configuration chip by the spi bus between described microcontroller and configuration chip, control described spi bus and switch off the spi bus between described microcontroller and described configuration chip, and turn on the spi bus between described FPGA and described configuration chip.Owing to embodiment of the present invention microcontroller is when needing the configuration file of FPGA is upgraded, the spi bus between FPGA and configuration chip can be switched off by control spi bus, therefore spi bus it is possible to prevent to be taken by FPGA, and turning on the spi bus between FPGA and described configuration chip, therefore configuration file can be upgraded by microcontroller by spi bus.
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is some embodiments of the present application, rather than whole embodiments.Based on the embodiment in the application, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of the application protection.
As it is shown in figure 1, the method that the embodiment of the present invention provides the configuration file of a kind of FPGA that upgrades, including:
Step 101, microcontroller, after the configuration file determining FPGA needs upgrading, controls microcontroller described in spi bus switch conduction and the spi bus between configuration chip, and disconnects the spi bus between described FPGA and described configuration chip；
Step 102, after the configuration file that upgrading is used by described microcontroller is sent to described configuration chip by the spi bus between described microcontroller and configuration chip, control described spi bus and switch off the spi bus between described microcontroller and described configuration chip, and turn on the spi bus between described FPGA and described configuration chip.
The microcontroller of the embodiment of the present invention can be the processor chips having and controlling function and multiple I/O pin resource, for instance single-chip microcomputer.
The configuration chip of the embodiment of the present invention can be can repeatedly program and storage chip that power failure data is not lost, for instance E2PROM chip, Flash (flash memory) chip.
The embodiment of the present invention includes microcontroller, and spi bus switchs, and configures chip and FPGA.Microcontroller can pass through to control spi bus switch controlling signal and control the conducting situation of spi bus.Microcontroller can control spi bus and be under two kinds of mode of operations:
One, loading mode
Under loading mode, FPGA uses spi bus loading configuration file from configuration chip.In such a mode, microprocessor controls spi bus switchs, and makes the spi bus conducting between FPGA and configuration chip, and the serial peripheral equipment interface SPI bus between microcontroller and configuration chip disconnects.FPGA can pass through spi bus loading configuration file from configuration chip.
In practical application, spi bus switch can have one and control pin, when microcontroller is to when controlling pin output low level or high level, the spi bus conducting between FPGA and configuration chip, the serial peripheral equipment interface SPI bus between microcontroller and configuration chip disconnects.
Two, upgrade mode
Under upgrade mode, microcontroller utilizes the configuration file that spi bus uses to programming upgrading in configuration chip.In such a mode, microprocessor controls spi bus switchs, and makes the spi bus between FPGA and configuration chip disconnect, the serial peripheral equipment interface SPI bus conducting between microcontroller and configuration chip.The configuration file that upgrading uses can be entered to configure chip by user by the spi bus programming between microcontroller and configuration chip.Under upgrade mode,
Embodiment of the present invention microprocessor is receiving from the upgrade command controlling equipment, controls spi bus and enters upgrade mode.Namely control equipment (such as computer) and actively apply for upgrading configuration, send upgrade command to microcontroller.Microcontroller can pass through usb bus and receive, from controlling equipment, the configuration file that upgrading uses, and the configuration file that upgrading is used sends configuration chip to by spi bus.After microcontroller determines that configuration file has successfully sent configuration chip to, it is possible to adjust spi bus and return to loading mode, and control, by reset line in Fig. 3, the configuration file that FPGA loading upgrading uses.
After the configuration file that microcontroller uses to configuration chip write upgrading, it is possible to make, by two ways, the configuration file that FPGA loading upgrading uses:
(1), after FPGA power-off, it is powered back up；
Spi bus can be passed through when FPGA powers on and load the configuration file that the upgrading in configuration chip uses.
(2) microcontroller sends reset signal to described FPGA.
Microcontroller can send low level reset signal by reset alignment FPGA and control FPGA reset, and FPGA can load the configuration file that the upgrading in configuration chip uses when resetting.
After FPGA loads the configuration file that the upgrading in configuration chip uses, embodiment of the present invention microcontroller can also judge that whether FPGA loading configuration file is successful.Also having one between FPGA and microcontroller and load pass signal line, these holding wire default conditions are low level.When FPGA loads successfully, a rising edge can be exported to this holding wire.Microprocessor can after described FPGA loads described configuration file, it may be judged whether receive the loading pass signal of described FPGA feedback within the setting time；
If it is, determine the success of described FPGA loading configuration file；
Otherwise, it determines the failure of described FPGA loading configuration file.
User can set that a set time (such as 1s), and after controlling FPGA actively loading configuration file, detection loads pass signal line, if recognizing high level, then loads successfully；If not recognizing, then load failure.If loading unsuccessfully.After completing judgement, microcontroller will determine that result is sent to control equipment.
As in figure 2 it is shown, the embodiment of the present invention provides the overall flow of the configuration file of a kind of FPGA that upgrades, including:
Step 201, microcontroller receives the instruction controlling device upgrade configuration file, and receives, from controlling equipment, the configuration file that upgrading uses；
Step 202, microprocessor controls spi bus switchs, and makes the spi bus between FPGA and configuration chip disconnect, the spi bus conducting between microcontroller and configuration chip；
Step 203, the configuration file that upgrading is used by microcontroller is sent to configuration chip by the serial peripheral equipment interface SPI bus between microcontroller and configuration chip；
Step 204, microprocessor controls spi bus switchs, and makes the spi bus conducting between FPGA and configuration chip, and the spi bus between microcontroller and configuration chip disconnects；
Step 205, the configuration file that microprocessor controls FPGA loading upgrading uses, and determine that whether the configuration file that FPGA loading upgrading uses is successful；
Step 206, the result of the result success or failure of the configuration file that FPGA loading upgrading is used by microcontroller is sent to control equipment.
Based on same inventive concept, the embodiment of the present application additionally provides a kind of updating apparatus, owing to the method that this equipment is corresponding is the method in the embodiment of the present application, and the principle that equipment solves problem is similar to the method for the embodiment of the present application, therefore the enforcement of this equipment may refer to the enforcement of method, repeats part and repeats no more.
As it is shown on figure 3, the embodiment of the present invention provides a kind of updating apparatus, including microcontroller 301, FPGA302 and configuration chip 303, spi bus switch 304, described microcontroller 301 is used for:
After the configuration file determining described FPGA needs upgrading, control upgraded module described in spi bus switch conduction and the spi bus between configuration chip, and disconnect the spi bus between described FPGA and described configuration chip；
After configuration file upgrading used is sent to described configuration chip by the spi bus between described upgraded module and configuration chip, control described spi bus and switch off the spi bus between described upgraded module and described configuration chip, and turn on the spi bus between described FPGA and described configuration chip.
Optionally, described microcontroller 301 specifically for:
Receiving after the upgrade command of control equipment, it is determined that the configuration file of described FPGA needs upgrading；Or
After the failure of described FPGA loading configuration file, it is determined that the configuration file of described FPGA needs upgrading.
Optionally, described microcontroller 301 is additionally operable to:
Receiving from after controlling the upgrade command of equipment, receiving from the configuration file controlling equipment, and using configuration file that the described configuration file that receives uses as upgrading.
Optionally, described microcontroller 301 is additionally operable to:
Judge that whether described FPGA loading configuration file is failed, and loading result is sent to described control equipment.
Optionally, described microcontroller 301 is additionally operable to, and judges that whether described FPGA loading configuration file is failed according to following manner:
After described FPGA loads described configuration file, it may be judged whether receive the loading pass signal of described FPGA feedback within the setting time:
If it is, determine the success of described FPGA loading configuration file；
Otherwise, it determines the failure of described FPGA loading configuration file.
As shown in Figure 4, the embodiment of the present invention provides the system of the configuration file of a kind of FPGA that upgrades, including control equipment 10 and updating apparatus 20.
Control equipment 10 by being connected wirelessly with between updating apparatus 20, such as bluetooth etc.；Can also be connected by wired mode, such as USB interface or other can transmit the interface of data.
Control equipment 10 sends request upgrade command to embodiment of the present invention updating apparatus 20, then retransmits the configuration file that upgrading uses；Or request upgrade command comprises the configuration file that upgrading uses.
Accordingly, what the microcontroller in embodiment of the present invention updating apparatus 20 sent sends request upgrade command and the configuration file of upgrading use.
Wherein, control equipment 10 can be the equipment that can write configuration file to FPGA, for instance computer.Updating apparatus can be the equipment of any use fpga chip the configuration file that can change FPGA.Such as, flash programmable device (off-line fever writes).
It can be seen from the above: in the method for the embodiment of the present invention, microcontroller is after the configuration file determining FPGA needs upgrading, control serial peripheral equipment interface SPI bus switch and turn on the spi bus between described microcontroller and configuration chip, and disconnect the spi bus between described FPGA and described configuration chip；After the configuration file that upgrading is used by described microcontroller is sent to described configuration chip by the spi bus between described microcontroller and configuration chip, control described spi bus and switch off the spi bus between described microcontroller and described configuration chip, and turn on the spi bus between described FPGA and described configuration chip.Owing to embodiment of the present invention microcontroller is when needing the configuration file of FPGA is upgraded, the spi bus between FPGA and configuration chip can be switched off by control spi bus, therefore spi bus it is possible to prevent to be taken by FPGA, and turning on the spi bus between FPGA and described configuration chip, therefore configuration file can be upgraded by microcontroller by spi bus.
Obviously, the present invention can be carried out various change and modification without deviating from the spirit and scope of the present invention by those skilled in the art.So, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Those skilled in the art are it should be appreciated that embodiments herein can be provided as method, system or computer program.Therefore, the application can adopt the form of the embodiment of complete hardware embodiment, complete application software embodiment or connected applications software and hardware aspect.And, the application can adopt the form at one or more upper computer programs implemented of computer-usable storage medium (including but not limited to disk memory, CD-ROM, optical memory etc.) wherein including computer usable program code.
The application describes with reference to flow chart and/or the block diagram according to the method for the embodiment of the present application, equipment (system) and computer program.It should be understood that can by the combination of the flow process in each flow process in computer program instructions flowchart and/or block diagram and/or square frame and flow chart and/or block diagram and/or square frame.These computer program instructions can be provided to produce a machine to the processor of general purpose computer, special-purpose computer, Embedded Processor or other programmable data processing device so that the instruction performed by the processor of computer or other programmable data processing device is produced for realizing the device of function specified in one flow process of flow chart or multiple flow process and/or one square frame of block diagram or multiple square frame.
These computer program instructions may be alternatively stored in and can guide in the computer-readable memory that computer or other programmable data processing device work in a specific way, the instruction making to be stored in this computer-readable memory produces to include the manufacture of command device, and this command device realizes the function specified in one flow process of flow chart or multiple flow process and/or one square frame of block diagram or multiple square frame.
These computer program instructions also can be loaded in computer or other programmable data processing device, make on computer or other programmable devices, to perform sequence of operations step to produce computer implemented process, thus the instruction performed on computer or other programmable devices provides for realizing the step of function specified in one flow process of flow chart or multiple flow process and/or one square frame of block diagram or multiple square frame.
Although having been described for the preferred embodiment of the application, but those skilled in the art are once know basic creative concept, then these embodiments can be made other change and amendment.So, claims are intended to be construed to include preferred embodiment and fall into all changes and the amendment of the application scope.
Obviously, the application can be carried out various change and modification without deviating from spirit and scope by those skilled in the art.So, if these amendments of the application and modification belong within the scope of the application claim and equivalent technologies thereof, then the application is also intended to comprise these change and modification.
Claims (10)
1. the method for the configuration file of an on-site programmable gate array FPGA of upgrading, it is characterised in that including:
Microcontroller, after the configuration file determining FPGA needs upgrading, controls serial peripheral equipment interface SPI bus switch and turns on the spi bus between described microcontroller and configuration chip, and disconnect the spi bus between described FPGA and described configuration chip；
After the configuration file that upgrading is used by described microcontroller is sent to described configuration chip by the spi bus between described microcontroller and configuration chip, control described spi bus and switch off the spi bus between described microcontroller and described configuration chip, and turn on the spi bus between described FPGA and described configuration chip.
2. the method for claim 1, it is characterised in that described microcontroller determines that the configuration file of described FPGA needs upgrading, including:
Described microprocessor is receiving after the upgrade command of control equipment, it is determined that the configuration file of described FPGA needs upgrading.
3. method as claimed in claim 2, it is characterised in that the configuration file that upgrading is used by described microcontroller also includes before being sent to described configuration chip by conducting spi bus:
Described microcontroller is receiving from after controlling the upgrade command of equipment, receives from the configuration file controlling equipment, and using configuration file that the described configuration file that receives uses as upgrading.
4. the method for claim 1, it is characterised in that the configuration file that upgrading is used by described microcontroller also includes after being sent to described configuration chip by the spi bus between described microcontroller and configuration chip:
Described microcontroller judges that whether described FPGA loading configuration file is failed, and loading result is sent to described control equipment.
5. the method as described in claim 2 or claim 3, it is characterised in that according to following manner, described microprocessor judges that whether described FPGA loading configuration file is failed:
Described microprocessor is after described FPGA loads described configuration file, it may be judged whether receive the loading pass signal of described FPGA feedback within the setting time；
If it is, determine the success of described FPGA loading configuration file；
Otherwise, it determines the failure of described FPGA loading configuration file.
6. a updating apparatus, it is characterised in that include microprocessor, spi bus controls switch, FPGA and configuration chip；
Described microprocessor is used for: after the configuration file determining described FPGA needs upgrading, controls upgraded module described in described spi bus switch conduction and the spi bus between configuration chip, and disconnects the spi bus between described FPGA and described configuration chip；After configuration file upgrading used is sent to described configuration chip by the spi bus between described upgraded module and configuration chip, control described spi bus and switch off the spi bus between described upgraded module and described configuration chip, and turn on the spi bus between described FPGA and described configuration chip.
7. equipment as claimed in claim 6, it is characterised in that described microcontroller specifically for:
Receiving after the upgrade command of control equipment, it is determined that the configuration file of described FPGA needs upgrading.
8. equipment as claimed in claim 7, it is characterised in that described microcontroller is additionally operable to:
Receiving from after controlling the upgrade command of equipment, receiving from the configuration file controlling equipment, and using configuration file that the described configuration file that receives uses as upgrading.
9. equipment as claimed in claim 6, it is characterised in that described microcontroller is additionally operable to:
Judge that whether described FPGA loading configuration file is failed, and loading result is sent to described control equipment.
10. according to following manner, the equipment as described in claim 7 or claim 8, it is characterised in that described microcontroller is additionally operable to, judges that whether described FPGA loading configuration file is failed:
After described FPGA loads described configuration file, it may be judged whether receive the loading pass signal of described FPGA feedback within the setting time:
If it is, determine the success of described FPGA loading configuration file；
Otherwise, it determines the failure of described FPGA loading configuration file.
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