CN105704924A - Method for encapsulating substrate and circuit board - Google Patents
Method for encapsulating substrate and circuit board Download PDFInfo
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- CN105704924A CN105704924A CN201410680318.9A CN201410680318A CN105704924A CN 105704924 A CN105704924 A CN 105704924A CN 201410680318 A CN201410680318 A CN 201410680318A CN 105704924 A CN105704924 A CN 105704924A
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- Prior art keywords
- substrate
- groove
- insulating barrier
- described substrate
- metal
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Abstract
The invention discloses a method of encapsulating a substrate. The objective of the invention is to solve the problem of a poor binding forces and uneven thickness of a processed groove wall insulation layer in substrate encapsulation in the prior art. The method includes the following steps that: a groove is processed in a substrate; the substrate is metalized; and the groove wall of the groove and the surface of the substrate are coated with an insulating layer through an electrophoresis process. The embodiment of the invention also provides a corresponding circuit board.
Description
Technical field
The present invention relates to circuit board technology field, be specifically related to method and the circuit board of a kind of base plate for packaging。
Background technology
Society is huge to designing the circuit board product demand having chip, such as mike, mains transformer, on and off switch, transducer, wave filter, agitator etc., therefore, the substrate of encapsulation has at least the groove structure of a hollow out, for chip placement, and form screen layer in the enterprising row metalization of cell wall, it is used for preventing chip signal to be disturbed；The outer layer of screen layer is insulating barrier, for armour metal layer and prevent short circuit。
At present, the technique of base plate for packaging is: use milling machine working groove, after electroless copper plating and plating, the sidewall at groove plates last layer copper, realize the circuit between different conductor layer to be connected, in whole groove, filling holes with resin is carried out again by the method for pressing, make to form insulating barrier, after filling up resin in whole groove, be solidified into an entirety, and then use milling machine to process the groove more slightly smaller than life size。
Practice finds, the cell wall insulating barrier that current technology processes, adhesion is bad, in uneven thickness。
Summary of the invention
The embodiment of the present invention provides method and the circuit board of a kind of base plate for packaging, is used for solving the problem that during base plate for packaging in prior art, the cell wall insulating barrier adhesion of processing is bad, in uneven thickness。
First aspect present invention provides a kind of method of base plate for packaging, including:
Substrate processes groove；
By described substrate metal；
Adopt the surface-coated insulating barrier of the electrophoresis process cell wall at described groove and described substrate。
In conjunction with first aspect, in the implementation that the first is possible, described on substrate, process groove before also include:
Blanking forms described substrate, and described substrate is resin glass fiber cloth double face copper。
In conjunction with the first possible implementation of first aspect or first aspect, in the implementation that the second is possible, the described groove that processes on substrate includes:
Adopting milling machine or laser equipment to process described groove on the substrate, the length of described groove and width are all not less than 0.4mm, and the height of described groove is not more than 1mm。
In conjunction with first aspect, in the implementation that the third is possible, described described substrate metal is included:
Carry out electroless copper plating and electro-coppering on the substrate, make described substrate metal, described in carry out the copper after electroless copper plating and plating thick in 10 μm。
In conjunction with the third possible implementation of first aspect, in the 4th kind of possible implementation, described carry out on the substrate electroless copper plating and plating before also include:
Remove staining of described substrate。
In conjunction with first aspect, in the 5th kind of possible implementation, described employing electrophoresis process also includes after the cell wall of described groove and the surface-coated insulating barrier of described substrate:
Toast described substrate。
In conjunction with the 5th kind of possible implementation of first aspect, in the 6th kind of possible implementation, also include after the described substrate of described baking:
The method adopting machinery brushing removes the insulating barrier of described substrate surface；
Adopting technique metal level on the plated surface of described substrate of plating or chemical plating, described metal level comprises the hybrid metal of Ni and Au or the hybrid metal of Ni, Pd and Au。
In conjunction with first aspect, in the 7th kind of possible implementation,
The thickness of described insulating barrier is not less than 50 μm, and described insulating barrier is resin bed。
In conjunction with first aspect, in the 8th kind of possible implementation,
Described groove, for chip placement；
Described insulating barrier, is coated uniformly on described substrate for conducting polymer under electric field action。
Second aspect present invention provides a kind of circuit board, including: substrate；
Described substrate is resin glass fiber cloth double face copper, and the surface of described substrate is coated with metal level, and described metal level comprises the hybrid metal of Ni and Au or the hybrid metal of Ni, Pd and Au；
Described substrate is provided with the groove for chip placement；
The length of described groove and width are all not less than 0.4mm, and the height of described groove is not more than 1mm；
The sidewall of described groove is provided with insulating barrier；Described insulating barrier is coated uniformly on described substrate for conducting polymer under electric field action。
Applying above technical scheme, the embodiment of the present invention adopts after processing groove on substrate, by substrate metal, and adopts the surface-coated insulating barrier of the electrophoresis process cell wall at groove and substrate, adopts the insulating barrier adhesion that electrophoresis process processes good, and thickness is uniform。
Accompanying drawing explanation
In order to be illustrated more clearly that embodiment of the present invention technical scheme, the accompanying drawing used required in embodiment and description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings。
Fig. 1 is an embodiment schematic diagram of the method for base plate for packaging in the embodiment of the present invention；
Fig. 2 is the schematic diagram processing groove in the embodiment of the present invention；
Fig. 3 is a schematic diagram of substrate metal in the embodiment of the present invention；
Fig. 4 is the schematic diagram being coated with insulating layer coating in the embodiment of the present invention；
Fig. 5 is a schematic diagram of the insulating barrier removing substrate surface in the embodiment of the present invention；
Fig. 6 is an embodiment schematic diagram of metal cladding in the embodiment of the present invention。
Detailed description of the invention
The embodiment of the present invention provides a kind of method of base plate for packaging, is used for solving the problem that during base plate for packaging in prior art, the cell wall insulating barrier adhesion of processing is bad, in uneven thickness。The embodiment of the present invention also provides for corresponding circuit board。
In order to make those skilled in the art be more fully understood that the present invention program, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the embodiment of a present invention part, rather than whole embodiments。Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, all should belong to the scope of protection of the invention。
Below by specific embodiment, it is described in detail respectively。
Embodiment one,
Referring to Fig. 1, the embodiment of the present invention provides a kind of method of base plate for packaging, it may include:
101, on substrate, groove is processed；
Refer to Fig. 2, in the embodiment of the present invention, substrate 200 processes groove 201。
Optionally, substrate 200 processes groove 201 before also include:
Blanking forms described substrate 200, and described substrate 200 is resin glass fiber cloth double face copper。
It should be noted that substrate includes copper foil layer and resin glass fiber layer of cloth, wherein, resin glass fiber layer of cloth is insulating barrier, and copper foil layer is line layer。Resin can be epoxy resin, it is also possible to is bimaleimide resin, is not specifically limited herein。
Optionally, substrate 200 processes groove 201 to include:
Adopting milling machine or laser equipment to process described groove 201 on the substrate, the length of described groove 201 and width are all not less than 0.4mm, and the height of described groove 201 is not more than 1mm。
102, by substrate metal；
Refer to Fig. 3, in the embodiment of the present invention, substrate 200 processes on the basis of groove 201, further substrate 200 is metallized。
Optionally, the metallization of described substrate 100 is included:
Described substrate 200 carries out electroless copper plating and electro-coppering, makes described substrate metal, described in carry out electroless copper plating and plating after copper thickness 102 more than 10 μm。
It is understood that copper is thick in 10 μm, it is ensured that the phenomenons such as fracture will not occur in the process of base plate for packaging。
Optionally, also include before described substrate 200 carrying out electroless copper plating and plating:
Remove staining of described substrate 200。
103, the surface-coated insulating barrier of the electrophoresis process cell wall at groove and substrate is adopted。
Refer to Fig. 4, in the embodiment of the present invention, on metallized for substrate 200 basis, the surface-coated insulating barrier 203 of the electrophoresis process cell wall at groove 201 and substrate will be adopted further。
Unlike the prior art, adopting the insulating barrier adhesion that electrophoresis process processes good, thickness is uniform。
Optionally, electrophoresis process is adopted also to include after the cell wall of described groove 201 and the surface-coated insulating barrier 103 of described substrate:
Toast described substrate 200。
It should be understood that by toasting so that insulating barrier is more firm, and adhesion is better。
Refer to Fig. 5 and Fig. 6, optionally, also include after toasting described substrate 200:
The method adopting machinery brushing removes the insulating barrier 203 on described substrate 200 surface；
Adopting technique metal level 204 on the plated surface of described substrate 200 of plating or chemical plating, described metal level 204 comprises the hybrid metal of Ni and Au or the hybrid metal of Ni, Pd and Au。
It should be noted that this metal level can also comprise other metals or other hybrid metals, it is not specifically limited herein。
It is understood that after adopting the method for machinery brushing to remove the insulating barrier of substrate surface, it is simple to follow-up metal cladding。
Optionally, the thickness of described insulating barrier is not less than 50 μm, and described insulating barrier is resin bed。
Optionally, described groove, for chip placement；
Described insulating barrier, is coated uniformly on described substrate for conducting polymer under electric field action。
The embodiment of the present invention adopts after processing groove on substrate, by substrate metal, and adopts the surface-coated insulating barrier of the electrophoresis process cell wall at groove and substrate, adopts the insulating barrier adhesion that electrophoresis process processes good, and thickness is uniform。
Embodiment two,
For ease of better implementing the above-mentioned correlation technique of the embodiment of the present invention, relevant apparatus for coordinate said method is also provided below。
The embodiment of the present invention provides a kind of circuit board, it may include:
Substrate；Described substrate is resin glass fiber cloth double face copper, and the surface of described substrate is coated with metal level, and described metal level comprises the hybrid metal of Ni and Au or the hybrid metal of Ni, Pd and Au；
Substrate is provided with the groove for chip placement；
The length of described groove and width are all not less than 0.4mm, and the height of described groove is not more than 1mm；
The sidewall of groove is provided with insulating barrier；Described insulating barrier is coated uniformly on described substrate for conducting polymer under electric field action。
Owing to this circuit board is the circuit board corresponding to said method embodiment, specifically see above-described embodiment, repeat no more herein。
In sum, the embodiment of the present invention adopts after processing groove on substrate, by substrate metal, and adopts the surface-coated insulating barrier of the electrophoresis process cell wall at groove and substrate, adopts the insulating barrier adhesion that electrophoresis process processes good, and thickness is uniform。
It should be noted that, for aforesaid each embodiment of the method, in order to be briefly described, therefore it is all expressed as a series of combination of actions, but those skilled in the art should know, the present invention is not by the restriction of described sequence of movement, because according to the present invention, some step can adopt other order or carry out simultaneously。Secondly, those skilled in the art also should know, embodiment described in this description belongs to preferred embodiment, necessary to involved action and the module not necessarily present invention。
Method and the circuit board of the base plate for packaging above embodiment of the present invention provided are described in detail, but the explanation of above example is only intended to help to understand method and the core concept thereof of the present invention, should not be construed as limitation of the present invention。Those skilled in the art, according to the thought of the present invention, in the technical scope that the invention discloses, the change that can readily occur in or replacement, all should be encompassed within protection scope of the present invention。
Claims (10)
1. the method for a base plate for packaging, it is characterised in that including:
Substrate processes groove；
By described substrate metal；
Adopt the surface-coated insulating barrier of the electrophoresis process cell wall at described groove and described substrate。
2. method according to claim 1, it is characterised in that described on substrate, process groove before also include:
Blanking forms described substrate, and described substrate is resin glass fiber cloth double face copper。
3. method according to claim 1 and 2, it is characterised in that the described groove that processes on substrate includes:
Adopting milling machine or laser equipment to process described groove on the substrate, the length of described groove and width are all not less than 0.4mm, and the height of described groove is not more than 1mm。
4. method according to claim 1, it is characterised in that described described substrate metal is included:
Carry out electroless copper plating and electro-coppering on the substrate, make described substrate metal, described in carry out the copper after electroless copper plating and plating thick in 10 μm。
5. method according to claim 4, it is characterised in that described carry out on the substrate electroless copper plating and plating before also include:
Remove staining of described substrate。
6. method according to claim 1, it is characterised in that described employing electrophoresis process also includes after the cell wall of described groove and the surface-coated insulating barrier of described substrate:
Toast described substrate。
7. method according to claim 6, it is characterised in that also include after the described substrate of described baking:
The method adopting machinery brushing removes the insulating barrier of described substrate surface；
Adopting technique metal level on the plated surface of described substrate of plating or chemical plating, described metal level comprises the hybrid metal of Ni and Au or the hybrid metal of Ni, Pd and Au。
8. method according to claim 1, it is characterised in that
The thickness of described insulating barrier is not less than 50 μm, and described insulating barrier is resin bed。
9. method according to claim 1, it is characterised in that
Described groove, for chip placement；
Described insulating barrier, is coated uniformly on described substrate for conducting polymer under electric field action。
10. a circuit board, it is characterised in that including: substrate；
Described substrate is resin glass fiber cloth double face copper, and the surface of described substrate is coated with metal level, and described metal level comprises the hybrid metal of Ni and Au or the hybrid metal of Ni, Pd and Au；
Described substrate is provided with the groove for chip placement；
The length of described groove and width are all not less than 0.4mm, and the height of described groove is not more than 1mm；
The sidewall of described groove is provided with insulating barrier；Described insulating barrier is coated uniformly on described substrate for conducting polymer under electric field action。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410680318.9A CN105704924A (en) | 2014-11-24 | 2014-11-24 | Method for encapsulating substrate and circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410680318.9A CN105704924A (en) | 2014-11-24 | 2014-11-24 | Method for encapsulating substrate and circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105704924A true CN105704924A (en) | 2016-06-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410680318.9A Pending CN105704924A (en) | 2014-11-24 | 2014-11-24 | Method for encapsulating substrate and circuit board |
Country Status (1)
| Country | Link |
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| CN (1) | CN105704924A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050224968A1 (en) * | 2004-03-31 | 2005-10-13 | Aptos Corporation | Wafer level mounting frame for ball grid array packaging, and method of making and using the same |
| CN103222353A (en) * | 2010-07-23 | 2013-07-24 | 德塞拉股份有限公司 | Microelectronic elements with post-ssembly planarization |
| CN103779245A (en) * | 2014-01-28 | 2014-05-07 | 苏州晶方半导体科技股份有限公司 | Chip packaging method and packaging structure |
-
2014
- 2014-11-24 CN CN201410680318.9A patent/CN105704924A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050224968A1 (en) * | 2004-03-31 | 2005-10-13 | Aptos Corporation | Wafer level mounting frame for ball grid array packaging, and method of making and using the same |
| CN103222353A (en) * | 2010-07-23 | 2013-07-24 | 德塞拉股份有限公司 | Microelectronic elements with post-ssembly planarization |
| CN103779245A (en) * | 2014-01-28 | 2014-05-07 | 苏州晶方半导体科技股份有限公司 | Chip packaging method and packaging structure |
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Application publication date: 20160622 |
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