CN105704080A - Improved variable code rate carrier wave synchronization Costas loop design - Google Patents

Abstract

The invention discloses a variable code rate carrier wave synchronization structure based on a Costas ring and belongs to the signal processing technology field. In an existing Costas ring structure, a parameter value corresponding to a specific code rate is fixed to an internal portion of a program in advance and the parameter value can not modified in real time. Aiming at the above defects, on a basis of analyzing and researching an original Costas ring structure, a Costas loop carrier wave synchronization system in which the parameter can be modified in real time and which is suitable for the variable code rate is designed and realized. In the system, an external controller dynamically calculates each parameter according to a change of a code rate, and an FPGA heavy load technology is used to update the parameter to a Costas carrier wave synchronization ring in real time. In a wide scope, carrier wave synchronization of the variable code rate can be rapidly realized so that an important meaning is possessed to subsequent signal processing.

Description

A kind of variable bit rate carrier synchronization Costas loop design of improvement

Technical field

The present invention relates to a new generation's receiver signal of communication to process, be specially a kind of based on Costas ring, it is achieved the carrier synchronization problem of variable bit rate。

Background technology

Simultaneous techniques, as one of the core technology of communication system, is occupied vital effect in a communications system, is directly affected the performance of communication system。Carrier synchronization is not only an important branch of synchronization, and determines the demodulation performance of coherent demodulation system to a great extent。Carrier synchronization method has two classes: a class is closed loop carrier synchronization method, and another kind of is open-loop carrier Synchronos method。Wherein, the Costas ring structure in closed loop carrier synchronization method is owing to having certain frequency displacement rejection ability, and is the optimum device following the tracks of low signal-to-noise ratio, suppressed carrier signal, is therefore widely applied in carrier synchronization。

Costas ring carrier synchronization systematic study carries out carrier synchronization processes for specific bit rate substantially both at home and abroad at present。Owing to Costas ring parameter value is fixed on inside program in advance, and one group of Costas ring parameter value can only corresponding a kind of bit rate, when inputting the bit rate change of data, then former synchronization parameter can not realize carrier synchronization, limited bit rate change is adapted to, it is impossible to according to applied environment, the parameter value of carrier synchronization is carried out real-time adjustment only by switching intrinsic bit rate gear。In top receiver or communication instrument are applied, after secret signalling reaches carrier synchronization, it is desirable to the fluctuation range of frequency and the bit error rate are as far as possible little, then the parameter of Costas ring must be accurately；Frequency-hopping communication system requires that Costas ring sets up carrier synchronization within the shortest time, it is allowed to certain frequency shift (FS) and the bit error rate。In order to meet the requirement of different communication systems, it is desirable to each several part parameter real-time, tunable of Costas ring, and the Costas ring carrier synchronization structure of existing designated code speed can only meet a kind of communication system。

Document currently for variable bit rate Carrier Synchronization research is fewer, " Liu Guodong. the Clock extraction of rate-compatible differential phase keying (DPSK) nonreturn to zero code signal. Chinese laser; 2014 " with " China is outstanding. based on the research communicated between the time-varying code speed star of formation flight small satellite system. China Science & Technology University; 2014 " etc. variable bit rate has been studied, but be directed to Inter-satellite Communication System and optical communication system。Therefore the present invention based on above-mentioned some propose a kind of Costas ring carrier synchronization structure for top receiver communication system of new generation, parameter can be carried out real time modifying, carrier synchronization suitable in variable bit rate by this structure。

Summary of the invention

The technical problem to be solved, need to be fixed to inside program by parameter value corresponding for special code speed for existing Costas ring structure in advance, and parameter value can not the defect of real time modifying。Propose a kind of carrier synchronization structure based on Costas ring, the problem solving quickly to realize carrier synchronization under bit rate situation of change。The method calculates parameter value by peripheral control unit, then the parameter value of calculating divides three groups be handed down to FPGA relevant parameter is carried out real time modifying, reach quickly to realize the purpose of variable bit rate carrier synchronization。

This invention address that the technical scheme of above-mentioned technical problem is: the correlation of input signal is set by peripheral control unit；Peripheral control unit calculates corresponding parameter according to Android interface input value, obtains three groups of parameter values, parameter value encapsulates framing and is handed down to internal controller FPGA by interface channel；After internal controller receives frame, resolve the parameter of each several part in frame, each several part parameter is modified, so that loop completes carrier synchronization, wherein data stream is consistent with the processing procedure of traditional designated code speed Costas ring carrier synchronization structure in the processing procedure of internal controller；When the bit rate that synchro system inputs signal changes, parameter in Costas ring cannot meet synchronization requirement, therefore loop parameter must be modified (such as: low pass filter filter factor, loop filter parameters etc.), now peripheral control unit must recalculate the parameter in Costas ring according to actual needs, then re-issue to internal processor by calculating the parameter value obtained, internal controller revises parameter value corresponding in carrier synchronization structure in the way of coefficient heavy duty, it is achieved carrier synchronization when variable bit rate。

The carrier synchronization when present invention uses Costas loop technique to realize variable bit rate, not only overcomes convention carrier simultaneous techniques and for the problem of specific bit rate, and can only improve the time of the foundation of carrier synchronization。

Accompanying drawing explanation

Fig. 1 overall structure figure of the present invention

Fig. 2 second-order loop filter structure chart of the present invention

Fig. 3 present invention inputs signal carrier and synchronizes front and back planisphere

Fig. 4 present invention inputs signal carrier and synchronizes front and back eye pattern

Fig. 5 present invention locks curve comparison figure before and after improving

Fig. 6 difference filter order carrier synchronization locking curve of the present invention

The convergence curve of Fig. 7 difference bit rate input signal of the present invention

Detailed description of the invention

According to Fig. 1 Costas ring carrier synchronization theory diagram improved, if input signal expression is:

S (t)=m (t) cos (ω_c+θ)(1)

In formula, m (t) represents baseband signal；ω_cMid frequency for carrier wave；θ is initial phase。So, the input two-way orthogonal signalling that produce with NCO of data are multiplied respectively and obtain being mixed data, after being then passed through low pass filter, phase discriminator process, homophase, orthogonal two loops error signal be respectively as follows:

S_I(t)=m (t) cos (ω_c+θ₁)(2)

S_Q(t)=m (t) cos (ω_c+θ₁)(3)

Two error signals are output as after being multiplied:

$U_d\left(t\right)=\frac{K_{Id}{K}_{Qd}}{8}{m}^2\left(t\right)sin\[2(\mathrm{\θ}-{\mathrm{\θ}}_1)\]---\left(4\right)$

K in formula_Id、K_QdFor the phase demodulation factor。Phase error signal enters loop filter and is filtered processing, now loop filter function as low pass filter, its cut-off frequency is very low, only allows the signal of approximate DC to pass through。

The output signal of digital loop filters is the frequency control word of NCO, by adjusting the frequency control word of NCO in real time, controls NCO and exports frequency and the phase place of local carrier signal so that phase error signal U_dT () is little as far as possible。By formula (4) it can be seen that ideally, as the instantaneous phase difference U of input signal and local signal_dDuring (t)=0, namely realize the carrier wave of local carrier signal and input signal with frequency homophase。

The low pass filter of adaptive-bandwidth is the changeable low pass filter of pass band width, and its major function is to filter high fdrequency component and out-of-band noise, finally obtains such as the result of formula (2) and formula (3)。

Variable bandwidth low-pass ripple device coefficient can be adjusted in real time by peripheral control unit。The performance of Costas ring all can be impacted by the change etc. of the exponent number of the input bit rate of signal, decay factor and low pass filter, therefore has three input options as shown in fig. 1 at the coefficients generator of peripheral control unit。

Fig. 2 be the loop filter structure after improving compared with classical loop filter structure, the parameter of the loop filter of present invention design, can by real time modifying by the control of peripheral control unit。Loop filter in Costas loop circuit is a linear low-pass filters, and it is possible not only to filter the radio-frequency component in instantaneous phase error signal, and the adjustment of loop parameter is played a decisive role。It addition, it can provide an impermanent memory for loop, can guarantee that phaselocked loop rapid recapture signal when system is due to instantaneous noise losing lock。

Second order digital loop filter stable state difference when locking is 0, and Timing Belt is infinitely great, it is achieved difficulty is suitable for, so adopting second order digital loop filter in major part Costas ring。

C in Fig. 2₁、C₂Represent the coefficient of integration branch road and proportional branch, e^IFREQUENCY CONTROL for loop filter output is lived, for adjusting the phase place of local NCO。This second-order loop filter transmission function in Z territory is:

$F\left(z\right)=C_1+\frac{C_2}{1-Z^{-1}}---\left(6\right)$

$C_1=\frac{8{\mathrm{\ξX}}_{n}T}{K_0{K}_d\[4+4{\mathrm{\ξX}}_{n}T+{\left(X_{n}T\right)}^2\]}---\left(7\right)$

$C_2=\frac{4{\left(X_{n}T\right)}^2}{K_0{K}_d\[4+4{\mathrm{\ξX}}_{n}T+{\left(X_{n}T\right)}^2\]}---\left(8\right)$

K₀For local NCO gain, K_dFor phase detection gain；ξ is the damped coefficient of phaselocked loop, generally takes ξ=0.707；X_nFor loop natural angular frequency, and change with the change of input signal code speed。T is loop filter sampling time interval, and namely phase place adjusts interval, and its value is f_sInverse。

$X_n=\frac{8K_L{R}_b}{4{\mathrm{\ξ}}^2+1}---\left(9\right)$

K_LFor the regulatory factor of loop, R_bFor input signal code speed。When inputting the change of signal code speed, X_nAlso changing, peripheral control unit can recalculate loop filter parameters value C according to formula (7), (8) and (9)₁And C₂, then parameter value is issued to internal controller, in order to internal controller undated parameter value。

In Fig. 3, a figure represents, when input signal is not up to carrier synchronization, its planisphere is a discrete circle；After Costas ring carrier synchronization, importing in MATLAB by the data that FPGA produces, the planisphere approximate convergence obtaining input signal is four points, in Fig. 6 shown in b figure。Owing to not carrying out bit synchronization, therefore planisphere can not Complete Convergence be four points。

In Fig. 4 a, b two figure represent respectively the eye pattern inputting signal before and after carrier synchronization, left figure represent without carrier synchronization input signal eye pattern, now input signal without carrier synchronization, eye pattern is very discrete, can't see clearly " eyes "；Right figure represents derives, by FPGA data, the eye pattern obtained after carrier synchronization, and after Costas ring carrier synchronization, eye pattern is restrained very much, and " eyes " open bigger, and eye pattern is very proper。

After the analogous diagram of Fig. 3, Fig. 4 improved Costas ring of known input signal, complete carrier synchronization, hence it is demonstrated that the correctness of the Costas ring carrier synchronization structure of the present invention。

In Fig. 5 a, b two figure represent input data, signal to noise ratio, decay factor etc. all identical when, be the phase error simulation figure that the input signal of 30KHz produces after Costas ring carrier synchronization structure by input signal frequency deviation。Owing to a figure peripheral control unit only issues one group of parameter, therefore complete time substantially about the 2.2ms of carrier synchronization；B figure peripheral controller issues two groups of parameter values, and the convergence time of input data is about about 0.3ms。First realizing thick synchronization with one group of parameter value in b figure, then realize essence with another group parameter value again and synchronize, the effect being finally reached is consistent with a figure, but it can be seen that the time of carrier synchronization shortens nearly 7 times。

In Fig. 6 a, b two figure represent different low pass filter exponent number respectively, input data reach the convergence curve of carrier synchronization。In Fig. 6, the low pass filter exponent number of a figure is 50, and the time reaching carrier synchronization is 0.9ms；The low pass filter exponent number of b figure is 30, and the time reaching carrier synchronization is 1.2ms, and therefore input data reach time of carrier synchronization and are inversely proportional to low pass filter exponent number。

Fig. 7 represents input signal frequency deviation curve of loop filter output after Costas ring, and the bit rate wherein inputting signal first is 2Mbps, and the time of loop-locking is 0.9ms, as shown in figure a；When the bit rate inputting signal becomes 4Mbps, the time that loop relocks is 1.7ms, as shown in figure b figure；When the bit rate inputting signal is 8Mbps, the time that loop relocks is 3.9ms, as shown in figure c figure。By the analysis of Fig. 7 it can be seen that carrier synchronization intermediate ring road increases along with the increase of bit rate locking time。

By theoretical derivation and simulation analysis, demonstrate correctness and the feasibility of design of the present invention。The present invention is applicable to the Costas ring carrier synchronization system of variable bit rate, uses FPGA heavy duty technology and interfacing that loop parameter carries out real time modifying, eliminates the carrier wave frequency deviation of input signal。Compared with traditional Costas ring carrier synchronization system, the structure after improvement can not only meet specific environment demand, quickly finishes carrier synchronization, and can adapt to environment complicated and changeable according to actual needs。

Claims (5)

1. based on a Costas ring variable bit rate carrier synchronization structure, its step is in that, the analogue signal received, after A/D samples, is converted to digital signal, i.e. the input signal of Costas ring by IF input signals；Input signal is divided into two branch roads of I, Q after entering Costas ring, and being multiplied with the NCO quadrature carrier produced respectively obtains mixing data；Mixing data obtain i after LPF_k、q_kTwo paths of signals；I by output_k、q_kSignal is input to phase demodulation module and carries out phase error computation, it is thus achieved that phase error；Then after loop filter module, obtain error controling signal (frequency control word), control NCO and adjust output frequency, be gradually reduced the phase contrast between local carrier and modulation carrier wave, be finally completed carrier synchronization。

2. process according to claim 1, local NCO adopts DDS principle design。DDS (direct digital synthesis technique) is a kind of new frequency synthesis technique, has that frequency resolution height, frequency conversion speed be fast and Phase Continuation, output signal accuracy advantages of higher。Concrete implementation adopts the IPCore carried in Vivado13.3 software to be designed, and wherein the computing formula of frequency control word isN represents frequency control word bit wide, f_outRepresent output frequency, f_clkSample frequency for system。Output frequency can be configured by the FREQUENCY CONTROL word modules in peripheral control unit, and when output frequency changes, calculated frequency control word can be handed down to internal controller by peripheral control unit, internal controller receive renewal instruction after renewal frequency control word。

3. process according to claim 1, low pass filter implements and adopts the IDE Vivado13.3 FIR filter IPCore carried。Filter coefficient is generated by the coefficients generator of peripheral control unit, and is passed to internal controller by passage, then passes through coefficient heavy duty and imports IP kernel, and the data bit width of variable bandwidth low-pass ripple device coefficient is 16, is controlled by peripheral control unit。When the bit rate change of the input signal that receiver receives, need according to practical situation, the data of three inputs of coefficients generator in peripheral control unit to be arranged in real time, the parameter value of acquisition is handed down to internal controller, in the IPCore that in the way of coefficient heavy duty, the coefficient value received is updated FPGA。Therefore the amendment to low-pass filter coefficients is realized。

4. process according to claim 1, loop filter C₁、C₂Value can also be changed by peripheral control unit。When bit rate changes, peripheral control unit can calculate corresponding value according to formula (7) (8), by the algorithm of host computer in peripheral control unit, two class values obtained is handed down to FPGA respectively；FPGA updates C₁、C₂The Fast carrier realizing variable bit rate synchronizes。

5. the present invention chooses the conventional QPSK signal input signal as Costas ring。For ease of analyzing, analogous diagram is by inputting data after Costas ring carrier synchronization structure, FPGA being saved in text document by the data of generation, then utilize and draw its wave simulation waveform in MATLAB。