CN105703745A - Clock state indicating circuit and method - Google Patents
Clock state indicating circuit and method Download PDFInfo
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- CN105703745A CN105703745A CN201410679855.1A CN201410679855A CN105703745A CN 105703745 A CN105703745 A CN 105703745A CN 201410679855 A CN201410679855 A CN 201410679855A CN 105703745 A CN105703745 A CN 105703745A
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Abstract
The invention relates to a clock state indicating circuit. The clock state indicating circuit includes a clock frequency dividing circuit, an edge correction circuit, an edge detection circuit and a shift register circuit, wherein the clock frequency dividing circuit is connected with the edge correction circuit, the edge correction circuit is connected with the edge detection circuit and the shift register circuit, and the edge detection circuit is connected with the shift register circuit. The method includes the following steps that: different frequency division clock signals and periodic reset signals are generated; and a clock state is indicated through the shift and reset operation of a shift register. According to the circuit of the invention, when frequency-halving is adopted, at least six flip flops and two gate circuits can be adopted to realize a clock state indicating function. The clock state indicating circuit has the advantages of simple structure, lower operation power consumption and the like.
Description
Technical field
The present invention relates to a kind of clock status indicating circuit and method, normally whether specifically a kind of monitoring clock state for on-chip system chip circuit and method。
Background technology
Along with developing rapidly of integrated circuit technique, particularly on-chip system chip technology, chip internal has been generally integrated multiple clock agitator, relatively common such as resistance-capacitance type agitator, quartz oscillator etc.。The startup time of different clock oscillators is different, and precision, stability are also different。As a rule, it is fast that resistance-capacitance type agitator has the startup time, the features such as precision is relatively low；It is slow that quartz oscillator has the startup time, precision high。On-chip system chip is in the process of working on power, and in order to reach quickly to launch into duty, usually first uses resistance-capacitance type agitator as system work clock, after quartz oscillator stably starts, is automatically switched to system work clock。In order to complete clock handoff procedure, inside on-chip system chip, must there is the clock status indicating circuit duty for real-time telltable clock。Therefore, inside the on-chip system chip including multi-clock agitator, clock monitor circuit is generally all comprised。When clock monitor circuit can be used for when on-chip system chip starts or has clock oscillator to lose efficacy, generate switching or disablement signal, it is ensured that the normal operation of chip。
Traditional method that realizes generally is taked to use two intervalometers, and respectively reference clock and detection clock count respectively, by count value is compared, it is judged that loss of clock。Also some method uses single counter, two stage latch structure, judges whether clock is lost by the similarities and differences of two stage latch value。No matter adopt above any method, circuit structure all relative complex, consume more logical resource, the power consumption of on-chip system chip can be brought negative effect。
Summary of the invention
For above-mentioned technical deficiency, it is an object of the present invention to provide a kind of clock status indicating circuit towards SOC(system on a chip) and method。Clock signal to be measured when clock frequency to be measured is more than reference clock, effectively can be carried out state instruction, produces the condition indicative signal of clock to be measured by this circuit。
In order to realize function above, this invention takes following technical scheme: a kind of clock status indicating circuit, including clock division circuits, edge correction circuit, edge sense circuit and shift-register circuit；Described clock division circuits is connected with edge correction circuit；Described edge correction circuit is connected with edge sense circuit, shift-register circuit；Described edge sense circuit is connected with shift-register circuit；
Described clock division circuits is for dividing reference clock, and output frequency division clock signal is to edge sense circuit；
Described edge sense circuit access clock to be measured, clock division circuits output sub-frequency clock signal and edge correction circuit output edge correction signal, sub-frequency clock signal carries out edge detection, and output cycle reset signal is to edge correction circuit and shift-register circuit；
Described edge correction circuit accesses reference clock and cycle reset signal is modified obtaining edge correction signal and exports to edge sense circuit；
Described shift-register circuit accesses high level, reference clock and cycle reset signal, carries out internal register displacement and reset operation, exports clock status signal。
Described clock division circuits includes not gate and depositor；Described non-gate output terminal is connected with the data terminal of depositor, and the outfan of depositor is as the output of clock division circuits, and the input of NAND gate connects；The clock of depositor terminates into reference clock。
Described edge sense circuit includes three depositors being sequentially connected with and an XOR gate；The clock end of described three depositors all accesses clock to be measured, reset terminal is all connected with the outfan of edge correction circuit, the the first register data end being sequentially connected with is as the input of edge sense circuit and is connected with the outfan of clock division circuits, 3rd depositor outfan is connected with the first input end of XOR gate, second depositor outfan is connected with the second input of XOR gate, and the outfan of XOR gate is as the output of edge sense circuit。
Described edge sense circuit include not gate and with door, the input of not gate accesses reference clock, and outfan is connected with the first input end with door, is connected with the outfan of edge sense circuit with the second input of door, and outfan is the output of edge sense circuit。
Described shift-register circuit includes multiple depositor being linked in sequence, the clock end of each depositor all accesses reference clock, reset terminal is all connected with the outfan of edge sense circuit, the data terminal of first depositor connects high level, and the outfan of last depositor is as the output of shift-register circuit。
A kind of clock status indicating means, comprises the following steps:
A. reference clock is carried out frequency dividing and obtains sub-frequency clock signal by clock division circuits；
B. sub-frequency clock signal is carried out edge detection and obtains cycle reset signal by edge sense circuit；
C. high level is transmitted by shift-register circuit step by step, and when clock to be measured is normal, internal depositor is resetted by cycle reset signal, and shift-register circuit output keeps low level；When clock exception to be measured, cycle reset dropout, shift-register circuit output keeps high level；
D. correction circuit in edge is when clock to be measured stopping and cycle reset abnormal signal, the reference clock negated and cycle reset signal is carried out and generates edge correction signal；
E. exported clock status signal by shift-register circuit, return step a。
Described edge detection is specially when producing edge, and the second depositor being sequentially connected with and the output of the 3rd depositor not etc., do not produce high level by XOR gate。
The described frequency dividing that carries out is for carrying out N-equal duty ratio frequency dividing。
In described shift-register circuit, the progression of depositor is more than N+1 level。
The invention have the advantages that and advantage:
1. circuit of the present invention is towards system-on-chip designs, it is possible to the effective state providing clock signal to be measured。
2. circuit of the present invention all adopts Design of Digital Circuit to realize, it does not have analog circuit, it is possible to adopt in multiple fields such as IC design or field programmable logic array designs。
3. circuit of the present invention is when adopting 2 frequency dividing, and most I adopts six triggers and two gate circuits namely can realize clock status deictic function, has simple in construction, runs the advantages such as power consumption is little。
Accompanying drawing explanation
Fig. 1 is one clock status indicating circuit structure chart of the present invention；
Fig. 2 is 2 frequency-dividing clock frequency dividing circuit structure charts；
Fig. 3 is edge sense circuit structure chart；
Fig. 4 is edge correction circuit structure diagram；
Fig. 5 is shift-register circuit structure chart。
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail。
A kind of clock status indicating circuit, external input port includes reference clock signal, clock signal to be measured, output port include clock status signal。
When this, the port function of circuit describes as follows: reference clock signal is to continuously generate, and provides the clock of reference for producing clock status signal, is generally low frequency clock, in actual applications, can adopt the low-frequency clocks such as 32KHz, 10KHz；Clock signal to be measured, for being clock signal under, refers generally to altofrequency clock, in specialty of the present invention, should be more than the 3 of reference clock frequency times；Clock status signal indicates clock signal to be measured whether normal operation, if normal operation, output low level signal, otherwise generates high level signal。
The functional module of the present invention includes clock division circuits, edge correction circuit, edge sense circuit, shift-register circuit。
Module and the port connection relationship of the present invention are as follows: the input clock port of described clock division circuits is inputted by reference clock signal, and output port is sub-frequency clock signal；The input clock port of edge sense circuit is inputted by clock signal to be measured, and input reseting port is inputted by the edge correction signal of edge sense circuit, and output port is cycle reset signal；The input clock port of edge correction circuit is inputted by reference clock signal, and input reseting port is inputted by the cycle reset signal of edge sense circuit, and output port is edge correction signal；The input clock port of shift-register circuit is inputted by reference clock signal, and input reseting port is inputted by the cycle reset signal of edge sense circuit, and output port is clock status signal。
In patent of the present invention, the function of clock division circuits is reference clock signal to carry out N-equal duty ratio frequency dividing obtain sub-frequency clock signal, and effective high level of this signal and low level length are NT/2。Wherein the span of N is 1 to infinity, when N value is 1, does not namely divide。If the dutycycle of reference clock signal meets or can value be 1 close to 1, N。
In patent of the present invention, edge sense circuit is under clock effect to be measured, and the sub-frequency clock signal that clock division circuits is generated carries out edge detection, extracts rising edge and trailing edge specifically, and the generation cycle is the cycle reset signal of NT。
In patent of the present invention, the effect of edge correction circuit is cycle reset signal and reference clock signal that edge sense circuit is produced, by combinational logic circuit, produces edge correction signal。
In patent of the present invention, shift-register circuit comprises N+1 level Parasites Fauna, under cycle reset signal and reference clock effect, carries out resetting and the operation such as displacement, generates clock status signal。
The principles illustrated of circuit of the present invention is as follows。
Note reference clock signal frequency is F, and frequency is T。By the relation of frequency and clock, can obtaining the product of F and T equal to 1, namely F is equal to 1/T。
Reference clock signal carrying out N-equal duty ratio frequency dividing and can obtain effective high level and low level length is NT/2, the cycle is the frequency-dividing clock of NT；When clock to be measured is effective, can generate the cycle with frequency-dividing clock is NT cycle reset signal；In the N+1 level shift register group that high level input, reference clock drive, effect due to cycle reset signal that the cycle is NT, shift-register circuit resetted with NT for the cycle, high level is made to be merely able to be delivered to the N level depositor of shift register, being not transferred to the N+1 level of shift-register circuit, namely clock status signal remains low level；When disabling clock signals to be measured, edge sense circuit cannot generate cycle reset signal, and the N+1 level depositor in shift-register circuit finally produces high level instruction。
Due to the uncertainty of clock to be measured, under certain conditions, it is possible to create abnormal cycle reset signal, now shift-register circuit can be produced the impact of mistake, produce the clock status result of mistake。For the correction of this result can pass through cycle reset signal and reverse reference clock by with gate logic, produce edge correction signal。Correction signal in edge can revise abnormal cycle reset signal, and finally produces correct clock status signal。
When adopt N-equal duty ratio frequency dividing time, the progression of shift register be N+1 or more than, original normal circuit operation can be protected。
The method step of circuit of the present invention is:
Reference clock signal is carried out N-equal duty ratio frequency dividing by clock division circuits, and to obtain the cycle be NT sub-frequency clock signal；
The sub-frequency clock signal that clock division circuits is generated by edge sense circuit carries out edge detection, and the generation cycle is the cycle reset signal of NT；
High level is transmitted by shift-register circuit step by step, and when clock to be measured is normal, internal depositor is resetted by cycle reset signal, and shift-register circuit output keeps low level；When clock exception to be measured, cycle reset dropout, shift-register circuit output keeps high level。
Correction circuit in edge, when abnormal cycle reset signal being detected, generates edge correction signal；Edge sense circuit, under edge correction signal function, carries out logic circuit process, revises abnormal cycle reset signal。
Shift-register circuit, according to cycle reset signal and reference clock signal, produces clock status signal
Embodiment:
The present embodiment is a kind of mode realizing clock status indicating circuit described in this patent, have employed relatively simple circuit structure, wherein the N value in clock division circuits is 2, namely adopts the duty frequency dividings such as 2-, and shift register adopts 3 bit register shift-register circuits。
Specific embodiment refers to shown in Fig. 1, a kind of clock status indicating circuit, and structure includes clock division circuits, edge sense circuit, edge correction circuit and shift-register circuit；Outside port includes output port reference clock and clock to be measured, output port clock status。
Concrete annexation is, reference clock signal is connected to the clock port CK of clock division circuits, and the output terminal of clock mouth Q of clock division circuits produces sub-frequency clock signal C1；Clock signal to be measured is connected to the clock port CK of edge sense circuit, clock division circuits produces sub-frequency clock signal C1 and is connected to the FPDP D of edge sense circuit, correction circuit in edge produces edge correction signal F1 and is connected to the reset terminal of edge sense circuit, and the output port Q of edge sense circuit generates set signal R1；
The input clock port CK of edge correction circuit is inputted by reference clock signal, and input reseting port R is inputted by the cycle reset signal R1 of edge sense circuit, and output port is edge correction signal F1, exports the reseting port R to edge sense circuit；
The cycle reset signal R1 that edge sense circuit generates is connected to the reseting port R of shift-register circuit, reference clock signal is connected to the clock port CK of shift-register circuit, the FPDP D of shift-register circuit connects high level signal, and shift-register circuit output Q produces clock status signal。
The present embodiment adopts 2 frequency-dividing clock frequency dividing circuits, as shown in Figure 2。This frequency dividing circuit includes depositor 1 and not gate 1。The input end of clock mouth CK that its annexation is depositor 1 is inputted by the portion input port CK of clock division circuits, the data-in port D of depositor 1 is inputted by the output port Q of not gate 1, the output port Q of depositor 1 exports the input port A of not gate 1, and the output port Q of depositor 1 exports the output port Q of clock division circuits；The input port A of not gate 1 is inputted by the output port Q of depositor 1, and the output port Q of not gate 1 exports the input port D of depositor 1。
In the present embodiment, edge sense circuit structure is as shown in Figure 3。This edge sense circuit comprises depositor 2, depositor 3, depositor 4 and XOR gate 1 and forms。The input port D that its annexation is depositor 2 is inputted by edge sense circuit externally input CK, and the input port CK of depositor 2 is inputted by edge sense circuit externally input CK, and the output port Q of depositor 2 exports the input port D of depositor 3；The input port CK of depositor 3 is inputted by edge sense circuit externally input CK, and the input port D of depositor 2 is inputted by the output port Q of depositor 2, and the output port Q of depositor 3 exports the input port D of depositor 4 and the input port B of XOR gate 1；The input port CK of depositor 4 is inputted by edge sense circuit externally input CK, and the input port D of depositor 4 is inputted by the output port Q of depositor 3, and the output port Q of depositor 4 exports the input port A of XOR gate 1；The input port A of XOR gate 1 is inputted by the output port Q of depositor 4, and the output port B of XOR gate 1 is inputted by the output port Q of depositor 3, and the output port Q of XOR gate 1 exports the external output port Q of edge sense circuit。
In the present embodiment, edge correction circuit structure is as shown in Figure 4。This edge correction circuit comprises not gate 1 and forms with door 1。The input port A that its annexation is not gate 1 is inputted by the outside port CK of edge correction circuit, and the output port Q of not gate 1 is connected to the input port A with door 1；Accessed by the output port Q of not gate 1 with the input port A of door 1, accessed by the outside port R of edge correction circuit with the input port B of door 1, with the outside port Q that the output port Q of door 1 exports edge correction circuit。
In the present embodiment, shift-register circuit structure is as shown in Figure 5。This shift-register circuit comprises depositor 5, depositor 6 and depositor 7 and forms。The input port D that its annexation is depositor 5 is inputted by high level signal, and the input port CK of depositor 5 is inputted by shift-register circuit external input port CK, and the output port Q of depositor 2 exports the input port D of depositor 6；The input port CK of depositor 6 is inputted by shift-register circuit external input port CK, and the input port D of depositor 6 is inputted by the output port Q of depositor 5, and the output port Q of depositor 6 exports the input port D of depositor 7；The input port CK of depositor 7 is inputted by shift-register circuit external input port CK, and the input port D of depositor 7 is inputted by the output port Q of depositor 6, and the output port Q of depositor 7 exports shift-register circuit external output port Q。
The present embodiment only enumerates a kind of embodiment of this circuit, and other implementation can adopt Fractional-N frequency (N is even number) clock division circuits, corresponding employing N+1 or higher level shift-register circuit。If the set signal R1 effective width of edge detection circuit evolving is less than normal, the realization of more trigger can be inserted between depositor 3 and the depositor 4 in edge detection circuit。
Claims (9)
1. a clock status indicating circuit, it is characterised in that: include clock division circuits, edge correction circuit, edge sense circuit and shift-register circuit；Described clock division circuits is connected with edge correction circuit；Described edge correction circuit is connected with edge sense circuit, shift-register circuit；Described edge sense circuit is connected with shift-register circuit；
Described clock division circuits is for dividing reference clock, and output frequency division clock signal is to edge sense circuit；
Described edge sense circuit access clock to be measured, clock division circuits output sub-frequency clock signal and edge correction circuit output edge correction signal, sub-frequency clock signal carries out edge detection, and output cycle reset signal is to edge correction circuit and shift-register circuit；
Described edge correction circuit accesses reference clock and cycle reset signal is modified obtaining edge correction signal and exports to edge sense circuit；
Described shift-register circuit accesses high level, reference clock and cycle reset signal, carries out internal register displacement and reset operation, exports clock status signal。
2. a kind of clock status indicating circuit according to claim 1, it is characterised in that described clock division circuits includes not gate and depositor；Described non-gate output terminal is connected with the data terminal of depositor, and the outfan of depositor is as the output of clock division circuits, and the input of NAND gate connects；The clock of depositor terminates into reference clock。
3. a kind of clock status indicating circuit according to claim 1, it is characterised in that described edge sense circuit includes three depositors being sequentially connected with and an XOR gate；The clock end of described three depositors all accesses clock to be measured, reset terminal is all connected with the outfan of edge correction circuit, the the first register data end being sequentially connected with is as the input of edge sense circuit and is connected with the outfan of clock division circuits, 3rd depositor outfan is connected with the first input end of XOR gate, second depositor outfan is connected with the second input of XOR gate, and the outfan of XOR gate is as the output of edge sense circuit。
4. a kind of clock status indicating circuit according to claim 1, it is characterized in that described edge sense circuit include not gate and with door, the input of not gate accesses reference clock, outfan is connected with the first input end with door, being connected with the outfan of edge sense circuit with the second input of door, outfan is the output of edge sense circuit。
5. a kind of clock status indicating circuit according to claim 1, it is characterized in that described shift-register circuit includes multiple depositor being linked in sequence, the clock end of each depositor all accesses reference clock, reset terminal is all connected with the outfan of edge sense circuit, the data terminal of first depositor connects high level, and the outfan of last depositor is as the output of shift-register circuit。
6. a clock status indicating means, it is characterised in that comprise the following steps:
A. reference clock is carried out frequency dividing and obtains sub-frequency clock signal by clock division circuits；
B. sub-frequency clock signal is carried out edge detection and obtains cycle reset signal by edge sense circuit；
C. high level is transmitted by shift-register circuit step by step, and when clock to be measured is normal, internal depositor is resetted by cycle reset signal, and shift-register circuit output keeps low level；When clock exception to be measured, cycle reset dropout, shift-register circuit output keeps high level；
D. correction circuit in edge is when clock to be measured stopping and cycle reset abnormal signal, the reference clock negated and cycle reset signal is carried out and generates edge correction signal；
E. exported clock status signal by shift-register circuit, return step a。
7. a kind of clock status indicating circuit according to claim 1, it is characterised in that described edge detection is specially when producing edge, the second depositor being sequentially connected with and the output of the 3rd depositor not etc., do not produce high level by XOR gate。
8. a kind of clock status indicating circuit according to claim 1, it is characterised in that described in carry out frequency dividing for carrying out N-equal duty ratio frequency dividing。
9. a kind of clock status indicating circuit according to claim 1, it is characterised in that in described shift-register circuit, the progression of depositor is more than N+1 level。
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| CN201410679855.1A CN105703745B (en) | 2014-11-24 | 2014-11-24 | A kind of clock status indicating circuit and method |
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| CN201410679855.1A CN105703745B (en) | 2014-11-24 | 2014-11-24 | A kind of clock status indicating circuit and method |
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| CN105703745A true CN105703745A (en) | 2016-06-22 |
| CN105703745B CN105703745B (en) | 2019-01-04 |
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Cited By (1)
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| CN105913822A (en) * | 2016-06-23 | 2016-08-31 | 京东方科技集团股份有限公司 | GOA (Gate Driver on Array) signal judging circuit and judging method, gate driving circuit and display device |
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| WO2009076097A1 (en) * | 2007-12-06 | 2009-06-18 | Rambus Inc. | Edge-based loss-of-signal detection |
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| CN1571957A (en) * | 2001-08-03 | 2005-01-26 | 阿尔特拉公司 | Clock loss detection and switchover circuit |
| US20080054945A1 (en) * | 2006-08-31 | 2008-03-06 | El-Kik Tony S | Method and apparatus for loss-of-clock detection |
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| CN105913822A (en) * | 2016-06-23 | 2016-08-31 | 京东方科技集团股份有限公司 | GOA (Gate Driver on Array) signal judging circuit and judging method, gate driving circuit and display device |
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