CN105701291A - Finite element analysis device, information acquisition method and method for parallel generation of system matrix - Google Patents
Finite element analysis device, information acquisition method and method for parallel generation of system matrix Download PDFInfo
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Abstract
The invention relates to a finite element analysis device, an information acquisition method and a method for parallel generation of a system matrix. The information acquisition method comprises the following steps of S11 taking the first node in a finite element mesh as a current processing node; S12 setting the number of units connected to the current processing node as 0; S13 taking the first unit in the finite element mesh as the current processing unit; S14 judging whether the current processing node exists in the current processing unit; if yes, turning to step S15, and if no, turning to the step S14; S15 adding 1 to the number of units connected to the current processing node; S16 judging whether the current processing unit is the last unit, if yes, turning to the step S17; if no, taking the next unit of the current processing unit as the current processing unit and turning to the step S14; S17 obtaining the number of units connected to the current processing node; and S18 judging whether the current processing node is the last node, if yes, ending; if no, taking the next node of the current processing node as the current processing node and turning to the step S12.
Description
Technical field
It relates to finite element analysis technology field, in particular to a kind of finite element fraction analysis apparatus interior joint relevant information acquisition methods, relate to sytem matrix parallel generation method and a kind of finite element fraction analysis apparatus in a kind of finite element fraction analysis apparatus。
Background technology
Finite element fraction analysis apparatus is (FEA, actual physical system (geometry and load working condition) is simulated by the method FiniteElementAnalysis) utilizing mathematical approach, also utilize element that is simple and that interact, i.e. unit, removes to approach the real system of unlimited unknown quantity by the unknown quantity of limited quantity。
In finite element analysis, an important step is that element stiffness matrix is assembled into system global matrix (often claiming global stiffness matrix or gross mass matrix etc.), in conventional art, the modes adopting unit circulation more, namely calculate unit matrix in order respectively, be assembled into subsequently in system global matrix。
There is substantial amounts of neutral element in the system global matrix that computer is generated by traditional method, thus be referred to as " sparse matrix "。The memory space that this matrix occupies is very big, processes this matrix and need to expend the very long calculating time；And, difficult with external memory exchange, process large-scale finite element analysis problem and have difficulties；Further, it is difficult to realize parallel computation。
It should be noted that in information disclosed in above-mentioned background section only for strengthening the understanding of background of this disclosure, therefore can include not constituting the information to prior art known to persons of ordinary skill in the art。
Summary of the invention
For subproblem of the prior art or whole issue, the disclosure provides a kind of finite element fraction analysis apparatus interior joint relevant information acquisition methods, relates to sytem matrix parallel generation method and a kind of finite element fraction analysis apparatus in a kind of finite element fraction analysis apparatus。
First aspect according to disclosure embodiment, it is provided that a kind of finite element fraction analysis apparatus interior joint correlation unit information getting method, including:
S11. using the 1st node in finite element grid as currently processed node；
S12. the unit number arranging the connection of described currently processed node is 0；
S13. using the 1st unit in finite element grid as current processing unit；
S14. judge whether the node of described current processing unit exists described currently processed node；If it is present go to step S15, if it does not exist, then go to step S14；
S15. the element number connected by currently processed node increases by 1；
S16. judge whether current processing unit is last unit, if it is, go to step S17；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S14；
S17. the element number that currently processed node connects is obtained；
S18. judge whether currently processed node is last node, if it is, terminate；If it is not, then using the next node of currently processed node as currently processed node, and go to step S12。
In a kind of exemplary embodiment of the disclosure, wherein, in described step S18, when judging present node as last node, go to step S21；Described acquisition methods also includes:
S21. using the 1st node in finite element grid as currently processed node；
S22. using the 1st unit in finite element grid as current processing unit；
S23. judge whether the node of described current processing unit exists described currently processed node；If it is present go to step S24, if it does not exist, then go to step S25；
S24. then described current processing unit is designated as the unit being connected with described currently processed node；
S25. judge whether current processing unit is last unit, if it is, go to step S26；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S23；
S26. judge whether currently processed node is last node, if it is, terminate；If it is not, then using the next node of currently processed node as currently processed node, and go to step S22。
In a kind of exemplary embodiment of the disclosure, wherein, in described step S18, when judging present node as last node, go to step S21；Described acquisition methods also includes:
S21. using the 1st node in finite element grid as currently processed node, and n is set equal to 0；
S22. using the 1st unit in finite element grid as current processing unit；
S23. judge whether the node of described current processing unit exists described currently processed node；If it is present go to step S24, if it does not exist, then go to step S25；
S24. then by the unit being connected with described currently processed node that is designated as of described current processing unit, and n increases by 1；
S25. the n element number whether connected is judged less than described currently processed node: if it is less, go to step S26, if it is not, then go to step S27；
S26. judge whether current processing unit is last unit, if it is, go to step S27；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S23；
S27. judge whether currently processed node is last node, if it is, terminate；If it is not, then using the next node of currently processed node as currently processed node, and go to step S22。
Second aspect according to disclosure embodiment, it is provided that sytem matrix parallel generation method in a kind of finite element fraction analysis apparatus, including:
S31. the node total number nNode in computer core number and finite element grid is obtained, and using the 1st core core as currently processed core；
S32., initial row and the termination row of currently processed core sytem matrix to be processed are set；
S33. create thread in currently processed core, perform step S34 to step S38；
S34. corresponding with described initial row in finite element grid node is as currently processed node；
S35. element number and the unit number of the unit that currently processed node connects are obtained, and with the 1st unit in the unit that currently processed node connects for current processing unit；
S36. utilize described current processing unit computing system matrix sub block and be assembled in the sytem matrix row that described currently processed node is corresponding；
S37. judge that whether current processing unit is last unit in the unit that connects of currently processed node, if it is, go to step S38；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S36；
S38. judge whether described currently processed node is the node that described termination row is corresponding, if it is, go to step S39；If it is not, then using the next node of currently processed node as currently processed node, and go to step S35；
S39. using next core of currently processed core as currently processed core, and step S32 is gone to, until last described core processing is complete。
The third aspect according to disclosure embodiment, it is provided that a kind of finite element fraction analysis apparatus, it is characterised in that including:
Processor；And
Memorizer, for storing the executable instruction of described processor；
Wherein said processor is configured to by performing described executable instruction to perform following operation:
S11. using the 1st node in finite element grid as currently processed node；
S12. the unit number arranging the connection of described currently processed node is 0；
S13. using the 1st unit in finite element grid as current processing unit；
S14. judge whether the node of described current processing unit exists described currently processed node；If it is present go to step S15, if it does not exist, then go to step S14；
S15. the element number connected by currently processed node increases by 1；
S16. judge whether current processing unit is last unit, if it is, go to step S17；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S14；
S17. the element number that currently processed node connects is obtained；
S18. judge whether currently processed node is last node, if it is, terminate；If it is not, then using the next node of currently processed node as currently processed node, and go to step S12。
Technical scheme in the exemplary embodiment of the disclosure can have the advantages that
1) " sytem matrix parallel generation method " can shorten the system matrix computation time。
2) " node correlation unit information getting method " can be used for piecemeal and assemble and store external memory, saves internal memory, is beneficial to the extensive problem of process。
3) " node correlation unit information getting method " can be used for the line iteration without generating total system matrix, can process ultra-large problem on a common computer。
4) " node correlation unit information getting method " can be used for generating " dense " matrix, and " sparse " the matrix amount of storage comparing traditional method reduces by 1 to 2 orders of magnitude, calculates speed simultaneously and improves several times, ten several times even tens times。
It should be appreciated that it is only exemplary and explanatory that above general description and details hereinafter describe, the disclosure can not be limited。
Accompanying drawing explanation
Accompanying drawing herein is merged in description and constitutes the part of this specification, it is shown that meets and embodiment of the disclosure, and for explaining the principle of the disclosure together with description。It should be evident that the accompanying drawing in the following describes is only some embodiments of the disclosure, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings。
Fig. 1 schematically shows a kind of finite element matrix。
Fig. 2 schematically shows a kind of finite element grid。
Fig. 3 schematically shows the schematic flow sheet of a kind of finite element fraction analysis apparatus interior joint correlation unit information getting method in disclosure exemplary embodiment。
Fig. 4 schematically shows the structured flowchart of a kind of finite element fraction analysis apparatus interior joint correlation unit information acquisition device in disclosure exemplary embodiment。
Detailed description of the invention
It is described more fully with example embodiment referring now to accompanying drawing。But, example embodiment can be implemented in a variety of forms, and is not understood as limited to example set forth herein；On the contrary, it is provided that these embodiments make the disclosure will more fully and completely, and the design of example embodiment is conveyed to those skilled in the art all sidedly。Described feature, structure or characteristic can be combined in one or more embodiment in any suitable manner。In the following description, it is provided that many details are thus providing fully understanding of embodiment of this disclosure。It will be appreciated, however, by one skilled in the art that can put into practice the technical scheme of the disclosure and omit in described specific detail is one or more, or other method, constituent element, device, step etc. can be adopted。In other cases, it is not shown in detail or describes known solution a presumptuous guest usurps the role of the host and each side of the disclosure is thickened to avoid。
Additionally, accompanying drawing is only the schematic illustrations of the disclosure, it is not necessarily drawn to scale。Accompanying drawing labelling identical in figure represents same or similar part, thus will omit repetition thereof。Some block diagrams shown in accompanying drawing are functional entitys, it is not necessary to must be corresponding with physically or logically independent entity。Software form can be adopted to realize these functional entitys, or in one or more hardware modules or integrated circuit, realize these functional entitys, or in heterogeneous networks and/or processor device and/or microcontroller device, realize these functional entitys。
Technical scheme in this example embodiment can quickly calculate the total and all element number being attached thereto unit of unit that in finite element grid, each node is attached thereto。These information calculated may be used for fast parallel generation " dense " system global matrix, may be simultaneously used for adopting the line iteration being formed without system global matrix to solve ultra-large finite element analysis problem。In this example embodiment, described " dense " system global matrix eliminates all neutral elements, matrix size is made to be greatly reduced, such that it is able to be effectively improved computer to calculate speed, it is achieved block storage system global matrix and then solve the finite element analysis problem of imperial scale。
Finite element matrix is to arrange with the order of node number to carry out arranging。As it is shown in figure 1, be 1 (during more than 1, matrix element can be regarded as submatrix) for ease of understanding the degree of freedom assuming each node, now node number is equal with sytem matrix line number, line number and node number same meaning, under do not repeat。
Iterative sytem matrix is from the first row, and iteration to the last a line, completes an iteration line by line。And if edge generating system matrix limit is iterated avoiding the need for storage total system matrix line by line, ultra-large problem thus just can be solved on a common computer。
When direct solution, a kind of parallel generation sytem matrix method is to distribute the sytem matrix of the of substantially equal line number of number to each thread, and is carried out parallel computation independently by these threads。Such as certain computer has two cores, sytem matrix is 100 rank (n=100), sytem matrix is divided into two pieces, 1-50 behavior first piece, 51-100 behavior second piece, distributing first and assess calculation the first block system matrix calculus, another core is responsible for the system matrix computation of the 2nd piece, and thus the two core can independently calculate the matrix-block being each responsible for concurrently。
As in figure 2 it is shown, finite element grid includes unit 20,21,22 and 23；The numbering of the node on each unit is irregular, as the node number on No. 20 unit is respectively as follows: 14,15,16,17,18,23,24,25。Can be seen that these numberings are random, be not in order。
Therefore by the mode of " node scan ", system stiffness matrix must could be generated line by line。But must could obtain sytem matrix by first computing unit matrix；Namely (the i-th row) stiffness matrix that i-th node is corresponding is calculated, it is necessary to calculating the sub-block relevant with i-node to all cell matrixs that i-node is connected, this is accomplished by the information of the unit being connected with each node, i.e. " node correlation unit information "。
In this example embodiment, described " node correlation unit information " includes the number of unit and the unit number numbering that are connected in finite element grid with each node。In 2 dimension grids as shown in Figure 2, the unit being connected with node " 2 " only has 1, and unit number is 21；The unit being connected with node 15 has 2, unit number respectively 20,21；The unit being connected with node 16 has 3, unit number respectively 20,21,22, and the node being connected with node 25 has 3, unit number respectively 20,22,23。
In this example embodiment, it is provided that finite element fraction analysis apparatus interior joint correlation unit information getting method, it is possible to including:
S11. using the 1st node in finite element grid as currently processed node；
S12. the unit number arranging the connection of described currently processed node is 0；
S13. using the 1st unit in finite element grid as current processing unit；
S14. judge whether the node of described current processing unit exists described currently processed node；If it is present go to step S15, if it does not exist, then go to step S14；
S15. the element number connected by currently processed node increases by 1；
S16. judge whether current processing unit is last unit, if it is, go to step S17；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S14；
S17. the element number that currently processed node connects is obtained；
S18. judge whether currently processed node is last node, if it is, terminate；If it is not, then using the next node of currently processed node as currently processed node, and go to step S12。
Further, in the step S18 of described finite element fraction analysis apparatus interior joint correlation unit information getting method, when judging present node as last node, it is possible to go to step S21；Described acquisition methods also includes:
S21. using the 1st node in finite element grid as currently processed node；
S22. using the 1st unit in finite element grid as current processing unit；
S23. judge whether the node of described current processing unit exists described currently processed node；If it is present go to step S24, if it does not exist, then go to step S25；
S24. then described current processing unit is designated as the unit being connected with described currently processed node；
S25. judge whether current processing unit is last unit, if it is, go to step S26；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S23；
S26. judge whether currently processed node is last node, if it is, terminate；If it is not, then using the next node of currently processed node as currently processed node, and go to step S22。
For reducing amount of calculation, it is also possible to be in the step S18 of described finite element fraction analysis apparatus interior joint correlation unit information getting method, when judging present node as last node, it is possible to go to step S21；Described acquisition methods also includes:
S21. using the 1st node in finite element grid as currently processed node, and n is set equal to 0；
S22. using the 1st unit in finite element grid as current processing unit；
S23. judge whether the node of described current processing unit exists described currently processed node；If it is present go to step S24, if it does not exist, then go to step S25；
S24. then by the unit being connected with described currently processed node that is designated as of described current processing unit, and n increases by 1；
S25. the n element number whether connected is judged less than described currently processed node: if it is less, go to step S26, if it is not, then go to step S27；
S26. judge whether current processing unit is last unit, if it is, go to step S27；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S23；
S27. judge whether currently processed node is last node, if it is, terminate；If it is not, then using the next node of currently processed node as currently processed node, and go to step S22。
Below, above-mentioned steps S11 is illustrated to step S27:
In this example embodiment, total nodes of finite element grid is nNode, and regulation minimum node number is 1, and maximum node number is nNode, and node is from 1 to nNode serial number；Total unit number of finite element grid is nElment, and regulation minimum unit number is 1, and largest unit number is nElment, and unit is from 1 to nElment serial number。
In this example embodiment, it is possible to first data structure is arranged and be configured, mainly include arranging nodal information data structure Node and arranging unit information data structure Element。
For example, arrange nodal information data structure Node (with C++ sign flag) may include that
Namely the number of degrees of freedom, of each node, degree of freedom on a node basis array pointer, coupled number of unit, coupled unit number array pointer, coupled interstitial content and coupled node number array pointer etc. are set。
For example, arrange unit information data structure Element (with C++ sign flag) may include that
Namely node number array pointer of unit class model, unit group number, material number, the nodes of unit, unit etc. is set。
The cell type that wherein unit class model is corresponding can be as shown in Table 1 below:
Table 1 cell type
In this example embodiment, the calculating of node correlation unit information may include that
1) arranging the first one-dimension array ND, the element in array is above-mentioned nodal information data structure；Such as:
ND=newNode [nNode]；
First one-dimension array length is nNode；ND [i]-> nEl in array (i=0 ... nNode-1) store each node contiguous location number。
In this example embodiment, it is also possible to include the first one-dimension array ND is initialized:
ND [i]-> nEl=0 (i=1 ... nNode)；
ND [i]-> ei [j] (j=1 ... ND [i]-> nEl) storage node be connected unit number。
2) arranging the second one-dimension array EL, the element in array is above-mentioned unit information data structure；Such as:
EL=newElement [nElment]；
3) input block information:
EL [i], i=1 ..nElment；
Including:
Unit class model EL [i]-> mat；
Unit material item number EL [i]-> type；
According to unit class model, cell node number is set with reference to table 1: EL [i]-> num；
Cell node number be stored in array EL [i]-> ie [j] (j=1 ..., EL [i]-> num) in。
4) node circulation is carried out
For (iNode=1；INode≤nNode；INode++)
{
5) unit circulation is carried out:
For (iElem=1；IElem≤nElment；IElem++)
{
6) cell node circulation is carried out for each unit iElem:
For (j=1；J≤EL [i]-> num；J++)
{
7) if:
I=EL [i]-> ie [j], then
ND [i]-> nEl increases by 1, i.e. ND [i]-> nEl=ND [i]-> nEl+1；Go to step 5) carry out the calculating of next unit。
8) j increases by 1, returns 6), when j is equal to EL [i]-> num, loop termination, turn lower step。
}
9) iElem increases by 1, returns 5), when iElem is equal to nElment, loop termination, turn lower step。
}
10) space of ND [iNode]-> nEl integer is distributed for array ND [iNode]-> ei
ND [iNode]-> ei=newint [ND [iNode]-> nEl]；
11) iNode increases by 1, returns 4), when iNode is equal to nNode, loop termination, turn lower step。
}
12) node circulation is carried out
For (iNode=1；INode≤nNode；INode++)
{
If n is equal to 0:n=0；
13) unit circulation is carried out:
For (iElem=1；IElem≤nElment；IElem++)
{
If n is more than or equal to ND [i]-> nEl:if (n >=ND [i]-> nEl), go to step 12) carry out next node calculating。
14) cell node circulation is carried out for each unit iElem:
For (j=1；J≤EL [i]-> num；J++)
{
If EL [i]-> ie [j] is equal to iNode:if (EL [i]-> ie [j]-1==iNode), then:
ND [iNode]-> ei [n]=iElem；(showing what node i Node and unit iElem was connected to)
N increases 1:n=n+1；
Go to step 13) carry out next unit calculating
15) j increases by 1, returns 14), when j is equal to EL [i]-> num, loop termination, turn lower step。
16) iElem increases by 1, returns 13), when iElem is equal to nElment, loop termination, turn lower step。
}
17) iNode increases by 1, returns 12), when iNode is equal to nNode, loop termination, turn lower step。
}
Terminate。
Further, this example embodiment additionally provides sytem matrix parallel generation method in a kind of finite element fraction analysis apparatus, including:
S31. the node total number nNode in computer core number and finite element grid is obtained, and using the 1st core core as currently processed core；
S32., initial row and the termination row of currently processed core sytem matrix to be processed are set；
S33. create thread in currently processed core, perform step S34 to step S38；
S34. corresponding with described initial row in finite element grid node is as currently processed node；
S35. element number and the unit number of the unit that currently processed node connects are obtained, and with the 1st unit in the unit that currently processed node connects for current processing unit；Wherein, element number and the unit number of the unit that currently processed node connects is obtained by above-mentioned acquisition methods in this example embodiment；
S36. utilize described current processing unit computing system matrix sub block and be assembled in the sytem matrix row that described currently processed node is corresponding；
S37. judge that whether current processing unit is last unit in the unit that connects of currently processed node, if it is, go to step S38；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S36；
S38. judge whether described currently processed node is the node that described termination row is corresponding, if it is, go to step S39；If it is not, then using the next node of currently processed node as currently processed node, and go to step S35；
S39. using next core of currently processed core as currently processed core, and step S32 is gone to, until last described core processing is complete。
Below, above-mentioned steps S31 is illustrated to step S39:
1) computer core number nCpu, node total number: nNode are obtained。
2) the initial behavior the first row of first core sytem matrix to be processed is set:
NLine1=1；
3) circulation of machine core number it is calculated
For (iCpu=1；ICpu≤nCpu；ICpu++)
{
Calculate the termination row nLine2 of i-th Cpu core sytem matrix to be processed:
NLine2=nLine1+nNode/nCpu；
4) the i-th Cpu thread is created
5) circulate in the i-th Cpu thread interior nodes
For (iNode=nLine1；INode≤nLine2；INode++)
{
6) iNode node correlation unit circulation
For (j=1；J≤ND [iNode]-> nEl；J++)
{
Correlation unit iElement assignment:
IElement=ND [i]-> ei [j]；
7) iElement unit is calculated the cell matrix sub-block relevant to iNode node
8) by 7) the cell matrix sub-block that calculates is assembled into the i-th Node row of sytem matrix
9) j increases by 1:
J=j+1；
It is back to step 6), as j=ND [iNode]-> nEl, turn lower step。
10) iNode increases by 1:
INode=1+iNode；
It is back to step 5), as iNode=nLine2, turn lower step。
11), after iCpu thread terminates, iCpu increases by 1:
ICpu=1+iCpu；
It is back to step 3), as iCpu=nCpu, turn lower step。
12) terminate。
Method in this example embodiment at least has the following advantages, and the following checking having obtained great many of experiments of the disclosure。
1) " sytem matrix parallel generation method " can shorten the system matrix computation time。
2) " node correlation unit information getting method " can be used for piecemeal and assemble and store external memory, saves internal memory, is beneficial to the extensive problem of process。
3) " node correlation unit information getting method " can be used for the line iteration without generating total system matrix, can process ultra-large problem on a common computer。
4) " node correlation unit information getting method " can be used for generating " dense " matrix, and " sparse " the matrix amount of storage comparing traditional method reduces by 1 to 2 orders of magnitude, calculates speed simultaneously and improves several times, ten several times even tens times。
It should be noted that, although describing each step of method in the disclosure with particular order in the accompanying drawings, but, this does not require that or implies must according to this particular order to perform these steps, or the step shown in having to carry out all could realize desired result。Additional or alternative, it is convenient to omit some step, multiple steps are merged into a step and performs, and/or a step is decomposed into multiple step execution etc.。
Fig. 4 illustrates the schematic diagram according to finite element fraction analysis apparatus 400 a kind of in disclosure example embodiment。Such as, device 400 may be provided in a server。With reference to Fig. 4, device 400 includes processing assembly 422, and it farther includes one or more processor and the memory resource representated by memorizer 432, can by the instruction of the execution processing assembly 422 for storing, for instance application program。In memorizer 432 application program of storage can include one or more each corresponding to the module of one group of instruction。It is configured to perform instruction additionally, process assembly 422, to perform said method。
Device 400 can also include a power supply module 426 and be configured to perform the power management of device 400, and a wired or wireless network interface 450 is configured to be connected to device 400 network and input and output (I/O) interface 458。Device 400 can operate based on the operating system being stored in memorizer 432, for instance WindowsServerTM, MacOSXTM, UnixTM, LinuxTM, FreeBSDTM or similar。
Those skilled in the art, after considering description and putting into practice invention disclosed herein, will readily occur to other embodiment of the disclosure。The application is intended to any modification of the disclosure, purposes or adaptations, and these modification, purposes or adaptations are followed the general principle of the disclosure and include the undocumented known general knowledge in the art of the disclosure or conventional techniques means。Description and embodiments is considered only as exemplary, and the true scope of the disclosure and spirit are pointed out by claim below。
It should be appreciated that the disclosure is not limited to precision architecture described above and illustrated in the accompanying drawings, and various amendment and change can carried out without departing from the scope。The scope of the present disclosure is only limited by appended claim。
Claims (5)
1. a finite element fraction analysis apparatus interior joint correlation unit information getting method, it is characterised in that including:
S11. using the 1st each and every one node in finite element grid as currently processed node；
S12. the unit number arranging the connection of described currently processed node is 0；
S13. using the 1st unit in finite element grid as current processing unit；
S14. judge whether the node of described current processing unit exists described currently processed node；If it is present go to step S15, if it does not exist, then go to step S14；
S15. the element number connected by currently processed node increases by 1；
S16. judge whether current processing unit is last unit, if it is, go to step S17；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S14；
S17. the element number that currently processed node connects is obtained；
S18. judge whether currently processed node is last node, if it is, terminate；If it is not, then using the next node of currently processed node as currently processed node, and go to step S12。
2. finite element fraction analysis apparatus interior joint correlation unit information getting method according to claim 1, it is characterised in that wherein, in described step S18, when judging present node as last node, go to step S21；Described acquisition methods also includes:
S21. using the 1st node in finite element grid as currently processed node；
S22. using the 1st unit in finite element grid as current processing unit；
S23. judge whether the node of described current processing unit exists described currently processed node；If it is present go to step S24, if it does not exist, then go to step S25；
S24. then described current processing unit is designated as the unit being connected with described currently processed node；
S25. judge whether current processing unit is last unit, if it is, go to step S26；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S23；
S26. judge whether currently processed node is last node, if it is, terminate；If it is not, then using the next node of currently processed node as currently processed node, and go to step S22。
3. finite element fraction analysis apparatus interior joint correlation unit information getting method according to claim 1, it is characterised in that wherein, in described step S18, when judging present node as last node, go to step S21；Described acquisition methods also includes:
S21. using the 1st node in finite element grid as currently processed node, and n is set equal to 0；
S22. using the 1st unit in finite element grid as current processing unit；
S23. judge whether the node of described current processing unit exists described currently processed node；If it is present go to step S24, if it does not exist, then go to step S25；
S24. then by the unit being connected with described currently processed node that is designated as of described current processing unit, and n increases by 1；
S25. the n element number whether connected is judged less than described currently processed node: if it is less, go to step S26, if it is not, then go to step S27；
S26. judge whether current processing unit is last unit, if it is, go to step S27；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S23；
S27. judge whether currently processed node is last node, if it is, terminate；If it is not, then using the next node of currently processed node as currently processed node, and go to step S22。
4. sytem matrix parallel generation method in a finite element fraction analysis apparatus, it is characterised in that including:
S31. the node total number nNode in computer core number and finite element grid is obtained, and using the 1st core core as currently processed core；
S32., initial row and the termination row of currently processed core sytem matrix to be processed are set；
S33. create thread in currently processed core, perform step S34 to step S38；
S34. corresponding with described initial row in finite element grid node is as currently processed node；
S35. element number and the unit number of the unit that currently processed node connects are obtained, and with the 1st unit in the unit that currently processed node connects for current processing unit；Wherein, element number and the unit number of the unit that currently processed node connects is obtained by the method described in claims 1 to 3 any one；
S36. utilize described current processing unit computing system matrix sub block and be assembled in the sytem matrix row that described currently processed node is corresponding；
S37. judge that whether current processing unit is last unit in the unit that connects of currently processed node, if it is, go to step S38；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S36；
S38. judge whether described currently processed node is the node that described termination row is corresponding, if it is, go to step S39；If it is not, then using the next node of currently processed node as currently processed node, and go to step S35；
S39. using next core of currently processed core as currently processed core, and step S32 is gone to, until last described core processing is complete。
5. a finite element fraction analysis apparatus, it is characterised in that including:
Processor；And
Memorizer, for storing the executable instruction of described processor；
Wherein said processor is configured to by performing described executable instruction to perform following operation:
S11. using the 1st node in finite element grid as currently processed node；
S12. the unit number arranging the connection of described currently processed node is 0；
S13. using the 1st unit in finite element grid as current processing unit；
S14. judge whether the node of described current processing unit exists described currently processed node；If it is present go to step S15, if it does not exist, then go to step S14；
S15. the element number connected by currently processed node increases by 1；
S16. judge whether current processing unit is last unit, if it is, go to step S17；If it is not, then using the next unit of current processing unit as current processing unit, and go to step S14；
S17. the element number that currently processed node connects is obtained；
S18. judge whether currently processed node is last node, if it is, terminate；If it is not, then using the next node of currently processed node as currently processed node, and go to step S12。
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| CN111008497A (en) * | 2019-12-06 | 2020-04-14 | 集美大学 | Generation method of finite element total stiffness matrix and terminal |
| CN112434451A (en) * | 2020-10-28 | 2021-03-02 | 西安交通大学 | Finite element analysis method based on block parallel computation |
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