CN105699877B - The stepping automatic testing equipment and method of SOC chip leakage current - Google Patents
The stepping automatic testing equipment and method of SOC chip leakage current Download PDFInfo
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- CN105699877B CN105699877B CN201610093767.2A CN201610093767A CN105699877B CN 105699877 B CN105699877 B CN 105699877B CN 201610093767 A CN201610093767 A CN 201610093767A CN 105699877 B CN105699877 B CN 105699877B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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Abstract
The present invention provides a kind of the stepping automatic testing equipment and method of SOC chip leakage current, including scene setting storage unit, gate valve value storage unit, scan control module, electric current judging unit, EFUSE programmings control unit, EFUSE circuit units；The scene setting storage unit connects scan control module；Gate valve value storage unit connects electric current judging unit；Scan control module connects the clamping unit ring of each power domain by the effective control signal wire of clamper, and the MTCOMS power switch rings of each power domain are connected by powered-down control signal wire；Scan control module is also connected with test mode signal and the electric current judging unit；Each clamping unit ring connects electric current judging unit by a galvanometer；Electric current judging unit, EFUSE programmings control unit, EFUSE circuit units are sequentially connected.The present invention is that chip is tested in CP test phases, each power domain is individually tested and recorded.
Description
Technical Field
The invention relates to a grading automatic testing device and a grading automatic testing method for SOC chip leakage current.
Background
The leakage current is a very small current flowing through the PN junction when it is off. After D-S is set at forward bias, G-S is reverse bias, and the conducting channel is opened, current flows from D to S. In practice, however, free electrons are attached to the SIO due to the presence of the free electrons2And N +, resulting in D-S leakage current. The popular explanation is that under the state that the chip is powered on but does not work, certain leakage current can still be generated due to the electrical characteristics of the PN junction, when the chip scale is small, the leakage current is small, and along with the rapid increase of the chip scale, the current leakage current reaches a considerable degree.
With the gradual expansion of the scale of the SOC chip, the leakage current of the SOC chip is also more and more concerned. When the chip scale is small, the leakage current is small, along with the rapid increase of the chip scale, the current leakage current reaches a very objective degree, and because many mobile devices have very high requirements on the power consumption of the chip leakage current, how to screen out the chip with the large leakage current in the test process is very important.
The current chip testing method is that after the chip packaging is finished, the chip is placed on a PCB, the chip is effectively in a non-working state by controlling a reset pin, and the leakage current is tested by testing the power consumption of a testing current source, so that the method has obvious defects:
1. if the time for finding the problem is too late, the chip is packaged, and if the chip is scrapped, the packaging cost is wasted;
2. the leakage current can only be tested by a whole chip, and the leakage current can not be separately and finely tested to the power domain of each chip, if the leakage current is large, the current position of the problem with large current can not be positioned, and the leakage current can not be fed back to a chip production factory for targeted optimization treatment;
3. the test work is finished manually, and cannot be finished automatically, so that risks are introduced, and the workload is increased.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a device and a method for automatically testing the leakage current of an SOC chip in a grading manner, which are used for testing the chip in a CP testing stage, and can individually test and record each power domain of the chip and automatically output a testing result.
The device of the invention is realized as follows: a grading automatic testing device for leakage current of an SOC chip is provided with a plurality of power domains, a MTCMOS power switch ring is arranged outside each power domain, a clamping unit ring is arranged outside each MTCMOS power switch ring, and the grading automatic testing device comprises a scene setting storage unit, a gate valve value storage unit, a scanning control module, a current judgment unit, an EFUSE programming control unit and an EFUSE circuit unit;
the scene setting storage unit is connected with the scanning control module; the gate threshold value storage unit is connected with the current judgment unit;
the scanning control module is connected with each clamping unit ring through a clamping effective control signal line and is connected with each MTCMOS power switch ring through a power-off control signal line; and is connected to the reset control ends of all the register units in the corresponding power domain circuit through a reset control signal wire;
the scanning control module is also connected with a test mode signal and the current judging unit;
each clamping unit ring is connected with the current judging unit through an ammeter;
the current judging unit, the EFUSE programming control unit and the EFUSE circuit unit are sequentially connected; and the current judging unit also outputs a power domain indicating bit signal with overhigh leakage current.
Further, the scene setting storage unit stores the number of power consumption scenes to be tested and the switching conditions of all power domains under each power consumption scene; the gate valve value storage unit stores leakage current gate threshold values in various low-power consumption scenes, and when the leakage current of the chip in the low-power consumption scene exceeds the value, the power consumption value of the chip in the low-power consumption scene exceeds the standard.
Furthermore, the test mode signal is controlled by the CP tester and input to the scan control module, and when the test mode signal is at a high level, the test is started.
The method of the invention is realized as follows: a grading automatic test method for SOC chip leakage current is characterized in that: the stepped automatic test device for leakage current of SOC chip according to claim 1, wherein the test procedure is as follows:
(1) configuring the scene setting storage unit and the gate valve value storage unit in a chip;
(2) after receiving the test effective signal, the scanning control module reads a power consumption scene and corresponding power domain switch configuration from the scene setting storage unit, and starts a test from a first scene:
(3) when the test is started, the power supply of all power domains is normally opened, and the reset control signal of the circuit is set to be effective;
then setting a clamp effective control signal corresponding to the power domain needing power-off as effective, and clamping a boundary signal value corresponding to the power domain into a fixed value;
after the clamp control is finished, setting a power-off control signal of a power domain needing power-off as valid, and carrying out power supply turn-off operation on an MTCMOS power switch ring of the power domain, wherein the power supply of other power domains is normal; then waiting for a period of time to allow the current to stabilize;
then, the current judging unit reads the current measured value of the corresponding ammeter of each power domain and the power consumption threshold value of the power consumption scene in the gate valve value storage unit, compares the accumulated value of the current of each power domain with the power consumption threshold value of the power consumption scene, if the accumulated value is smaller than the threshold value, the power consumption performance of the chip in the power consumption scene meets the product requirement and is qualified, otherwise, the chip is unqualified;
then, the current judging unit sends the judging result to the outside of the chip through a leakage current over-high indicating bit signal and simultaneously sends the judging result to the efuse programming control unit to program the bit which is qualified or not in the power consumption scene in the efuse circuit unit, and the test is also finished;
(4) and (4) returning to the step (3), and starting the test of the next power consumption scene until the test of all the power consumption scenes is completed.
Further, the test mode signal is controlled by the CP test machine and input to the scanning control module, and when the test mode signal is at a high level, the test is started; in the testing process, the CP testing machine can always observe a signal of an over-high indication bit of leakage current, if the signal is changed into effective, the chip is indicated to be an unqualified product, and the chip is screened out on the CP testing machine, or the chip is judged and screened out by reading a corresponding efuse bit at a later stage.
Further, the scan control module is implemented by a state machine circuit.
The invention has the following advantages:
1. PLL (phase Locked Loop) can be tested at the CP test stage of the chip, and problems are found at the earliest stage after the chip leaves a factory, so that waste is reduced to the minimum; cp (chip probe) refers to a process of performing performance and function tests on a chip by pricking a probe card on a chip pin at a wafer stage before the chip is packaged, which is sometimes referred to as ws (wafer sort);
2. each power domain of the chip can be tested and recorded independently, once the leakage current is found to be large, the position of a circuit with a large current problem can be positioned, and the circuit can be directly fed back to a chip production factory for targeted process optimization;
3. performing automatic scene-dividing traversal power consumption test to obtain power consumption data under various scenes, and automatically storing the power consumption data;
4. and the test result is automatically calculated and judged, so that the risk and workload of manual judgment are saved.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
FIG. 1 is a block diagram of the present invention showing the structure of an automatic SOC leakage current grading test device.
Detailed Description
As shown in fig. 1, the present invention provides a stepping automatic testing apparatus for leakage current of An SOC chip, the SOC chip has a plurality of power domains (a1, a2 … An), each power domain is externally provided with a MTCMOS power switch ring B, each MTCMOS power switch ring B is externally provided with a clamping unit ring C, the stepping automatic testing apparatus 100 includes a scene setting storage unit 101, a gate valve value storage unit 102, a scan control module 103, a current judgment unit 104, An EFUSE programming control unit 105, and An EFUSE circuit unit 106;
the scene setting storage unit 101 is connected with the scanning control module 103; the gate valve value storage unit 102 is connected with a current judgment unit 104;
the scan control module 103 may be implemented by a state machine circuit, which is connected to each of the clamp cell rings C through clamp active control signal lines 103C and to each of the MTCMOS power switch rings B through power-off control signal lines 103B; and is connected to the reset control terminals (not shown) of all the register units in the corresponding power domain circuit through a reset control signal line 103D;
the scan control module 103 is further connected to a test mode signal and the current determination unit 104;
each clamping unit ring C is connected with the current judging unit 104 through a current meter 107;
the current judgment unit 104, the EFUSE programming control unit 105 and the EFUSE circuit unit 106 are connected in sequence; and the current determination unit 104 also outputs a leakage current over-high power domain indicator bit signal.
Wherein,
the scene setting storage unit 101 stores the number of power consumption scenes to be tested and the switching conditions of all power domains in each power consumption scene;
the gate threshold storage unit 102 stores a leakage current gate threshold in each low power consumption scenario, and when the leakage current of the chip in the power consumption scenario exceeds the value, it indicates that the power consumption value of the chip in the low power consumption scenario exceeds the standard. For example, a chip has abcd 4 power domains, and power consumption scenes in operation are divided into 3 types:
in a power consumption scene 1, a power supply domain a is powered on, and a power supply domain bcd is powered off;
a power consumption scene 2, a power supply domain bc is powered on, and a power supply domain ad is powered off;
power consumption scene 3, power domain abcd is completely off;
the scene setting storage unit 101 stores therein the power domain switching condition corresponding to each scene and 3 scene values to be tested.
The scanning control module 103 is used for controlling each power domain and peripheral circuits thereof to cooperate to perform leakage current test and record;
the current judgment unit 104 is configured to read a current measurement value of the ammeter 107 corresponding to each power domain and a power consumption threshold value of the power consumption scenario in the gate valve value storage unit 102, and compare an accumulated value of the current of each power domain with the power consumption threshold value of the power consumption scenario;
the EFUSE programming control unit 105 is configured to program a bit that is qualified or not in the power consumption scenario in the EFUSE circuit unit 106;
the EFUSE circuit unit 106 is used for
The invention relates to a grading automatic test method of SOC chip leakage current, which utilizes the grading automatic test device 100 of SOC chip leakage current to test, and the test process is as follows:
(1) configuring the scene setting storage unit 101 and the gate valve value storage unit 102 in a chip;
(2) after receiving the test valid signal, the scan control module 103 starts to control each power domain and its peripheral circuits to cooperate to perform leakage current test and record; the scanning control module reads a power consumption scene and a corresponding power domain switch configuration from a scene setting storage unit, and starts testing from a first scene:
(3) when the test is started, the power supply of all power domains is normally opened, and the reset control signal of the circuit is set to be effective;
then setting a clamp effective control signal corresponding to the power domain needing power-off as effective, and clamping a boundary signal value corresponding to the power domain into a fixed value;
after the clamp control is finished, setting the power-off control signal of the power domain needing power-off as valid, and carrying out power supply turn-off operation on the MTCMOS power switch ring C of the power domain, wherein the power supply of other power domains is normal; then waiting for a period of time to allow the current to stabilize;
then, the current determination unit 104 reads the current measurement value of the ammeter 107 corresponding to each power domain and the power consumption threshold value of the power consumption scene in the gate valve value storage unit 102, compares the accumulated value of the current of each power domain with the power consumption threshold value of the power consumption scene, and if the accumulated value is smaller than the power consumption threshold value, it indicates that the power consumption performance of the chip in the power consumption scene meets the product requirement and is qualified, otherwise, it is unqualified;
then, the current determination unit 104 sends the determination result to the outside of the chip through the leakage current over-high indication bit signal 104A and simultaneously sends the determination result to the EFUSE programming control unit 105 to program the bit in the EFUSE circuit unit 106, which is qualified in the power consumption scenario, and the test is also completed;
(4) and (4) returning to the step (3), and starting the test of the next power consumption scene until the test of all the power consumption scenes is completed.
The test mode signal is controlled by the CP test machine and input to the scanning control module, and the test is started when the test mode signal is at a high level; in the testing process, the CP testing machine can always observe a signal of an over-high indication bit of leakage current, if the signal is changed into effective, the chip is indicated to be an unqualified product, and the chip is screened out on the CP testing machine, or the chip is judged and screened out by reading a corresponding efuse bit at a later stage.
Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.
Claims (6)
1. The utility model provides a stepping automatic testing arrangement of SOC chip leakage current, the SOC chip has a plurality of power domains, is equipped with a MTCMOS switch ring outside every power domain, is equipped with a clamping unit ring outside every MTCMOS switch ring, its characterized in that: the automatic grading test device comprises a scene setting storage unit, a gate valve value storage unit, a scanning control module, a current judgment unit, an EFUSE programming control unit and an EFUSE circuit unit;
the scene setting storage unit is connected with the scanning control module; the gate threshold value storage unit is connected with the current judgment unit;
the scanning control module is connected with each clamping unit ring through a clamping effective control signal line and is connected with each MTCMOS power switch ring through a power-off control signal line; and is connected to the reset control ends of all the register units in the corresponding power domain circuit through a reset control signal wire;
the scanning control module is also connected with a test mode signal and the current judging unit;
each clamping unit ring is connected with the current judging unit through an ammeter;
the current judging unit, the EFUSE programming control unit and the EFUSE circuit unit are sequentially connected; and the current judging unit also outputs a power domain indicating bit signal with overhigh leakage current.
2. The apparatus of claim 1, wherein the apparatus comprises:
the scene setting storage unit stores the number of power consumption scenes to be tested and the switching conditions of all power domains under each power consumption scene;
the gate valve value storage unit stores leakage current gate threshold values in various low-power consumption scenes, and when the leakage current of the chip in the low-power consumption scene exceeds the value, the power consumption value of the chip in the low-power consumption scene exceeds the standard.
3. The apparatus of claim 1, wherein the apparatus comprises: the test mode signal is controlled by the CP test machine and input to the scanning control module, and the test is started when the test mode signal is at a high level.
4. A grading automatic test method for SOC chip leakage current is characterized in that: the stepped automatic test device for leakage current of SOC chip according to claim 1, wherein the test procedure is as follows:
(1) configuring the scene setting storage unit and the gate valve value storage unit in a chip;
(2) after receiving the test effective signal, the scanning control module reads a power consumption scene and corresponding power domain switch configuration from the scene setting storage unit, and starts a test from a first scene:
(3) when the test is started, the power supply of all power domains is normally opened, and the reset control signal of the circuit is set to be effective;
then setting a clamp effective control signal corresponding to the power domain needing power-off as effective, and clamping a boundary signal value corresponding to the power domain into a fixed value;
after the clamp control is finished, setting a power-off control signal of a power domain needing power-off as valid, and carrying out power supply turn-off operation on an MTCMOS power switch ring of the power domain, wherein the power supply of other power domains is normal; then waiting for a period of time to allow the current to stabilize;
then, the current judging unit reads the current measured value of the corresponding ammeter of each power domain and the power consumption threshold value of the power consumption scene in the gate valve value storage unit, compares the accumulated value of the current of each power domain with the power consumption threshold value of the power consumption scene, if the accumulated value is smaller than the threshold value, the power consumption performance of the chip in the power consumption scene meets the product requirement and is qualified, otherwise, the chip is unqualified;
then, the current judging unit sends the judging result to the outside of the chip through a leakage current over-high indicating bit signal and simultaneously sends the judging result to the efuse programming control unit to program the bit which is qualified or not in the power consumption scene in the efuse circuit unit, and the test is also finished;
(4) and (4) returning to the step (3), and starting the test of the next power consumption scene until the test of all the power consumption scenes is completed.
5. The method of claim 4, wherein the step-by-step automatic testing of SOC chip leakage current comprises: the test mode signal is controlled by a CP test machine and input to the scanning control module, and the test is started when the test mode signal is at a high level; in the testing process, the CP testing machine can always observe a signal of an over-high indication bit of leakage current, if the signal is changed into effective, the chip is indicated to be an unqualified product, and the chip is screened out on the CP testing machine, or the chip is judged and screened out by reading a corresponding efuse bit at a later stage.
6. The method of claim 4, wherein the step-by-step automatic testing of SOC chip leakage current comprises: the scanning control module is realized by a state machine circuit.
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| CN102545574A (en) * | 2010-12-27 | 2012-07-04 | 北京中电华大电子设计有限责任公司 | Low-power consumption power network designing method for system on chip (SOC) chip |
| CN103439570A (en) * | 2013-08-30 | 2013-12-11 | 深圳市度信科技有限公司 | Chip leakage current testing system |
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| US7417469B2 (en) * | 2006-11-13 | 2008-08-26 | International Business Machines Corporation | Compensation for leakage current from dynamic storage node variation by the utilization of an automatic self-adaptive keeper |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102545574A (en) * | 2010-12-27 | 2012-07-04 | 北京中电华大电子设计有限责任公司 | Low-power consumption power network designing method for system on chip (SOC) chip |
| CN103439570A (en) * | 2013-08-30 | 2013-12-11 | 深圳市度信科技有限公司 | Chip leakage current testing system |
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