CN105680992A - Construction method of coset partition (n, n(n-1), n-1) permutation group code and code set generator thereof - Google Patents

Abstract

The invention discloses a construction method of a coset partition (n, n(n-1), n-1) permutation group code. The coset partition (n, n(n-1), n-1) permutation group code has error correcting capability d-1 and has strong inhibiting capability in simultaneous channel disturbance on the mixed multi-frequency noise and signal fading. The construction method of the coset partition (n, n(n-1), n-1) permutation group code is as follows: when a code length n is a prime number, aiming at a permutation code family with minimum distance of n-1 and code set size of n(n-1), firstly using FOMRLA to compute n-1 track head permutation codeword, and then using FORMULA to enumerate other codewords in the code set. The invention further provides a code set generator of the corresponding (n, n(n-1), n-1) permutation group code. The coset partition (n, n(n-1), n-1) permutation group code provided by the invention is an algebraic structure code, n-1 codeword in a track head array can be used for replacing the multiplication of positive integer through the adoption of a simple summing unit and (modn) calculator; a cyclic shift composite operation function with good definition is used for replacing the compositional operation of a cyclic subgroup to the track head permutation, and a cyclic shift register bank is used for realize the operation from the cyclic group to the permutation.

Description

Construction method of coset division (n, n (n-1), n-1) permutation group code and code set generator thereof

Technical Field

The invention belongs to the technical field of channel coding in communication transmission, and particularly relates to a construction method of a coset partition (n, n (n-1), n-1) permutation group code and a code set generator thereof.

Background

The situation that multiple kinds of interference such as multipath fading, narrow-band permanent noise, broadband pulse noise, colored background noise and the like coexist or occur simultaneously exists on a power line channel, and the situation that the multiple kinds of interference occur simultaneously rarely occurs on a wireless channel and a wired channel, so that the reliability of information transmission is hard to guarantee if the existing mature technologies of wireless and wired communication are directly moved to a power line carrier communication channel. From this point of view, it is necessary to provide a solution of error correction code with higher reliability requirement for the problem of multi-form and multi-frequency interference in power line carrier communication. In addition to the power line carrier channel, other wireless and wired channels in which various forms and various frequency interferences occur simultaneously also need to use a more reliable error correction code scheme.

Vinck introduced permutation codes into power line carrier communication in 2000, published article "code modulation for power line communications", aeuint.j.electron.com., vol.54, No.1, pp:45-49,2000 ", and proposed a solution for power line carrier code modulation combining M-dimensional FSK modulation and permutation codes. According to the scheme, at the transmitter end, time diversity and frequency diversity are introduced simultaneously by utilizing the nonlinear redundancy of the permutation codes, so that the capacity of resisting multi-frequency and fading interference is enhanced; at the receiver end, a constant envelope demodulation algorithm can be adopted to detect the received signal, and a simple noncoherent demodulation scheme is naturally formed. Of particular concern is that Vinck analyzes a group of permutation codes with the code length of 4 to obtain a permutation code with a special structure, which has the error correction capability of d-1, but not the permutation code with the special structureAnd (4) concluding. However, Vinck does not provide an effective replacement code construction method, and the replacement code with the error correction capability of d-1 is not practically applied at present, and the key reason of slow development is that the algebraic structure design method of the replacement code is less, and particularly, the hardware executable scheme is not effectively solved.

Disclosure of Invention

The invention provides a construction method of a coset division (n, n (n-1), n-1) permutation group code and a code set generator thereof, in particular to a permutation code algebraic structure design method and a code set enumerator of a code length n, a minimum distance n-1, a code number n (n-1) and an error correction capability d-1-n-2. Aiming at the condition that multiple interferences such as multipath fading, narrow-band permanent noise, broadband pulse noise, colored background noise and the like in power line carrier communication coexist or occur simultaneously, the invention provides a high-reliability error correction code design scheme for effectively resisting the combined interferences. In addition, the permutation group code provided by the invention also has stronger inhibition capability for multi-frequency interference and man-made malicious frequency interference in wireless communication. In summary, in an operating environment where the data transmission rate requirement is not high but various mixed frequency interference and deep fading exist simultaneously, the coset division (n, n (n-1), n-1) permutation group code provided by the invention has protection capability on transmitted signals.

To achieve the above object, according to one aspect of the present invention, there is provided a method for constructing a coset-partitioned (n, n (n-1), n-1) permutation group code having a code length n and a minimum distance n-1 and having a code set size n (n-1) by constructing a permutation group code having a code length n and a minimum distance n (n-1) The code set P_n＝C_nO_nBy cyclically permuting subgroup C_nAnd a different subgroup O_nAre cosets of each other; the code set P_n＝{{C_no₁},{C_no₂},...,{C_no_n-1Is permutation subgroup C_nWill P_nDivided into n-1 cosets, each coset { C_no_αIs formed by a substitution o_αOrbital or circular Latin Square (C-LS); the code set Is each permutation code word p_βαFrom subgroup C_nSubstitution of (1) to (c)_βAnd subgroup O_nSubstitution of (1) to_αThe synthesis operation of (a) yields, α ═ 1,2,. n-1 and β ═ 1,2,. n.

According to another aspect of the present invention, there is also provided a code set generator of a coset-partitioned (n, n (n-1), n-1) permutation group code, including a track head array generator, a ROM memory, and a bidirectional cyclic shift register set, wherein:

the track head array generator is used for executingCalculating to generate n-1 track head permutations;

the ROM stores the output result of the track head array generator and the output result of the bidirectional cyclic shift register group;

the bidirectional cyclic shift register set executes₁)^n-1Or (r)_n)^n-1For one permutation operation, realize each track head permutation o_αTrack of (l { (l)₁)^n-1o_αEither (r)_n)^n-1o_αComputation and code set of { (l)₁)^n-1O_nEither (r)_n)^n-1O_nCalculation of, α ═ 1, 2.., n-1.

Has the advantages that: the coset division (n, n (n-1), n-1) permutation group code provided by the invention is an algebraic structure code, the track head permutation code word in the code set can be completed by simple addition operation and (modn) operation without complex synthesis operation, and the whole code set can be realized by using circular shift register hardware; the error correction capability of the multi-system error correction code class is d-1, which is the error correction capability of the traditional multi-system error correction code classTwice of; when combined with the MFSK modulation technique, the receiver end can employ a simple non-coherent constant envelope demodulation technique for demodulation; the reliability of signal transmission can be ensured on an interference channel in which mixed multi-frequency noise and deep fading exist simultaneously.

Drawings

FIG. 1 is a block diagram of a (n, n (n-1), n-1) permuting group code generator circuit according to the present invention;

FIG. 2 is a schematic diagram of a track head array generating circuit according to the present invention;

FIG. 3 is a diagram of a ROM memory according to the present invention;

FIG. 4 is a diagram of an n-ary bidirectional circular shift register set according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

Basic principle

This section describes the basic principle of coset partitioning (n, n (n-1), n-1) permutated group codes to which the present invention relates.

The coded symbols may take values in two finite fields, i.e. setIs an n-order finite field containing 0 elementIs an n-order finite positive integer field that does not contain 0 elements, and is also a cyclic group of order n. Is defined inOrAll n of the n elements on! The set formed by the permutations is called a symmetric group, with S_n＝{π₁,...,π_k,...,π_n！Denotes, where each element can be replaced by a permutation of π_k＝[a₁...a_i...a_n]To indicate that each permuted element isOrThe degree (dimension) of each permutation is | π_kN, the potential (order) of the symmetry group is | S_n| n! . Let pi₀＝e＝[a₁a₂...a_n]＝[01...n-1]Or pi₀＝e＝[a₁a₂...a_n]＝[12...n]Represents a symmetric group S_nA unit cell of (a). [ a ] A₁a₂...a_n]Denotes S_n(ii) replacement of (a)₁a₂...a_n) A permutation operator is represented.

If the group is H mu S_nIs generated from a single element, i.e. there is an element x ∈ H such that there is a resultant operationThen H is a cyclic permutation group denoted as H < x > and is said to be produced by x, or x is the generator of H.

Let γ ═ γ₂Is a cyclic permutation group consisting of n permutation operators, which generates the child γ₂＝(a₂a₃...a_na₁) Its potential is | γ | ═ n. If the operator set gamma is made to be < gamma₂Acting on a permutation pi ═ a₁...a_i...a_n]To obtain { γ pi } ═ { { γ { }₂,γ₃,...,γ_n,γ₁}[a₁...a_i...a_n]}＝{〈γ₂〉π}＝{{γ₂,γ₂ ²,...,γ₂ ^n-1,γ₂ ⁿ}[a₁...a_i...a_n]Then { γ pi } is an orbital that contains the permutation pi under the action of the cyclic group γ, and the number of elements contained in this orbital is | { γ pi } | ═ n.

The following three theorems or lemmas provide the basic structure of coset partitioning (n, n (n-1), n-1) permutation group codes without evidence.

Introduction 1[ circulation group C_nStructure of (1)]: is provided with C_n＝{γπ}＝{〈γ₂〉[a₁a₂...a_n]Y is specified as { y ═ y }₁,γ₂,...,γ_nEach subscript value of } and C_nThe index value of the first element of each permutation remains the same, i.e. c₁＝γ₁π＝c₂ ⁿ＝γ₂ ⁿπ＝(a₂a₃...a_na₁)ⁿ[a₁a₂...a_n]＝[a₁a₂...a_n],c₂＝γ₂π＝[a₂a₃...a_na₁]，c₃＝γ₃π＝c₂ ²＝γ₂ ²π＝(a₂a₃...a_na₁)²[a₁a₂...a_n]＝[a₃a₄...a_na₁a₂],…,c_n＝γ_nπ＝c₂ ^n-1＝γ₂ ^n-1π＝(a₂a₃...a_na₁)^n-1[a₁a₂...a_n]＝[a_na₁a₂...a_n-1]Then C_n＝{c₁,c₂,...,c_n}＝〈c₂〉＝{〈γ₂Is S_nIs also a cyclic permutation group, the minimum distance of which isIts potential is | C_n|＝n。

Theorem 2[ O ]_nStructure of (1)]: let O_nIs a permutation array of (n-1) × n or a set of n-1 permutationsWherein o is₁＝[12...n]Is a unit permutation, α ═ 1, 2., n-1 is permutation array O_nIs also the set O_nIf and only if 1) n is a prime number, 2) for all α,1,2_nIs S_nSubgroup of, array O_nIs all n, and O_nIs a minimum distance ofIts potential is | O_n|＝n-1。

Theorem 3[ by C_nAnd O_nConstructing a permutated group code P_n]: for any prime number n, let P_n＝{p₁₁,...,p_βα,...,p_n(n-1)Is S_nA non-trivial subgroup of (a). With C_nAnd O_nTo construct P_nThat is to say have Wherein c is_βοo_αRepresents a substitution c_βAnd substitution o_αThe synthesis operation of (1). If C is present_n∩O_n＝e＝[12...n]Then P_nIs C_nAnd O_nMutual coset permutation group code, P_nThe minimum Hamming distance of isIts potential is | P_n|＝n(n-1)。

Example 1: when n is 5, the following C is obtained according to the theorem 1₅，

$C_5=\left\{\begin{array}{c}{c}_1,\\ c_2,\\ c_3,\\ c_4,\\ c_5\end{array}\right\}=<c_2>=\left\{\begin{array}{c}{c_2}^5,\\ {c_2}^1,\\ {c_2}^2,\\ {c_2}^3,\\ {c_2}^4\end{array}\right\}=<{\mathrm{\&gamma;}}_2\mathrm{\&pi;}>=\left(\begin{array}{c}{{\mathrm{\&gamma;}}_2}^5\mathrm{\&pi;},\\ {{\mathrm{\&gamma;}}_2}^1\mathrm{\&pi;},\\ {{\mathrm{\&gamma;}}_2}^2\mathrm{\&pi;},\\ {{\mathrm{\&gamma;}}_2}^3\mathrm{\&pi;},\\ {{\mathrm{\&gamma;}}_2}^4\mathrm{\&pi;}\end{array}\right)=\left\{\begin{array}{c}{\left(a_2{a}_3{a}_4{a}_5{a}_1\right)}^5\&lsqb;a_1{a}_2{a}_3{a}_4{a}_5\&rsqb;,\\ \left(a_2{a}_3{a}_4{a}_5{a}_1\right)\&lsqb;a_1{a}_2{a}_3{a}_4{a}_5\&rsqb;,\\ {\left(a_2{a}_3{a}_4{a}_5{a}_1\right)}^2\&lsqb;a_1{a}_2{a}_3{a}_4{a}_5\&rsqb;,\\ {\left(a_2{a}_3{a}_4{a}_5{a}_1\right)}^3\&lsqb;a_1{a}_2{a}_3{a}_4{a}_5\&rsqb;,\\ {\left(a_2{a}_3{a}_4{a}_5{a}_1\right)}^4\&lsqb;a_1{a}_2{a}_3{a}_4{a}_5\&rsqb;\end{array}\right\}=\left\{\begin{array}{c}{a}_1{a}_2{a}_3{a}_4{a}_5,\\ a_2{a}_3{a}_4{a}_5{a}_1,\\ a_3{a}_4{a}_5{a}_1{a}_2,\\ a_4{a}_5{a}_1{a}_2{a}_3,\\ a_5{a}_1{a}_2{a}_3{a}_4,\end{array}\right\}=\left\{\begin{array}{c}12345,\\ 23451,\\ 34512,\\ 45123,\\ 51234\end{array}\right\}$

The following O was obtained according to theorem 2₅In the form of a permuted array

$O_5=\left[\begin{array}{c}{o}_1\\ o_2\\ o_3\\ o_4\end{array}\right]=\left[\begin{array}{c}1o_1\\ 2o_2\\ 3o_3\\ 4o_4\end{array}\right]=\left[\begin{array}{ccccc}1\&CenterDot;1& 1\&CenterDot;2& 1\&CenterDot;3& 1\&CenterDot;4& 1\&CenterDot;5\\ 2\&CenterDot;1& 2\&CenterDot;2& 2\&CenterDot;3& 2\&CenterDot;4& 2\&CenterDot;5\\ 3\&CenterDot;1& 3\&CenterDot;2& 3\&CenterDot;3& 3\&CenterDot;4& 3\&CenterDot;5\\ 4\&CenterDot;1& 4\&CenterDot;2& 4\&CenterDot;3& 4\&CenterDot;4& 4\&CenterDot;5\end{array}\right]\left(\mathrm{mod}5\right)=\left[\begin{array}{ccccc}1& 2& 3& 4& 5\\ 2& 4& 6& 8& 10\\ 3& 6& 9& 12& 15\\ 4& 8& 12& 16& 20\end{array}\right]\left(\mathrm{mod}5\right)=\left[\begin{array}{ccccc}1& 2& 3& 4& 5\\ 2& 4& 1& 3& 5\\ 3& 1& 4& 2& 5\\ 4& 3& 2& 1& 5\end{array}\right]$

Then O₅In the form of a collection of $O_5=\left\{\begin{array}{c}{o}_1,\\ o_2,\\ o_3,\\ o_4\end{array}\right\}=\left\{\begin{array}{c}{a}_1{a}_2{a}_3{a}_4{a}_5,\\ a_2{a}_4{a}_1{a}_3{a}_5,\\ a_3{a}_1{a}_4{a}_2{a}_5,\\ a_4{a}_5{a}_1{a}_2{a}_3,\\ a_4{a}_3{a}_2{a}_1{a}_5\end{array}\right\}=\left\{\begin{array}{c}12345,\\ 24135,\\ 31425,\\ 43215\end{array}\right\},$

Let c₁＝o₁＝e＝[12345]The following P was obtained according to theorem 3₅，

Example 1 description of P₅The code length is 5, the minimum distance is 4, the number of code words is 20, and the error correction capability is 3. From P₅In can be seen that P₅From 4 tracks { C₅o₁},{C₅o₂},{C₅o₃},{C₅o₄And (5) composition.

Technical scheme

The technical scheme is divided into two parts. The first part is a construction method based on coset division (n, n (n-1), n-1) permutation group codes; the second part is the structural design of the code set generator of the (n, n (n-1), n-1) permutation group code.

A first part: construction method of coset division (n, n (n-1), n-1) permutation group code

According to theorem 1, theorem 2 and theorem 3, the construction method of the coset division (n, n (n-1), n-1) permutation group code is as follows: all codewords in the code set are composed of Calculation of where P_nIs a symmetric group S_nOf size | P_nN (n-1), the minimum distance beingC_nIs P_nIs also a cyclic group C_n＝{c₁,...,c_β,...,c_n}＝〈c₂Dimension is | C_nN, the minimum distance beingβ＝1,2,...,n；O_n＝{o₁,...,o_α,...,o_n-1Is P_nAnd C_nAnother subgroup that is not identical, also called the head-of-track array of the (n, n (n-1), n-1) permuted group code, has a size | O_nN-1, the minimum distance beingα is 1,2, n-1, and C_nAnd O_nOf (2) intersection C_n∩O_nE is a unit permutation. In the code set P_nIn, C_nWill P_nDivided into n-1 cosets P_n＝{C_no₁,C_no₂,...,C_no_n-1Each coset { C }_no_αIs formed by a substitution o_αAlso called the circular Latin Square (C-LS).

Each code word in the permutation code set is composed of p_βα＝c_βοo_αCalculation of which is two permutations c_βAnd o_αThe synthesis operation of (2) is not favorable for hardware implementation, and therefore, a permutation operation function which can be executed by a circuit needs to be constructed. Due to C_nIs a cyclic array, and it is conceivable to replace C with a cyclic shift of the pair permutation_nThereby equivalently converting the permuted synthesis operation into a cyclic shift operation and can be performed by a basic cell circuit cyclic shift register, for which the following operation functions and composite operation functions are first defined.

Constructing an operation function: let T denote the set of all the operating functions that act on the permutation. Constructing a right shift operation function set T_right＝{r₂,r₃,...,r_n-1,r_nAn element of an construct, which is an arbitrary element r_i∈T_rightIs a function r_i:S_n→S_nAnd is formed by_iπ＝r_i[a₁...a_i...a_n]＝[a_ia₁...a_i-1a_i+1...a_n]∈S_nTo define, call r_i∈T_rightIs a permuted partial loop right shift operation function; when i is n, there is r_nπ＝r_n[a₁a₂...a_n]＝[a_na₁a₂...a_n-1]∈S_nBalance r_nIs a permuted circular right shift operation function. Similarly, a set of left shift opfunctions T is constructed_left＝{l₁,l₂,...,l_n-1Mu.l of an element l_j∈T_leftIs a function l_j:S_n→S_nAnd is composed of_jπ＝l_j[a₁...a_j...a_n]＝[a₁...a_j-1a_j+1...a_na_j]∈S_nTo define, term l_j∈T_leftIs a permuted partial loop left shift operation function; when j is 1, there is l₁π＝l₁[a₁a₂...a_n]＝[a₂a₃...a_n-1a_na₁]∈S_nBalance l₁Is a permuted circular left shift operation function.

Constructing a composite operation function of cyclic shift: according to a certain sorting rule, T is added_leftOr T_rightSome or all of the operation functions in the set are arranged in strings or in multiples of powers of different functions, and the strings of operation functions or products of powers of the operation functions form a composite operation function, denoted as f_CF(u, Λ), wherein u represents the synthesis function f_CF(u, Λ) and Λ denotes the order rule of the operation functions Λ is the order rule of the operation functions that a certain function is repeatedly used λ -1 times, and when λ is equal to n, a loop left-shift composite operation function is constructedConstructing a cyclic right-shift composite operation functionIf the two classes of complex operating functions are each acted upon by a permutation pi ═ a₁a₂...a_n]Then two sets of n permutations are obtained, respectively, expressed as: $\left\{{\left(l_1\right)}^{n-1}\mathrm{\&pi;}\right\}\stackrel{\mathrm{\&Delta;}}{=}\{\mathrm{\&pi;},l_1\mathrm{\&pi;},{l_1}^2\mathrm{\&pi;},...,{l_1}^{n-1}\mathrm{\&pi;}\}$ and $\left\{{\left(r_n\right)}^{n-1}\mathrm{\&pi;}\right\}\stackrel{\mathrm{\&Delta;}}{=}\{\mathrm{\&pi;},r_n\mathrm{\&pi;},{r_n}^2\mathrm{\&pi;},...,{r_n}^{n-1}\mathrm{\&pi;}\}.$ set { (l)₁)^n-1Pi } sum { (rn)^n-1Pi and set { C_nπ are equally well the ones replacing π, i.e. { C_nπ}＝{(l₁)^n-1π}＝{(rn)^n-1Pi, that is to say the tracks formed by the three different operations constitute equivalent classes, but the ordering of the permutations in each track is different, and therefore the C-LS in each track is different.

Thus, coset partition (n, n (n-1), n-1) code set P of permutation group code_n＝{C_nO_nThe circulating group C in_nThe operation function (l) can be compounded by moving the loop left₁)^n-1Or circularly right-shift the composite operation function (r)_n)^n-1Instead, each track { C_no_αExecution expression of { C }_no_α}＝{(r_n)^n-1o_α}＝{(l₁)^n-1o_αThe expression enumerating all codewords is α ═ 1,2_n＝C_nO_n＝{(r_n)^n-1O_n}＝{{(r_n)^n-1o₁},{(r_n)^n-1o₂},...,{(r_n)^n-1o_n-1}}＝{(l₁)^{n- 1}O_n}＝{{(l₁)^n-1o₁},{(l₁)^n-1o₂},...,{(l₁)^n-1o_n-1}}。

Head of track array O provided below for theorem 2_nStructural feature analysis is carried out, and then O is given_nSome different design methods.

Rail head array O_nHas the structural characteristics that the track head array of the (n, n (n-1), n-1) permutation group code has the following structural characteristics that one is the array of (n-1) × n, and each row is S_nA permutation of (c) and the presence of a unique column containing the same element a_kK, whereinOrSecondly, if the column of the same element is removed, the remaining rows and columns form a Latin square of size (n-1) × (n-1), and thirdly, the head array of tracks O_nEach row of (a) has n different adjacent pairs (a)_μ,a_n) Comprising pairs of cyclic neighbors, and a head array O_nItself comprising n (n-1) non-identical pairs of adjacent (or cyclically adjacent) numbers, whereinOrAnd a is_μ≠a_n，μ≠v。In general, when n positive integers form a pair (a)_μ,a_v) When there are a total of n (n-1) different pairs, this is a sufficient condition for the track head array to contain n (n-1) non-identical pairs of adjacent numbers.

Rail head array O_nThe design method of (1): the track head array satisfying the three structural characteristics can be calculated by an explicit expression, for example, theorem 2, and the hardware executable design scheme has two. Scheme 1, the substitutions contain 0 elements. Is provided withRepresents the array O_n1Intermediate α₁Line β₁An element of the column, wherein α₁N-2 represents array O_n1Line index of β₁N-1 denotes array O_n1Column index of (1), k₁0,1, n-1 represents O_n1Middle (k) th₁The columns have the same elements. When n is a prime number, if calculatedWhen it is a multiple of n, xn, it is specified that n is modulo, the result is 0, i.e.Where x is an arbitrary integer, the head array of tracks O_n1Each element of each permutation is calculated as follows

$a_{{\mathrm{\&alpha;}}_1,{\mathrm{\&beta;}}_1}\left(k_1\right)=\&lsqb;({\mathrm{\&alpha;}}_1+1)\&times;({\mathrm{\&beta;}}_1-k_1)+k_1\&rsqb;\left(\mathrm{mod}n\right)---\left(i\right)$

$O_{n1}\left(k_1\right)=\{o_0,o_1,...,o_{n-2}\}={\left\{{\left\{a_{{\mathrm{\&alpha;}}_1,{\mathrm{\&beta;}}_1}\left(k_1\right)\right\}}_{{\mathrm{\&alpha;}}_1=0}^{n-2}\right\}}_{{\mathrm{\&beta;}}_1=0}^{n-1}$ When k is₁0,1, n-1 (ii)

In case 2, the substitution does not contain 0 element. Is provided withRepresents the array O_n2Intermediate α₂Line β₂An element of the column, wherein α₂1,2, n-1 denotes array O_nLine index of β₂1,2, n denotes the array O_n2Column index of (1), k₂1,2, n represents O_n2Middle (k) th₂The columns have the same elements. When n is a prime number, if calculatedIs a multiple of n, xn, it is specified that it is modulo n, resulting in n, i.e. n Where x is an arbitrary integer, the head array of tracks O_n2Each element of each permutation is calculated as follows

$a_{{\mathrm{\&alpha;}}_2,{\mathrm{\&beta;}}_2}\left(k_2\right)=\&lsqb;{\mathrm{\&alpha;}}_2({\mathrm{\&beta;}}_2-k_2)+k_2\&rsqb;\left(\mathrm{mod}n\right)---\left(iii\right)$

$O_{n2}\left(k_2\right)=\{o_1,o_2,...,o_{n-1}\}={\left\{{\left\{a_{{\mathrm{\&alpha;}}_2,{\mathrm{\&beta;}}_2}\left(k_2\right)\right\}}_{{\mathrm{\&alpha;}}_2=1}^{n-1}\right\}}_{{\mathrm{\&beta;}}_2=1}^n$ When k is₂1,2, when n is (iv)

When k is₂When n, expressions (iii) and (iv) of scheme 2 can be simplified to

a_α,b(n)＝[α·β](modn) when α is 1,2,.., n-1 and β is 1,2,.., n, (v)

$O_n=\{o_1,o_2,...,o_{n-1}\}={\left\{{\left\{a_{\mathrm{\&alpha;},\mathrm{\&beta;}}\left(n\right)\right\}}_{\mathrm{\&beta;}=1}^n\right\}}_{\mathrm{\&alpha;}=1}^{n-1}={\&lsqb;{\&lsqb;\mathrm{\&alpha;}.\mathrm{\&beta;}\&rsqb;}_{\mathrm{\&beta;}=1}^n\&rsqb;}_{\mathrm{\&alpha;}=1}^{n-1}\left(\mathrm{mod}n\right)={\{\mathrm{\&alpha;}\&CenterDot;o_1\}}_{\mathrm{\&alpha;}=1}^{n-1}\left(\mathrm{mod}n\right)---\left(vi\right)$

Expression formula(vi) O of theorem 2_nThe calculation is the same.

Example 2: let n be 5, according to O_nIf 1, ifThen c₀＝o₀＝e＝[01234]When each element of each permutation consists of (i)Calculation of, for different k₁0,1,2,3,4, O of (ii)_n1(k₁) Respectively calculate the following different rail head arrays

${\left\{\begin{array}{c}01234,\\ 02413,\\ 03142,\\ 04321\end{array}\right\}}_{k_1=0}{\left\{\begin{array}{c}01234,\\ 41302,\\ 31420,\\ 21043\end{array}\right\}}_{k_1=1}{\left\{\begin{array}{c}01234,\\ 30241,\\ 14203,\\ 43210\end{array}\right\}}_{k_1=2}{\left\{\begin{array}{c}01234,\\ 24130,\\ 42031,\\ 10432\end{array}\right\}}_{k_1=3}{\left\{\begin{array}{c}01234,\\ 13024,\\ 20314,\\ 32104\end{array}\right\}}_{k_1=4}$

If a loop left shift is used to compound the operation function (l)₁)⁴Or circularly right-shift the composite operation function (r)₅)⁴Respectively act on O_n1(k₁)(k₁5 head of track arrays of 0,1,2,3,4), the obtained 10 permutation code sets are all equivalent.

Then n is 5, then according to O_nDesign 2 and simplification ifThen c₁＝o₁＝e＝[12345]When each element of each permutation consists of (iii)(modn) is calculated or calculated from (v) a_α,β(n)＝[α·β](modn) calculation for different k₂1,2,3,4,5 and simplified version, O of (iv)_n2(k₂) And (vi) O_nRespectively calculate the following different rail head arrays

${\left\{\begin{array}{c}12345,\\ 13524,\\ 14253,\\ 15432\end{array}\right\}}_{k_2=1}{\left\{\begin{array}{c}12345,\\ 52413,\\ 42513,\\ 32154\end{array}\right\}}_{k_2=2}{\left\{\begin{array}{c}12345,\\ 41352,\\ 25314,\\ 54321\end{array}\right\}}_{k_2=3}{\left\{\begin{array}{c}12345,\\ 35241,\\ 53142,\\ 21543\end{array}\right\}}_{k_2=4}{\left\{\begin{array}{c}12345,\\ 24135,\\ 31425,\\ 43215\end{array}\right\}}_{k_2=5}{O}_5=\left\{\begin{array}{c}12345,\\ 24135,\\ 31425,\\ 43215\end{array}\right\}$

If a loop left shift is used to compound the operation function (l)₁)⁴Or circularly right-shift the composite operation function (r)₅)⁴Respectively act on O_n2(k₂)(k₂1,2,3,4,5) and a simplified head-of-track array O₅The obtained 12 permutation code sets are all equivalent to the permutation group code based on coset division obtained by the synthesis operation, that is, k is 1,2,3,4,5, there are

$P_5=C_5{O}_5=\left\{{\left(r_5\right)}^4{O}_{52}\left(k_2\right)\right\}=\left\{{\left(l_1\right)}^4{O}_{52}\left(k_2\right)\right\}=\left\{{\left(r_5\right)}^4{O}_5\right\}=\left\{{\left(l_4\right)}^4{O}_5\right\}=\left\{\begin{array}{cccc}12345,& 24135,& 31425,& 43215,\\ 23451,& 35241,& 42531,& 54312,\\ 34512,& 41352,& 53142,& 15432,\\ 45123,& 52413,& 14253,& 21543,\\ 51234,& 13524,& 25314,& 32154\end{array}\right\}$

Code set generator structure design of second part coset division (n, n (n-1), n-1) permutation group code

The structure of a code set generator for coset partitioning (n, n (n-1), n-1) permutation group codes is divided into 4 parts: the code set generator architecture comprises a code set generator architecture, a track head array generator, a ROM memory and a bidirectional cyclic shift register set.

Binary representation of permutations if each element of an n-long permutation is represented by an m-bit binary, then the n-long permutation may be described by a binary array of m × n, m and n satisfying 2^m-1+1≤n≤2^m。

Code set generator architecture: the method comprises a track head array generator, a ROM (read only memory) and a bidirectional cyclic shift register set, and is shown in figure 1. The principle circuit of the track head array generator is constructed by taking expressions (i) - (vi) as a basis, and the specific working process is to execute the calculation of the expression (vi)Generating a head-of-track array O comprising n-1 permutations_n＝{o₁,o₂,...,o_n-1}. The ROM memory is used for firstly storing the output result O of the track head array generator_n＝{o₁,o₂,...,o_n-1And storing an output result P of the bidirectional cyclic shift register group_n＝{{(l₁)^n-1o₁},{(l₁)^n-1o₂},...,{(l₁)^n-1o_n-1} or P_n＝{{(r_n)^n-1o₁},{(r_n)^n-1o₂},...,{(r_n)^n-1o_n-1}}. The bidirectional circular shift register group is used for executing a circular left shift composite operation function (l) to a replacement₁)^n-1Or circularly right-shift the composite operation function (r)_n)^n-1In particular to the head of the track replacement o_αPerforming n-1 times of cyclic left shift or n-1 times of cyclic right shift operation to realize the first replacement o of each track_αTrack of (l { (l)₁)^n-1o_αEither (r)_n)^n-1o_αSince each track { (l) }, α { (1, 2., n-1 { (l)₁)^n-1o_αEither (r)_n)^n-1o_αN permutations are contained, if the generation process of each track is repeated for n-1 times, a code set of coset division (n, n (n-1), n-1) permutation group codes is formed, and the specific calculation expression is P_n＝C_nO_n＝{(l₁)^n-1O_n}＝{{(l₁)^n-1o₁},{(l₁)^n-1o₂},...,{(l₁)^n-1o_n-1} or P_n＝C_nO_n＝{(r_n)^{n- 1}O_n}＝{{(r_n)^n-1o₁},{(r_n)^n-1o₂},...,{(r_n)^n-1o_n-1}}。

Track head array generator: see figure 2. In the case of optimizing the circuit structure, the structural parameters are designed as follows: n is any prime number, and in order to avoid collision between the situation that the amplitude is attenuated to 0 due to fading interference and the code element in the code word is 0, the amplitude is takenIt is guaranteed that no 0-bit occurs in each permuted codeword. To facilitate symbol tracking, take k₂N denotes that the last column of the track head array is the same column, and has a value of n, which can simplify expressions (i) and (iii) to the maximum extent as expression (v): a is_α,β(n)＝[α·β](modn) of the trackHead array O_nIs simplified intoWhere α is 1, 2.., n-1 denotes that the head array of tracks contains n-1 permutations, and β is 1, 2.., n denotes that each permutation contains n elements.

The function of the head array generator is to generate the head array when the initial permutation is o₁＝e＝[12...n]When n-1 head of track permutations are performed $O_n={\left\{{\mathrm{\&alpha;o}}_1\right\}}_{\mathrm{\&alpha;}=1}^{n-1}\left(\mathrm{mod}n\right)=\{o_1,2o_1,...,(n-1)o_1\}\left(\mathrm{mod}n\right)$ The calculation of (2) yields n-1 track head permutations, which are transferred to the ROM memory via the bus for each permutation.

The track head array generator is composed of five parts: the device comprises n parallel operation input buffers (10), n parallel operation positive integer adders (11), n parallel operation modn calculators (12), n parallel operation output buffers (13), n input single output switches (14) and an enable signal generator (15). The working principle of each part is described as follows:

n parallel operation input buffers (10) are formed of n m-bit registers each storing one of n input data in m-bit binary, each buffer having m parallel data line inputs and outputs. Input initial permutation o₁＝e＝[12...n]To n parallel running input buffers (10), the track head array generator starts to operate.

n parallel-running positive integer adders (11) for adding the n parallel-running positive integer addersMultiplication operation in (1) { o }₁,2o₁,...,(n-1)o₁Conversion to the initial permutation o₁＝[12...n]The accumulation operation of each element is mainly completedCalculating; the initial unit replacement is transmitted to the output buffer directly without accumulation, so that the accumulation is needed n-2 times to complete the aggregationThe operation of (1); each of n parallel-running positive integer adders (11) is formed by m 'binary full adders and m' bit B registersm data lines are input in parallel, and m' data lines are output in parallel; one input end of each binary full adder receives data of the input buffer, the other input end of each binary full adder is connected with the output end of the register B, and the output end of each binary full adder is connected with the input end of the register B; the working principle of the n parallel operation positive integer adders (11) is as follows: when the enable signal E is equal to 1, each adder adds the last summation result, namely the content in the B register, and the input results of n parallel operation input buffers (10) once, stores the summation result in the B register, and stores the content in the B registerOutputting to n parallel operation modn calculators (12); when the enable signal E is 0, the adder does not operate.

n parallel running modn calculators (12) for performingCalculating, specifically, performing modn calculation on data transmitted from B registers in n parallel operation positive integer adders (11); each modn calculator is composed of a two-input-end single-output-end general modn calculator, an m-bit C register and an m-bit D register, m' data lines are input in parallel, and m data lines are output in parallel; one input end of the general modn calculator is provided with an m' bit parallel input data line connected with the output end of the B register, the other input end of the general modn calculator is provided with an m bit parallel input data line connected with the output end of the C register, and one output end of the general modn calculator is provided with an m bit parallel output data line; the register C stores invariant data n, and the register D is used for storing the output result of the general modn calculator; if the data | x | of the D register is not 0, the data of the D register is output, and if the data | x | of the D register is 0, the data of the C register is output.

The n parallel operation output buffers (13) have the same structure as the n parallel operation input buffers (10), namely are composed of n m-bit registers and are used for storing the currently generated track head replacement; when the current data of the (n-1) th buffer of the n parallel operation output buffers (13) is ready, a signal is sent to the first switch of the n input single output switches (14) to close.

The n input single output switches (14) are used for serially outputting each of n data of n parallel operation output buffers (13) to a bus, and each switch is switched on from 1 to n, which is equivalent to that m data lines of each output buffer are switched on with m parallel buses; when the (n-1) th buffer of the n parallel operation output buffers (13) is ready for current data, a first switch of the n input single output switch (14) is sent out to close the switch; when the nth switch is closed and the last bit of data is transmitted to the ROM through the bus, a high level signal is output to the input terminal of the enable signal generator (15).

The enabling signal generator (15) provides enabling signals for n parallel operation positive integer adders (11), and the enabling signals comprise a binary plus 1 counter and a monostable trigger, and an input signal line, an output signal line and a normal output low level are connected in series; the input end of the enable signal generator is connected with an output control signal line of an nth switch of the n input single output switches (14), and the output end of the enable signal generator is connected with enable ends E of the n parallel operation positive integer adders (11); the working principle of the enabling signal generator (15) is as follows: when the nth switch of the n-input single-output switch (14) is closed, the enabling signal generator (15) works, the binary plus 1 counter performs one-time plus 1 operation, the monostable trigger generates high-level pulses with the duration of 1 cp and outputs the high-level pulses to the enabling ends of n parallel operation positive integer adders (11), and E is made to be 1; when the nth switch of the n-input single-output switch (14) is turned off, the enable signal generator (15) does not work and keeps E equal to 0. When the binary 1-up counter is n-1 times, the enable signal generator (15) outputs a low level.

ROM memory: see figure 3. The ROM memory (16) can be a programmable memory PROM, an erasable programmable memory EPROM, an electrically erasable programmable memory E²PROM, or flash memory. The storage structure of the ROM memory (16) is: each element of a permutation being represented by an m-bit binary, e.g. the first element of a permutation being represented by an m-bit binary b_1,1,b_2,1,...,b_m-1,1,b_m,1Representing the last element by m-bit binary b_1,n,b_2,n,...,b_m-1,n,b_m,nIs shown in the specification, wherein b_i,j(i-0, 1., m-1, j-0, 1., n-1) is a binary value that takes the value 0 or 1. The m-bit binary system of one element of each permutation occupies m storage units and is defined as one element storage word of the memory; one permutation occupies n element storage words, n-1 orbital head permutations occupy n (n-1) element storage words, and n (n-1) permutation code words occupy n²(n-1) element storage words. The ROM memory (16) has m-bit parallel data inputs and m-bit parallel data outputs. Specific operation of ROM memory (16)Comprises the following steps: when Wr is 1, m-bit data of one element storage word is input in parallel; when Rd is 1, m-bit data of one element memory word is output in parallel. When Wr is 0 and Rd is 0, the ROM memory (16) does not operate.

Bidirectional cyclic shift register set: see figure 4. The bidirectional cyclic shift register group (17) is used for realizing a cyclic left shift composite operation function (l)₁)^n-1Or circularly right-shift the composite operation function (r)_n)^n-1For a permuted operation, the track { (l) is executed₁)^{n- 1}o_αAnd { (r) }_n)^n-1o_αThe generation calculation implementation of { and the code set { (l)₁)^n-1O_nAnd { (r) }_n)^n-1O_nThe generation calculation of the N-dimensional permutation vector has the storage structure that each element of the n-dimensional permutation vector can be represented by an m-dimensional binary sequence, each n-dimensional permutation vector is mapped into an m × n-dimensional binary number array, m × n triggers form a trigger array with m rows and n columns, each row of m rows is formed by n triggers into a register capable of circularly moving left and circularly moving right, namely the n triggers form a bidirectional cyclic shift register, and m bidirectional cyclic shift registers are required to form m bidirectional cyclic shift register groups, wherein the first cyclic shift register stores n-bit binary numbers b_1,1,b_1,2,...,b_1,n-1,b_1,nThe mth cyclic shift register stores n-bit binary number b_m,1,b_m,2,...,b_m,n-1,b_m,n(note that the array is m × n, the array of the ROM memory (16) is n × m.) the m parallel switches (18) are connected in series in a circular left shift loop, with the switches closed, performing a circular left shift operation of m data in parallel, and with the switches open, performing a left shift input and a left shift output operation of m data in parallel.two control signal inputs REG-in and REG-out are provided, and four control signals 00,01,10,11 can be combined, corresponding to the four operating states of the bi-directional circular shift register set, respectively, left shift input, left shift output, circular left shift, and circular right shift. the operation of the bi-directional circular shift register set (17) is described as follows:

procedure a — input to perform a permutation. When REG-in is 0, REG-out is 0 and Rd is 1, m parallel switches (18) of the loop of the circulation left shift are turned off, and the first track in the ROM (16) is firstly permutated and transferred to a bidirectional circulation shift register group (17), during which the circulation shift register group executes the input operation of m-bit parallel n-bit serial left shift;

procedure b-move left with a loop to generate a new permutation. When REG-in is equal to 0 and REG-out is equal to 1, m parallel switches (18) of the loop for left shift circularly are closed, and a bidirectional circular shift register group (17) executes m-bit parallel n-bit serial circular left shift operation to generate a new permutation;

procedure c — output of one permutation is performed. When REG-in is 1, REG-out is 0 and Wr is 1, m parallel switches (18) of the loop left shift are closed, and the bidirectional loop shift register group (17) completes two operations: transferring the current permutation generated in the process b to a ROM (read only memory) (16) through m-bit parallel n-bit serial left shift output operation, and simultaneously finishing m-bit parallel n-bit serial circulation left shift operation of the current permutation to keep the permutation generated in the process b;

process d-Generation of a { (l)₁)^n-1o_αAnd (6) track. The process b and the process c are combined, m parallel switches (18) of a loop for left shift are closed in the period, and the two processes work in turn: during 1 cp clock pulse, REG-in is equal to 0 and REG-out is equal to 1, the bidirectional cyclic shift register group (17) executes a serial left shift operation of m bits in parallel and n bits once to obtain a new permutation; during the next n cp clock pulses, REG-in is 1, REG-out is 0 and Wr is 1, the bi-directional cyclic shift register bank (17) simultaneously performs an m-bit parallel n-bit serial left shift output operation and an m-bit parallel n-bit serial cyclic left shift operation on the current permutation, saves the current permutation, and transfers it to the ROM memory (16). Procedure d corresponds to the replacement of o for one track head_αCompletion (l)₁)^n-1Operate to generate a complete { (l)₁)^n-1o_αTrack and will be defined by track (l)₁)^n-1o_αN-1 generatedThe permutation is saved to a ROM memory (16).

Process e-generating a set of codes { (l)₁)^n-1O_n}. The method is formed by combining the process a and the process d, and the process e is repeatedly operated for n-1 times to complete the code set { (l) of a coset division (n, n (n-1), n-1) permutation group code₁)^n-1O_nThe generation process of.

Procedure b' -a new permutation is generated with a loop right shift. Modify process b to process b': when REG-in is 1 and REG-out is 1, m parallel switches of the loop for left shift cycle are turned off, and the bidirectional cyclic shift register group (17) executes m bit parallel n bit serial cyclic right shift operation to generate a new permutation.

The process d': generating a { (r)_n)^n-1o_αAnd (6) track. Combined by process b' and process c, equivalent to completing the permutation o_αTrack of (r { (r)_n)^n-1o_αIs generated and stored in a ROM memory (16) { (r)_n)^n-1o_α}。

The process e': generating a set of codes { (r)_n)^n-1O_n}. The method is formed by combining the process a and the process d ', and n-1 times of repeated operation is carried out on the process e', so that the code set { (r) of a coset division (n, n (n-1), n-1) permutation group code is completed_n)^n-1O_nThe generation process of.

It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (6)

1. A method for constructing a coset-partitioned (n, n (n-1), n-1) permutation group code, comprising: the structure of a permutation group code having a code length of n and a minimum distance of n-1 and a code set size of n (n-1) is The code set P_n＝C_nO_nBy cyclically permuting subgroup C_nAnd a different subgroup O_nAre cosets of each other; the code set P_n＝{{C_no₁},{C_no₂},...,{C_no_n-1Is permutation subgroup C_nWill P_nDivided into n-1 cosets, each coset { C_no_αIs formed by a substitution o_αOrbital or circular Latin Square (C-LS); the code set Is each permutation code word p_βαFrom subgroup C_nSubstitution of (1) to (c)_βAnd subgroup O_nSubstitution of (1) to_αThe synthesis operation of (a) yields, α ═ 1,2,. n-1 and β ═ 1,2,. n.

2. The method for constructing coset-partitioned (n, n (n-1), n-1) permutation group code as claimed in claim 1, wherein the operation function (l) is a circular left-shift complex operation function₁)^n-1Or circularly right-shift the composite operation function (r)_n)^n-1Substituted C_nTwo permutation subgroups C_nAnd O_nThe synthesis operation of (2) is converted into a cyclic shift operation which can be executed by hardware; said (l) is prepared from₁)^n-1Or (r)_n)^n-1Substituted C_nThe operation of (1) is specifically: each track in the permutation group { C_no_αUsing its equivalent expression { C }_no_α}＝{(r_n)^n-1o_α}＝{(l₁)^n-1o_αIs performed, α ═ 1, 2.. n-1, the set of codes P_n＝C_nO_nBy its equivalent expression P_n＝C_nO_n＝{(r_n)^n-1O_n}＝{{(r_n)^{n- 1}o₁},{(r_n)^n-1o₂},...,{(r_n)^n-1o_n-1} or P_n＝C_nO_n＝{(l₁)^n-1O_n}＝{{(l₁)^n-1o₁},{(l₁)^{n- 1}o₂},...,{(l₁)^n-1o_n-1} is performed.

3. The method for constructing a coset-partitioned (n, n (n-1), n-1) permutation group code according to claim 1, wherein the permutation subgroup O_nThe method is equivalent to a track head array, and the construction method specifically comprises the following steps:

if the permutation contains 0 element, then setRepresents the array O_n1Intermediate α₁Line β₁An element of the column, wherein α₁N-2 represents array O_n1Line index of β₁N-1 denotes array O_n1Column index of (1), k₁0,1, n-1 represents O_n1Middle (k) th₁Column is and₁the same elements; when n is a prime number, specifyingx is any integer; rail head array O_n1The computational expression of each element of each permutation isThe computational expression of n-1 permutations of the head array of tracks is $O_{n1}\left(k_1\right)=\{o_0,o_1,...,o_{n-2}\}={\left\{{\left\{a_{{\mathrm{\&alpha;}}_1,{\mathrm{\&beta;}}_1}\left(k_1\right)\right\}}_{{\mathrm{\&alpha;}}_1=0}^{n-2}\right\}}_{{\mathrm{\&beta;}}_1=0}^{n-1},$ Wherein k is₁0,1,., n-1; or,

if the permutation does not contain 0 elements: is provided withRepresents the array O_n2Intermediate α₂Line β₂An element of the column, wherein α₂1,2, n-1 denotes array O_n2Line index of β₂1,2, n denotes the array O_n2Column index of (1), k₂1,2, n represents O_n2Middle (k) th₂Column is and₂the same elements(ii) a When n is a prime number, specifyingx is any integer; rail head array O_n2The computational expression of each element of each permutation isThe computational expression of n-1 permutations of the head array of tracks is $O_{n2}\left(k_2\right)=\{o_1,o_2,...,o_{n-1}\}={\left\{{\left\{a_{{\mathrm{\&alpha;}}_2,{\mathrm{\&beta;}}_2}\left(k_2\right)\right\}}_{{\mathrm{\&alpha;}}_2=1}^{n-1}\right\}}_{{\mathrm{\&beta;}}_2=1}^n,$ Wherein k is₂1,2, n; let k₂N andthe rail head array O_n2The computational expression of each element of each permutation is reduced to a_α,β(n)＝[α·β](modn), head of track array O_n2The computational expression of n-1 permutations of (1) is simplified toWherein o is₁＝e＝[a₁a₂...a_n]＝[12...n]，α is 1,2,. n-1 and β is 1,2,. n.

4. A code set generator for a coset-partitioned (n, n (n-1), n-1) permutation group code, comprising a track head array generator, a ROM memory, and a bi-directional cyclic shift register set, wherein:

the track head array generator is used for executingCalculating to generate n-1 track head permutations;

the ROM stores the output result of the track head array generator and the output result of the bidirectional cyclic shift register group;

the bidirectional cyclic shift register set executes₁)^n-1Or (r)_n)^n-1For one permutation operation, realize each track head permutation o_αTrack of (l { (l)₁)^n-1o_αEither (r)_n)^n-1o_αComputation and code set of { (l)₁)^n-1O_nEither (r)_n)^n-1O_nCalculation of, α ═ 1, 2.., n-1.

5. The code set generator of the coset-partitioning (n, n (n-1), n-1) permutation group code as claimed in claim 4, wherein: the track head array generator is used for inputting the unit permutation o when the initial permutation is₁＝e＝[12...n]Under the condition of (1), performing n-1 track head replacement And storing the n-1 track head replacement into a ROM; the track head array generator comprises n parallel operation input buffers, n parallel operation positive integer adders, n parallel operation modn calculators, n parallel operation output buffers, n input single output switches and an enable signal generator, wherein:

the n parallel operation input buffers are composed of n m-bit binary registers, the input end and the output end of each register are connected with m parallel data lines, and m satisfies 2^m-1+1≤n≤2^m；

The n parallel-running positive integer adder executionsOperation, each positive integer adder is composed of m 'binary full adders and m' bit B registers,m data lines are input in parallel, and m' data lines are output in parallel; one input end of the binary full adder receives data of the input buffer, the other input end of the binary full adder is connected with the output end of the B register,the output end of the binary full adder is connected with the input end of the register B; when the enable signal E is equal to 1, the n parallel operation positive integer adders work, and when E is equal to 0, the n parallel operation positive integer adders do not work;

the n parallel running modn calculators are used for completingCalculating, wherein each modn calculator comprises a two-input-end single-output-end general modn calculator, an m-bit C register and an m-bit D register, m' data lines are input in parallel, and m data lines are output in parallel; one input end of the general modn calculator is provided with m 'parallel input data lines which are connected with the output ends of the m' bit B registers in the n parallel operation positive integer adders, and the other input end of the general modn calculator is provided with m parallel input data lines which are connected with the output ends of the m bit C registers; the output end of the general modn calculator is provided with m parallel output data lines; the m-bit C register stores an m-bit binary value corresponding to the data n and keeps unchanged; the m-bit D register stores the output value of the general modn calculator, if the value of the D register is not 0, the value of the D register is used as the output value, otherwise, the value of the C register is output;

the n parallel operation output buffers are composed of n m-bit registers, and the input end and the output end of each register are connected with m parallel data lines; when the (n-1) th buffer of the n parallel operation output buffers is ready for current data, sending a signal to close the first switch of the n input single output switches;

the n input single output switches are used for serially outputting each of n data of the n parallel operation output buffers to a bus, each switch is switched on from 1 to n, and m data lines of each output buffer are switched on with m parallel buses; the signal of the first switch closing of the n input single output switches is a control signal sent by the (n-1) th buffer of the n parallel operation output buffers; when the nth switch of the n-input single-output switch is closed, a high level signal is output to the input end of the enable signal generator;

the enabling signal generator provides enabling signals for the n parallel operation positive integer adders, and consists of a binary plus 1 counter and a monostable trigger, wherein the enabling signals comprise an input signal line, an output signal line and a normal output low level; the input end of the n-system plus 1 counter is connected with the output signal line of the nth switch of the n-input single-output switch, when an input control signal is received, the binary plus 1 counter performs a plus 1 operation, and enables the monostable trigger to generate a high level pulse with the duration of 1 cp and output the high level pulse to the E signal ends of the n parallel operation positive integer summers through a signal line; and a binary plus 1 counter is added for n-1 times, the monostable trigger does not send a pulse signal, and the enable signal generator outputs low level.

6. The coset-partitioning (n, n (n-1), n-1) permuted group code generator of claim 4, wherein said bi-directional cyclic shift register set is used for track { (l) }₁)^n-1o_αAnd { (r) }_n)^n-1o_αImplementation of, and code set { (l)₁)^n-1O_nAnd { (r) }_n)^n-1O_nImplementation of the method is carried out; the structure of the bidirectional cyclic shift register group is formed by a trigger array with m rows and n columns, and each row is provided with n triggers to form a bidirectional shift register which can circularly move left and right; connecting a switch in series in each loop of the circulation left shift loop, wherein m switches run in parallel, when m switches are closed, the circulation left shift operation of m data in parallel is executed, and when m switches are opened, the left shift input and left shift output operation of m data in parallel is executed; two control signal input ends REG-in and REG-out are arranged, four control signals 00,01,10 and 11 can be combined, and respectively correspond to four working states of the bidirectional cyclic shift register group: left shift input, left shift output, cyclic left shift, and cyclic right shift.