CN105680753B - Three-phase current reconstructing method based on single current sensor and device - Google Patents
Three-phase current reconstructing method based on single current sensor and device Download PDFInfo
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- CN105680753B CN105680753B CN201610057548.9A CN201610057548A CN105680753B CN 105680753 B CN105680753 B CN 105680753B CN 201610057548 A CN201610057548 A CN 201610057548A CN 105680753 B CN105680753 B CN 105680753B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
- H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
- H02P27/085—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation wherein the PWM mode is adapted on the running conditions of the motor, e.g. the switching frequency
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- Control Of Ac Motors In General (AREA)
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Abstract
The invention discloses a kind of three-phase current reconstructing method and device based on single current sensor, for detecting DC bus current, method includes single current sensor：Obtain the PWM waveform corresponding three-phase comparison point time of the downlink half period of current PWM cycle；Narrow spaces limitation is carried out to the corresponding three-phase comparison point time according to preset narrow spaces threshold limit, and PWM phase shifts processing is carried out to obtain the three-phase uplink and downlink comparison point time to the three-phase comparison point time after limitation according to current sample window time；The PWM waveform of next PWM cycle is exported according to the three-phase uplink and downlink comparison point time, and the first and second AD sampling triggering moments of next PWM cycle are obtained according to the three-phase downlink comparison point time；Triggering moment is sampled according to the first and second AD correspond to the first and second DC bus sample rate currents of reading in next PWM cycle, and three-phase current is reconstructed according to the first and second DC bus sample rate currents, to go out three-phase current by single current sensor accurate reconstruction in more modulation algorithm.
Description
Technical field
The present invention relates to motor control technology field, more particularly to a kind of three-phase current reconstruct based on single current sensor
Method and a kind of three-phase current based on single current sensor reconstruct device.
Background technology
Electric current reconstructing technology based on single current sensor is used widely due to its high performance-price ratio in household electric appliances.
DC bus current is detected by single current sensor, and motor three-phase mutually electricity can be reconstructed in conjunction with PWM pulsewidth modulations
Stream reaches the current feedback requirement of motor vector controlled.
Relevant single current sensor electric current reconstructing technology is low modulation area (output voltage amplitude very little) and unobservable
Area's (output voltage vector close to basic vector) needs to carry out phase shift to PWM waveform, accurately to detect DC bus current.
But the PWM phase-moving methods of the relevant technologies only consider a phase shift or two phase shifts, can not be suitable for three-phase modulations, it can not
Accurately reconstruct three-phase phase current.
Invention content
The present invention is directed to solve at least some of the technical problems in related technologies.For this purpose, the present invention
One purpose is to propose that a kind of three-phase current reconstructing method based on single current sensor, this method can accurately reconstruct three
Phase phase current.
It is another object of the present invention to propose a kind of three-phase current reconstruct device based on single current sensor.
In order to achieve the above objectives, one aspect of the present invention embodiment proposes a kind of three-phase current based on single current sensor
Reconstructing method, the single current sensor the described method comprises the following steps for detecting DC bus current：In current PWM
Period carries out vector controlled to obtain three-phase output voltage, and according to voltage modulated algorithm to the three-phase output voltage to motor
It is modulated the PWM waveform corresponding three-phase comparison point time of the downlink half period to obtain current PWM cycle；According to preset
Narrow spaces threshold limit carries out the PWM waveform of the downlink half period of the current PWM cycle corresponding three-phase comparison point time
Narrow spaces limit, and are carried out at PWM phase shifts to the three-phase comparison point time after narrow spaces limitation according to current sample window time
Reason is to obtain three-phase uplink comparison point time and three-phase downlink comparison point time；According to the three-phase uplink comparison point time and three
The phase downlink comparison point time exports the PWM waveform of next PWM cycle, and according to described in three-phase downlink comparison point time acquisition
The first AD sampling triggering moments of next PWM cycle and the 2nd AD sample triggering moment；In next PWM cycle according to
First AD samples triggering moment and the 2nd AD sampling triggering moments correspond to and read the first DC bus sample rate current and second
DC bus sample rate current, and according to described in the first DC bus sample rate current and the reconstruct of the second DC bus sample rate current
The three-phase current of motor.
The three-phase current reconstructing method based on single current sensor proposed according to embodiments of the present invention, first current
PWM cycle carries out vector controlled to obtain three-phase output voltage, and according to voltage modulated algorithm to three-phase output voltage to motor
It is modulated the PWM waveform corresponding three-phase comparison point time of the downlink half period to obtain current PWM cycle, secondly according to pre-
If narrow spaces threshold limit to the PWM waveform of the downlink half period of the current PWM cycle corresponding three-phase comparison point time carry out
Narrow spaces limit, and are carried out at PWM phase shifts to the three-phase comparison point time after narrow spaces limitation according to current sample window time
Reason is to obtain three-phase uplink comparison point time and three-phase downlink comparison point time, then according to three-phase uplink comparison point time and three
The phase downlink comparison point time exports the PWM waveform of next PWM cycle, and obtains next PWM according to the three-phase downlink comparison point time
The first AD sampling triggering moments in period and the 2nd AD sample triggering moment, are finally sampled according to the first AD in next PWM cycle
Triggering moment and the 2nd AD sampling triggering moments, which correspond to, reads the first DC bus sample rate current and the second DC bus sampling electricity
Stream, and according to the three-phase current of the first DC bus sample rate current and the second DC bus sample rate current reconstruct motor.As a result, should
Method can carry out phase shift processing in more modulation the algorithm such as modulation of three-phase modulations, two-phase to PWM waveform, and then pass through single electricity
Flow sensor accurately reconstructs motor three-phase phase current, and can reduce the switch damage of power switch tube by narrow spaces limitation
Consumption.
According to one embodiment of present invention, the PWM waveform corresponding three of the downlink half period of each PWM cycle compares
The point time includes that compare a time Tmax, interphase comparison point time Tmid of maximum compares a time Tmin with minimum,
In, Tmax >=Tmid >=Tmin.
According to one embodiment of present invention, it is described according to preset narrow spaces threshold limit to the current PWM cycle
PWM waveform corresponding three-phase comparison point time of downlink half period carry out narrow spaces limitation, including：When Tmax ＞ (Ts-Tm)/
When 2, the maximum in the PWM waveform of the downlink half period of the current PWM cycle corresponding three-phase comparison point time is compared
Point time Tmax is limited to Ts/2, wherein Ts is the PWM cycle, and Tm is the preset narrow spaces threshold limit；Work as Tmin
When ＜ Tm/2, by the minimum phase in the PWM waveform of the downlink half period of the current PWM cycle corresponding three-phase comparison point time
The comparison point time, Tmin was limited to 0.
According to one embodiment of present invention, described that three after narrow spaces limitation are compared according to current sample window time
PWM phase shifts processing is carried out to obtain three-phase uplink comparison point time and three-phase downlink comparison point time compared with the time, including：When
(Tmax-Tmid) when ＜ Tw, the three-phase comparison point time after limiting the narrow spaces carries out maximum phase shift phase processor, and most
Minimum phase shift phase processor is carried out after big phase shift phase processor, and calculates the three-phase uplink ratio after minimum phase shift phase processor
Compared with time and three-phase downlink comparison point time, wherein Tw is the current sample window time；As (Tmax-Tmid) >=Tw
And when (Tmid-Tmin) ＜ Tw, the three-phase comparison point time after limiting the narrow spaces directly carries out minimum phase shift phase processor,
And the three-phase uplink comparison point time and three-phase downlink comparison point time are calculated after minimum phase shift phase processor；As (Tmax-
Tmid) >=Tw and when (Tmid-Tmin) >=Tw, when directly calculating the three-phase uplink comparison point time and three-phase downlink comparison point
Between.
According to one embodiment of present invention, the three-phase comparison point time after limiting the narrow spaces carries out maximum phase shift
When phase processor, if (Tmid+Tw) >=Ts/2, δ max=(Ts/2-Tmax) are set, and δ mid=δ min=(Ts/2- are set
Tw-Tmin), wherein Tw is the current sample window time, and Ts is the PWM cycle, and δ max are maximum phase amount of phase shift, δ
Mid is interphase amount of phase shift, and δ min are minimum phase shift phasor；If δ max=(Tmid+ are arranged in (Tmid+Tw) ＜ Ts/2
Tw-Tmax), and δ mid=δ min=0 are set.
According to one embodiment of present invention, the three-phase comparison point time after limiting the narrow spaces carries out minimum phase shift
When phase processor, if (Tmin-Tw)≤0, δ max=δ max+Tw-Tmin are set, and δ mid=δ mid+Tw-Tmin are set,
And setting δ min=δ min-Tmin, wherein Tw is the current sample window time, and δ max are maximum phase amount of phase shift, δ mid
For interphase amount of phase shift, δ min are minimum phase shift phasor；If (Tmin-Tw) ＞ 0, δ min=δ min-(Tw- is set
Tmin), and keep δ max and δ mid constant.
According to one embodiment of present invention, when the corresponding three-phase comparison point of the PWM waveform of the downlink half period of PWM cycle
Between three-phase uplink comparison point time and three-phase downlink comparison point time calculated according to following formula：Tmax_down=Tmax+
δ max, Tmid_down=Tmid+ δ mid, Tmin_down=Tmin+ δ min, wherein Tmax_down, Tmid_down and
Tmin_down is respectively that maximum phase downlink comparison point time in the three-phase downlink comparison point time, interphase downlink compare
Point time and minimum phase downlink comparison point time, when Tmax, Tmid and Tmin are respectively the maximum phase downlink comparison point before phase shift
Between, interphase downlink comparison point time and minimum phase downlink comparison point time；Tmax_up=Tmax × 2-Tmax_down,
Tmid_up=Tmid × 2-Tmid_down, Tmin_up=Tmax × 2-Tmin_down, wherein Tmax_up, Tmid_up and
Tmin_up is respectively maximum phase uplink comparison point time in the three-phase uplink comparison point time, interphase uplink comparison point
Time and minimum phase uplink comparison point time.
According to one embodiment of present invention, after obtaining the three-phase uplink comparison point time, also to the three-phase
The uplink comparison point time carries out amplitude limiting processing.
According to one embodiment of present invention, the voltage modulated algorithm is three-phase modulations algorithm, minimum phase two-phase modulation
Any one in algorithm, maximum phase two-phase modulation algorithm and minimax phase two-phase modulation algorithm.
According to one embodiment of present invention, the current sample window time is that DC bus current signal rises stabilization
The sum of sample conversion time when time samples with AD.
In order to achieve the above objectives, another aspect of the present invention embodiment proposes a kind of three-phase electricity based on single current sensor
Stream reconstruct device, for detecting DC bus current, described device includes the single current sensor：Voltage modulated module is used
In the PWM wave for being modulated the uplink half period to obtain current PWM cycle to three-phase output voltage according to voltage modulated algorithm
The shape corresponding three-phase comparison point time, wherein the three-phase output voltage carries out vector controlled according to current PWM cycle to motor
It obtains；PWM phase shift blocks, for according to preset narrow spaces threshold limit to uplink half period of the current PWM cycle
The PWM waveform corresponding three-phase comparison point time carries out narrow spaces limitation, and is limited narrow spaces according to current sample window time
When the three-phase comparison point time afterwards carries out PWM phase shifts processing to obtain three-phase uplink comparison point time and three-phase downlink comparison point
Between；PWM output modules, for exporting next PWM according to the three-phase uplink comparison point time and three-phase downlink comparison point time
The PWM waveform in period；AD sample triggering moment acquisition module, for according to the three-phase uplink comparison point time obtain it is described under
The first AD sampling triggering moments of one PWM cycle and the 2nd AD sample triggering moment；Three-phase current reconstructed module, for described
Next PWM cycle samples triggering moment according to the first AD and the 2nd AD sampling triggering moments correspond to and read the first direct current
Busbar sample rate current and the second DC bus sample rate current, and it is female according to the first DC bus sample rate current and the second direct current
Line sample rate current reconstructs the three-phase current of the motor.
The three-phase current reconstruct device based on single current sensor proposed according to embodiments of the present invention, first voltage modulated
Module is modulated three-phase output voltage according to voltage modulated algorithm the PWM of the downlink half period to obtain current PWM cycle
The waveform corresponding three-phase comparison point time, next PWM phase shift block is according to preset narrow spaces threshold limit to current PWM cycle
PWM waveform corresponding three-phase comparison point time of downlink half period carry out narrow spaces limitation, and when according to current sample window
Between to narrow spaces limit after the three-phase comparison point time carry out PWM phase shifts processing to obtain three-phase uplink comparison point time and three-phase
The downlink comparison point time, then PWM output modules are according to three-phase uplink comparison point time and the output of three-phase downlink comparison point time
The PWM waveform of next PWM cycle, AD sample triggering moment acquisition module and obtain next PWM according to the three-phase downlink comparison point time
The first AD sampling triggering moments in period and the 2nd AD sample triggering moment, and last three-phase current reconstructed module was at next PWM weeks
Phase samples triggering moment according to the first AD and the 2nd AD sampling triggering moments correspond to and read the first DC bus sample rate current and the
Two DC bus sample rate currents, and motor is reconstructed according to the first DC bus sample rate current and the second DC bus sample rate current
Three-phase current.The device can carry out phase shift in more modulation the algorithm such as modulation of three-phase modulations, two-phase to PWM waveform as a result,
Processing, and then motor three-phase phase current is accurately reconstructed by single current sensor, and can be reduced by narrow spaces limitation
The switching loss of power switch tube.
According to one embodiment of present invention, the PWM waveform corresponding three of the downlink half period of each PWM cycle compares
The point time includes that compare a time Tmax, interphase comparison point time Tmid of maximum compares a time Tmin with minimum,
In, Tmax >=Tmid >=Tmin.
According to one embodiment of present invention, the PWM phase shift blocks are according to the preset narrow spaces threshold limit pair
When the PWM waveform corresponding three-phase comparison point time of the downlink half period of the current PWM cycle carries out narrow spaces limitation,
In, as Tmax ＞ (Ts-Tm)/2, the PWM phase shift blocks are by the PWM waveform of the downlink half period of the current PWM cycle
Maximum in the corresponding three-phase comparison point time time Tmax that compares is limited to Ts/2, wherein and Ts is the PWM cycle,
Tm is the preset narrow spaces threshold limit；As Tmin ＜ Tm/2, the PWM phase shift blocks are by the current PWM cycle
The downlink half period the PWM waveform corresponding three-phase comparison point time in the minimum time Tmin that compares be limited to 0.
According to one embodiment of present invention, the PWM phase shift blocks limit narrow spaces according to current sample window time
When the three-phase comparison point time after system carries out PWM phase shifts processing to obtain three-phase uplink comparison point time and three-phase downlink comparison point
Between when, wherein as (Tmax-Tmid) ＜ Tw, the PWM phase shift blocks to the narrow spaces limit after three-phase comparison point when
Between carry out maximum phase shift phase processor, and minimum phase shift phase processor is carried out after maximum phase shift phase processor, and in minimum phase shift
The three-phase uplink comparison point time and three-phase downlink comparison point time are calculated after phase processor, wherein Tw is that the electric current is adopted
Sample window time；As (Tmax-Tmid) >=Tw and (Tmid-Tmin) ＜ Tw, the PWM phase shift blocks limit the narrow spaces
The three-phase comparison point time after system directly carries out minimum phase shift phase processor, and the three-phase is calculated after minimum phase shift phase processor
Uplink comparison point time and three-phase downlink comparison point time；It is described as (Tmax-Tmid) >=Tw and (Tmid-Tmin) >=Tw
PWM phase shift blocks directly calculate the three-phase uplink comparison point time and three-phase downlink comparison point time.
According to one embodiment of present invention, the three-phase comparison point after the PWM phase shift blocks limit the narrow spaces
When time carries out maximum phase shift phase processor, wherein if (Tmid+Tw) >=Ts/2, δ max=are arranged in PWM phase shift blocks ifs
(Ts/2-Tmax), and δ mid=δ min=(Ts/2-Tw-Tmin) are set, wherein Tw is the current sample window time, Ts
For the PWM cycle, δ max are maximum phase amount of phase shift, and δ mid are interphase amount of phase shift, and δ min are minimum phase shift phasor；If
(Tmid+Tw) δ max=(Tmid+Tw-Tmax) are then arranged in ＜ Ts/2, the PWM phase shift blocks, and δ mid=δ min=are arranged
0。
According to one embodiment of present invention, the three-phase comparison point after the PWM phase shift blocks limit the narrow spaces
When time carries out minimum phase shift phase processor, wherein if (Tmin-Tw)≤0, δ max=δ are arranged in PWM phase shift blocks ifs
Max+Tw-Tmin, and δ mid=δ mid+Tw-Tmin are set, and setting δ min=δ min-Tmin, wherein Tw is the electricity
It flows the sampling window time, δ max are maximum phase amount of phase shift, and δ mid are interphase amount of phase shift, and δ min are minimum phase shift phasor；If
(Tmin-Tw) 0 ＞, δ min=δ min-(Tw-Tmin) is then arranged in the PWM phase shift blocks, and keeps δ max and δ mid constant.
According to one embodiment of present invention, the PWM phase shift blocks calculate the three-phase uplink ratio according to following formula
Compared with time and three-phase downlink comparison point time：Tmax_down=Tmax+ δ max, Tmid_down=Tmid+ δ mid, Tmin_
Down=Tmin+ δ min, wherein when Tmax_down, Tmid_down and Tmin_down are respectively the three-phase downlink comparison point
Between in maximum phase downlink comparison point time, interphase downlink comparison point time and minimum phase downlink comparison point time, Tmax,
Tmid and Tmin is respectively maximum phase downlink comparison point time, interphase downlink comparison point time and the minimum phase downlink before phase shift
The comparison point time；Tmax_up=Tmax × 2-Tmax_down, Tmid_up=Tmid × 2-Tmid_down, Tmin_up=
Tmax × 2-Tmin_down, wherein Tmax_up, Tmid_up and Tmin_up are respectively in the three-phase uplink comparison point time
Maximum phase uplink comparison point time, interphase uplink comparison point time and minimum phase uplink comparison point time.
According to one embodiment of present invention, after obtaining the three-phase uplink comparison point time, the PWM phase shifts mould
Block also carries out amplitude limiting processing to the three-phase uplink comparison point time.
According to one embodiment of present invention, the voltage modulated algorithm is three-phase modulations algorithm, minimum phase two-phase modulation
Any one in algorithm, maximum phase two-phase modulation algorithm and minimax phase two-phase modulation algorithm.
According to one embodiment of present invention, the current sample window time is that DC bus current signal rises stabilization
The sum of sample conversion time when time samples with AD.
Description of the drawings
Fig. 1 is the flow chart of the three-phase current reconstructing method according to the ... of the embodiment of the present invention based on single current sensor；
Fig. 2 is the schematic diagram according to an embodiment of the invention that PWM phase shift processing is carried out to the three-phase comparison point time；
Fig. 3 be carried out in the three-phase current reconstructing method according to an embodiment of the invention based on single current sensor it is narrow
The flow chart of pulsewidth limitation；
Fig. 4 is to obtain three in the three-phase current reconstructing method according to an embodiment of the invention based on single current sensor
The flow chart of phase uplink comparison point time and three-phase downlink comparison point time；
Fig. 5 is the box signal of the three-phase current reconstruct device according to the ... of the embodiment of the present invention based on single current sensor
Figure；And
Fig. 6 is the schematic diagram of electric machine control system according to an embodiment of the invention.
Specific implementation mode
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to for explaining the present invention, and is not considered as limiting the invention.
Below with reference to the accompanying drawings come describe the embodiment of the present invention three-phase current reconstructing method based on single current sensor and
Device.
Fig. 1 is the flow chart of the three-phase current reconstructing method according to the ... of the embodiment of the present invention based on single current sensor.It is single
Current sensor is for detecting DC bus current, specifically, as shown in fig. 6, electric machine control system includes drive module 100,
Wherein, the first input end of drive module 100 is connected with positive direct-current busbar A, the second input terminal of drive module 100 with it is negative straight
Stream busbar B is connected, and the first of drive module 100 is connected to third output end is corresponding with the three phase terminals of motor 200, drive module
100 the first to the 6th control terminal is for receiving drive signal, so that drive module 100 will be on DC bus according to drive signal
Voltage inversion be alternating current and be motor 200 power.Electric machine control system further includes electrolytic capacitor EC, and electrolytic capacitor EC is just
Pole is connected with positive direct-current busbar A, and the cathode of electrolytic capacitor EC is connected with negative DC bus B.One according to the present invention is shown
Example, drive module 100 can be the three-phase bridge drive module being made of 6 IGBT or the three-phase to be made of 6 MOSFET
Bridge-type drive module or be intelligent power module.
In an embodiment of the invention, single current sensor 300 can be connected on negative DC bus B to detect direct current mother
The three-phase current reconstructing method based on single current sensor of line current, the embodiment of the present invention can be carried out according to DC bus current
Motor three-phase current reconstructs.
As shown in Figure 1, the three-phase current reconstructing method based on single current sensor of the embodiment of the present invention includes following step
Suddenly：
S1：Vector controlled is carried out to obtain three-phase output voltage to motor in current PWM cycle, and is calculated according to voltage modulated
The PWM waveform corresponding three that method is modulated three-phase output voltage the downlink half period to obtain current PWM cycle compares
The point time.
Wherein, voltage modulated algorithm can be three-phase modulations algorithm, minimum phase two-phase modulation algorithm, maximum phase two-phase modulation calculation
Any one in method and minimax phase two-phase modulation algorithm.
In embodiments of the present invention, it is all made of increase and decrease clocking method in each PWM cycle and carries out timing, such as in PWM
The uplink half period in period, using incremental timing so that the timing time of timer increases to Ts/2 from 0；And in PWM cycle
The downlink half period, using timing of successively decreasing so that the timing time of timer is reduced to 0 from Ts/2, wherein Ts is PWM cycle.
S2：According to preset narrow spaces threshold limit to the PWM waveform corresponding three of the downlink half period of current PWM cycle
Compare time carries out a narrow spaces limitation, and when three-phase comparison point after being limited narrow spaces according to current sample window time
Between carry out PWM phase shifts processing to obtain three-phase uplink comparison point time and three-phase downlink comparison point time.
Wherein, current sample window time can be to sample to turn when DC bus current signal rises stabilization time with AD samplings
Change the sum of time.
S3：The PWM wave of next PWM cycle is exported according to three-phase uplink comparison point time and three-phase downlink comparison point time
Shape, and according to the three-phase downlink comparison point time obtain next PWM cycle the first AD sampling triggering moment and the 2nd AD sample touch
Send out the moment.
That is, can be compared according to the three-phase uplink comparison point time and three-phase downlink obtained after PWM phase shifts processing
The point time exports the three-phase PWM waveform of next PWM cycle, in this way next PWM cycle can be according to the three-phase of next PWM cycle
PWM waveform generates 6 road PWM drive signals, and drive module can control motor operation according to 6 road PWM drive signals of generation.
According to an example of the present invention, what the way of output of PWM waveform can be used symmetrical complement is incremented by output side of successively decreasing
Formula.
It should be understood that being on shape there are one the top tube and down tube of each phase in synchronization drive module
State, the PWM drive signal for being provided to the top tube and down tube of same phase have complementary relationship.As an example it is assumed that three-phase PWM waveform
Respectively U phases PWM waveform, V phases PWM waveform and W phase PWM waveforms, U phases PWM waveform can be provided to the pipes of the U+ in Fig. 6, U phases PWM
The complementary waveform of waveform can be provided to the pipes of the U- in Fig. 6；V phases PWM waveform can be provided to the pipes of the V+ in Fig. 6, V phase PWM waveforms
Complementary waveform can be provided to the pipes of the V- in Fig. 6；W phases PWM waveform can be provided to the pipes of the W+ in Fig. 6, the complementary wave of W phase PWM waveforms
Shape can be provided to the pipes of the W- in Fig. 6.
Also, as shown in Fig. 2, the first AD for obtaining next PWM cycle according to the three-phase downlink comparison point time samples triggering
When moment and the 2nd AD sampling triggering moments, the first AD sampling triggering moment T1 and the 2nd AD samplings triggering moment T2 will be arranged
The downlink half period of next PWM cycle, when the first AD sampling triggering moments T1 is the interphase downlink comparison point after phase shift at this time
Between subtract the AD sample conversion times, in fig. 2, moment T1 is located at the position of interphase downlink comparison point time subsequent arrow meaning
It sets；2nd AD sampling triggering moments T2 is the maximum phase downlink comparison point time after phase shift to subtract the AD sample conversion times, in Fig. 2
In, moment T2 is located at the position of subsequent arrow meaning of maximum phase downlink comparison point time.
S4：Triggering moment is sampled according to the first AD in next PWM cycle and the 2nd AD sampling triggering moments correspond to and read the
One DC bus sample rate current and the second DC bus sample rate current, and according to the first DC bus sample rate current and the second direct current
Busbar sample rate current reconstructs the three-phase current of motor.
Wherein, triggering moment T1 is sampled in the first AD, DC bus current can be detected by single current sensor to obtain
The the first DC bus sample rate current of moment T1 sampled is denoted as electric current I by the first DC bus sample rate current；In the 2nd AD
Sample triggering moment T2, can by single current sensor detect DC bus current to obtain the second DC bus sample rate current,
The the second DC bus sample rate current of moment T2 sampled is denoted as electric current II.
Specifically, as shown in Fig. 2, when the first AD sampling triggering moment T1 and the 2nd AD sampling triggering moment T2 settings exist
When the downlink half period of next PWM cycle, current sampling data can be read after the PWM wave paddy moment Tx of next PWM cycle
That is electric current I and electric current II, i.e., the lower PWM cycle after next PWM cycle read current sampling data, that is, electric current I and electric current
II, and motor three-phase current reconstruct is carried out according to three phase relations of current PWM cycle (maximum phase, interphase and minimum phase),
In, according to electric current I and electric current II and two-phase phase current in three-phase can be directly acquired, last phase phase current can be mutually electric according to three-phase
Stream scalar sum is zero to be calculated.
According to an example of the present invention, electric current I can be the negative value of maximum phase phase current, and electric current II can be minimum mutually electricity
Stream, as shown in table 1 below, when maximum phase is U in three-phase, electric current I is the negative value of U phase currents；When maximum phase is V in three-phase,
Electric current I is the negative value of V phase currents；When maximum phase is W in three-phase, electric current I is the negative value of W phase currents；When minimum phase in three-phase
For U when, electric current II be U phase currents；When minimum phase is V in three-phase, electric current II is V phase currents；When minimum phase is W in three-phase
When, electric current II is W phase currents.
Table 1
As a result, motor three-phase electricity is being carried out according to three phase relations (maximum phase, interphase and minimum phase) of current PWM cycle
When stream reconstruct, maximum phase phase current is the negative value of electric current I, and minimum phase phase current is electric current II, and interphase phase current is (maximum phase
Phase current+minimum phase phase current) negative value.
This method carries out at phase shift PWM waveform in more modulation the algorithm such as modulation of three-phase modulations, two-phase as a result,
Reason, and then motor three-phase phase current is accurately reconstructed by single current sensor, and work(can be reduced by narrow spaces limitation
The switching loss of rate switching tube.
According to one embodiment of present invention, as shown in Fig. 2, the PWM waveform of the downlink half period of each PWM cycle corresponds to
The three-phase comparison point time include that maximum compares a time Tmax, interphase comparison point time Tmid when comparing with minimum
Between Tmin, wherein Tmax >=Tmid >=Tmin.
That is, can be compared according to the size of PWM waveform three-phase comparison point time, the descending maximum that is defined as successively
It compares with minimum a time Tmin compared with a time Tmax, interphase comparison point time Tmid, to distinguish each PWM cycle
Maximum phase, interphase and minimum phase.
It should be noted that the downlink half period of each PWM cycle uses the clocking method that successively decreases, in this way, in the downlink of Fig. 2
In half period, the comparison point time of front is more than the subsequent comparison point time, and each comparison point time is both greater than equal to 0 and small
In equal to PWM cycle/2, i.e. Ts >=Tmax >=Tmid >=Tmin >=0.According to one embodiment of present invention, as shown in figure 3, root
According to preset narrow spaces threshold limit to the PWM waveform of the downlink half period of the current PWM cycle corresponding three-phase comparison point time
It is that step S2 further comprises to carry out narrow spaces limitation：
S21：As Tmax ＞ (Ts-Tm)/2, by the corresponding three-phase of PWM waveform of the downlink half period of current PWM cycle
Maximum in the comparison point time time Tmax that compares is limited to Ts/2, wherein Ts is PWM cycle, and Tm is preset narrow arteries and veins
Wide threshold limit；
S22：As Tmin ＜ Tm/2, by the corresponding three-phase comparison point of the PWM waveform of the downlink half period of current PWM cycle
Minimum in the time time Tmin that compares is limited to 0.
It is maximum when that is, maximum compares, time Tmax is more than ((PWM cycle-narrow spaces threshold limit)/2)
The time Tmax that compares is set to (PWM cycle/2), i.e., maximum corresponding upper tube output constant low level in drive module, most
Big corresponding down tube exports constant high level；And when minimum compares a time Tmin less than (narrow spaces threshold limit/2)
When, the minimum time Tmin that compares is set to zero, i.e., minimum corresponding upper tube exports constant high level, minimum in drive module
Corresponding down tube exports constant low level.
In other words, narrow spaces limitation is exactly exported when PWM pulsewidths are more than (PWM cycle-narrow spaces threshold limit) constant
High level exports constant low level when PWM pulsewidths are less than narrow spaces threshold limit.
Further, according to one embodiment of present invention, as shown in figure 4, according to current sample window time to narrow arteries and veins
The three-phase comparison point time after tolerance system carries out PWM phase shifts processing and is compared with obtaining three-phase uplink comparison point time and three-phase downlink
Point time, that is, step S2, including：
S23：As (Tmax-Tmid) ＜ Tw, the three-phase comparison point time after limiting narrow spaces carries out maximum phase phase shift
Processing, and minimum phase shift phase processor is carried out after maximum phase shift phase processor, and calculate three after minimum phase shift phase processor
Phase uplink comparison point time and three-phase downlink comparison point time, wherein Tw is current sample window time；
S24：As (Tmax-Tmid) >=Tw and (Tmid-Tmin) ＜ Tw, to narrow spaces limit after three-phase comparison point when
Between directly carry out minimum phase shift phase processor, and calculated under three-phase uplink comparison point time and three-phase after minimum phase shift phase processor
The row comparison point time；
S25：As (Tmax-Tmid) >=Tw and (Tmid-Tmin) >=Tw, directly calculate the three-phase uplink comparison point time and
The three-phase downlink comparison point time.
That is, judging whether (maximum compare a time Tmax- interphase comparison point time Tmin) is less than electric current
When sampling window time Tw, if (Tmax-Tmid) ＜ Tw, carry out maximum phase shift phase processor and minimum phase shift phase processor；It is no
Then, if (Tmax-Tmid) >=Tw, further judge that (interphase comparison point time Tmid- minimums compare the time
Tmin) whether it is less than current sample window time Tw, if (Tmid-Tmin) ＜ Tw, carry out minimum phase shift phase processor, if
(Tmid-Tmin) >=Tw is then handled without phase shift.
Specifically, when the three-phase comparison point time after limiting narrow spaces carries out maximum phase shift phase processor, wherein if
(Tmid+Tw) δ max=(Ts/2-Tmax) are then arranged in >=Ts/2, and δ mid=δ min=(Ts/2-Tw-Tmin) are arranged,
In, Tw is current sample window time, and Ts is PWM cycle, and δ max are maximum phase amount of phase shift, and δ mid are interphase amount of phase shift, δ
Min is minimum phase shift phasor；If (Tmid+Tw) ＜ Ts/2 are arranged δ max=(Tmid+Tw-Tmax), and δ mid=are arranged
δ min=0.
That is, if (interphase comparison point time Tmid+ current samples window time Tw) >=(PWM cycle Ts/
2), then, maximum phase amount of phase shift δ max are (PWM cycle Ts/2- maximums compare a time Tmax), interphase amount of phase shift δ mid
It is (PWM cycle Ts/2- current sample window time Tw- minimums compare a time Tmin) with minimum phase shift phasor δ min；
Otherwise, if (interphase comparison point time Tmid+ current samples window time Tw)<Maximum phase is then arranged in (PWM cycle Ts/2)
Amount of phase shift δ max are (interphase comparison point time Tmid+ current samples window time Tw- maximums compare a time Tmax), in
Between phase amount of phase shift δ mid and minimum phase shift phasor δ min be zero.
Also, when the three-phase comparison point time after limiting narrow spaces carries out minimum phase shift phase processor, wherein if
(Tmin-Tw)≤0, then δ max=δ max+Tw-Tmin are set, and δ mid=δ mid+Tw-Tmin are set, and setting δ min=
δ min-Tmin, wherein Tw is current sample window time, and δ max are maximum phase amount of phase shift, and δ mid are interphase amount of phase shift, δ
Min is minimum phase shift phasor；If (Tmin-Tw) ＞ 0, δ min=δ min-(Tw-Tmin) is set, and keeps δ max and δ
Mid is constant.
That is, if (minimum compare a time Tmin- current sample window time Tw)≤0, maximum phase
Amount of phase shift δ max increase (current sample window time Tw- minimums compare a time Tmin) with interphase amount of phase shift δ mid i.e.
δ max=δ max+Tw-Tmin, δ mid=δ mid+Tw-Tmin, (minimum compares the time for minimum phase shift phasor δ min reductions
Tmin) i.e. δ min=δ min-Tmin；Otherwise, if (minimum compare a time Tmin- current sample window time Tw) ＞ 0,
Then maximum phase amount of phase shift δ max and interphase amount of phase shift δ mid are constant, and minimum phase shift phasor δ min reduce (when current sample window
Between Tw- minimums compare a time Tmin) i.e. δ min=δ min-(Tw-Tmin).
It should be noted that before carrying out phase shift processing every time, it sets δ max, δ mid and δ min to initial value of zero.
Further, according to one embodiment of present invention, when the PWM waveform pair of the downlink half period of current PWM cycle
When the three-phase comparison point time answered is in the downlink half period of current period, after phase shift before downlink comparison point time=phase shift under
The row comparison point time+correspondence phase amount of phase shift；Uplink comparison point time × 2- after phase shift before uplink comparison point time=phase shift is moved
The uplink comparison point time after phase.Specifically, can be calculated according to following formula next PWM cycle the three-phase uplink comparison point time and
The three-phase downlink comparison point time：
Tmax_down=Tmax+ δ max,
Tmid_down=Tmid+ δ mid,
Tmin_down=Tmin+ δ min, wherein Tmax_down, Tmid_down and Tmin_down are respectively under three-phase
When maximum phase downlink comparison point time, interphase downlink comparison point time in the row comparison point time and minimum phase downlink comparison point
Between, Tmax, Tmid and Tmin are respectively maximum phase downlink comparison point time before phase shift, interphase downlink comparison point time and most
The small phase downlink comparison point time；
Tmax_up=Tmax × 2-Tmax_down,
Tmid_up=Tmid × 2-Tmid_down,
Tmin_up=Tmax × 2-Tmin_down, wherein Tmax_up, Tmid_up and Tmin_up are respectively on three-phase
When maximum phase uplink comparison point time, interphase uplink comparison point time in the row comparison point time and minimum phase uplink comparison point
Between.
In addition, according to one embodiment of present invention, after obtaining the three-phase uplink comparison point time, also to phase shift after
The three-phase uplink comparison point time carries out amplitude limiting processing.Specifically, the maximum value of three-phase uplink comparison point time is limited to after phase shift
(PWM cycle Ts/2), minimum value are limited to zero.
To sum up, the three-phase current reconstructing method based on single current sensor proposed according to embodiments of the present invention, exists first
Current PWM cycle carries out vector controlled to motor to obtain three-phase output voltage, and is exported to three-phase according to voltage modulated algorithm
Voltage is modulated the PWM waveform corresponding three-phase comparison point time of the downlink half period to obtain current PWM cycle, secondly root
According to preset narrow spaces threshold limit to the PWM waveform of the downlink half period of the current PWM cycle corresponding three-phase comparison point time
Narrow spaces limitation is carried out, and PWM shiftings are carried out to the three-phase comparison point time after narrow spaces limitation according to current sample window time
Phase processor is to obtain three-phase uplink comparison point time and three-phase downlink comparison point time, then according to the three-phase uplink comparison point time
The PWM waveform of next PWM cycle is exported with the three-phase downlink comparison point time, and next according to the acquisition of three-phase downlink comparison point time
The first AD sampling triggering moments of PWM cycle and the 2nd AD sample triggering moment, are finally adopted according to the first AD in next PWM cycle
Sample triggering moment and the 2nd AD sampling triggering moments correspond to and read the first DC bus sample rate current and the sampling of the second DC bus
Electric current, and according to the three-phase current of the first DC bus sample rate current and the second DC bus sample rate current reconstruct motor.As a result,
This method can carry out phase shift processing in more modulation the algorithm such as modulation of three-phase modulations, two-phase to PWM waveform, and then pass through list
Current sensor accurately reconstructs motor three-phase phase current, and can reduce the switch of power switch tube by narrow spaces limitation
Loss.
The three-phase current reconstruct device based on single current sensor using the above method is described below.
Fig. 5 is the box signal of the three-phase current reconstruct device according to the ... of the embodiment of the present invention based on single current sensor
Figure.As shown in fig. 6, single current sensor 300 is for detecting DC bus current.As shown in figure 5, based on single current sensor
Three-phase current reconstructs device：When voltage modulated module 10, PWM phase shift blocks 20, PWM output modules 30, AD sampling triggerings
Carve acquisition module 40 and three-phase current reconstructed module 50.
Specifically, voltage modulated module 10 is used to be modulated to obtain three-phase output voltage according to voltage modulated algorithm
The PWM waveform corresponding three-phase comparison point time of the downlink half period of current PWM cycle, wherein three-phase output voltage is according to working as
Preceding PWM cycle carries out vector controlled acquisition to motor.Wherein, voltage modulated algorithm can be three-phase modulations algorithm, minimum phase two-phase
Any one in modulation algorithm, maximum phase two-phase modulation algorithm and minimax phase two-phase modulation algorithm.Implement in the present invention
In example, it is all made of increase and decrease clocking method in each PWM cycle and carries out timing, such as in the uplink half period of PWM cycle, uses
It is incremented by timing so that the timing time of timer increases to Ts/2 from 0；And in the downlink half period of PWM cycle, using the meter that successively decreases
When so that the timing time of timer is reduced to 0 from Ts/2, wherein Ts is PWM cycle.
PWM phase shift blocks 20 were used for according to preset narrow spaces threshold limit to downlink half period of current PWM cycle
The PWM waveform corresponding three-phase comparison point time carries out narrow spaces limitation, and is limited narrow spaces according to current sample window time
When the three-phase comparison point time afterwards carries out PWM phase shifts processing to obtain three-phase uplink comparison point time and three-phase downlink comparison point
Between.Wherein, when current sample window time can be sample conversion when DC bus current signal rises stabilization time and AD samplings
The sum of between.
PWM output modules 30 are used for next according to three-phase uplink comparison point time and the output of three-phase downlink comparison point time
The PWM waveform of PWM cycle.According to an example of the present invention, being incremented by for symmetrical complement can be used in the way of output of PWM waveform
Subtract the way of output.
AD samplings triggering moment acquisition module 40 according to the three-phase downlink comparison point time for obtaining the of next PWM cycle
One AD samples triggering moment and the 2nd AD samples triggering moment.
Three-phase current reconstructed module 50 is used to sample triggering moment according to the first AD in next PWM cycle and the 2nd AD is sampled
Triggering moment, which corresponds to, reads the first DC bus sample rate current and the second DC bus sample rate current, and according to the first DC bus
The three-phase current of sample rate current and the second DC bus sample rate current reconstruct motor.
The device can carry out at phase shift PWM waveform in more modulation the algorithm such as modulation of three-phase modulations, two-phase as a result,
Reason, and then motor three-phase phase current is accurately reconstructed by single current sensor, and work(can be reduced by narrow spaces limitation
The switching loss of rate switching tube.
According to one embodiment of present invention, as shown in Fig. 2, the PWM waveform of the downlink half period of each PWM cycle corresponds to
The three-phase comparison point time include that maximum compares a time Tmax, interphase comparison point time Tmid when comparing with minimum
Between Tmin, wherein Tmax >=Tmid >=Tmin.
According to one embodiment of present invention, PWM phase shift blocks 20 according to preset narrow spaces threshold limit to current PWM
When the PWM waveform corresponding three-phase comparison point time of the downlink half period in period carries out narrow spaces limitation, wherein as Tmax ＞
(Ts-Tm)/2 when, when the PWM waveform of the downlink half period of current PWM cycle is the corresponding three-phase comparison point of PWM phase shift blocks 20
Between in the maximum time Tmax that compares be limited to Ts/2, wherein Ts is PWM cycle, and Tm is that preset narrow spaces limit threshold
Value；As Tmin ＜ Tm/2, PWM phase shift blocks 20 compare the PWM waveform corresponding three of the downlink half period of current PWM cycle
It is limited to 0 compared with the time Tmin that compares of the minimum in the time.
Further, according to one embodiment of present invention, PWM phase shift blocks 20 according to current sample window time to narrow
The three-phase comparison point time after pulsewidth limitation carries out PWM phase shifts processing to obtain three-phase uplink comparison point time and three-phase downlink ratio
When compared with time, wherein as (Tmax-Tmid) ＜ Tw, PWM phase shift blocks 20 narrow spaces are limited after three-phase comparison point when
Between carry out maximum phase shift phase processor, and minimum phase shift phase processor is carried out after maximum phase shift phase processor, and in minimum phase shift
Three-phase uplink comparison point time and three-phase downlink comparison point time are calculated after phase processor, wherein when Tw is current sample window
Between；As (Tmax-Tmid) >=Tw and (Tmid-Tmin) ＜ Tw, three after PWM phase shift blocks 20 limit narrow spaces compare
The point time directly carries out minimum phase shift phase processor, and the three-phase uplink comparison point time and three is calculated after minimum phase shift phase processor
The phase downlink comparison point time；As (Tmax-Tmid) >=Tw and (Tmid-Tmin) >=Tw, PWM phase shift blocks 20 directly calculate three
Phase uplink comparison point time and three-phase downlink comparison point time.
Further, according to one embodiment of present invention, three after PWM phase shift blocks 20 limit narrow spaces compare
When carrying out maximum phase shift phase processor compared with the time, wherein if δ max are arranged if phase shift block 20 (Tmid+Tw) >=Ts/2, PWM
=(Ts/2-Tmax), and δ mid=δ min=(Ts/2-Tw-Tmin) are set, wherein Tw is current sample window time, and Ts is
PWM cycle, δ max are maximum phase amount of phase shift, and δ mid are interphase amount of phase shift, and δ min are minimum phase shift phasor；If (Tmid+
Tw δ max=(Tmid+Tw-Tmax) are then arranged in) ＜ Ts/2, PWM phase shift block 20, and δ mid=δ min=0 are arranged.
Further, according to one embodiment of present invention, three after PWM phase shift blocks 20 limit narrow spaces compare
When carrying out minimum phase shift phase processor compared with the time, wherein if δ max=δ are arranged if phase shift block 20 (Tmin-Tw)≤0, PWM
Max+Tw-Tmin, and δ mid=δ mid+Tw-Tmin are set, and setting δ min=δ min-Tmin, wherein Tw adopts for electric current
Sample window time, δ max are maximum phase amount of phase shift, and δ mid are interphase amount of phase shift, and δ min are minimum phase shift phasor；If
(Tmin-Tw) 0 ＞, δ min=δ min-(Tw-Tmin) is then arranged in PWM phase shift blocks 20, and keeps δ max and δ mid constant.
A specific embodiment according to the present invention, when the PWM waveform corresponding three of the downlink half period of current PWM cycle
The time compare when being in the downlink half period of current period, PWM phase shift blocks 20 calculate three-phase uplink according to following formula
Comparison point time and three-phase downlink comparison point time：
Tmax_down=Tmax+ δ max,
Tmid_down=Tmid+ δ mid,
Tmin_down=Tmin+ δ min, wherein Tmax_down, Tmid_down and Tmin_down are respectively under three-phase
When maximum phase downlink comparison point time, interphase downlink comparison point time in the row comparison point time and minimum phase downlink comparison point
Between, Tmax, Tmid and Tmin are respectively maximum phase downlink comparison point time before phase shift, interphase downlink comparison point time and most
The small phase downlink comparison point time；
Tmax_up=Tmax × 2-Tmax_down,
Tmid_up=Tmid × 2-Tmid_down,
Tmin_up=Tmax × 2-Tmin_down, wherein Tmax_up, Tmid_up and Tmin_up are respectively on three-phase
When maximum phase uplink comparison point time, interphase uplink comparison point time in the row comparison point time and minimum phase uplink comparison point
Between.
In addition, according to one embodiment of present invention, after obtaining the three-phase uplink comparison point time, PWM phase shift blocks
20 also carry out amplitude limiting processing to the three-phase uplink comparison point time.
To sum up, the three-phase current reconstruct device based on single current sensor proposed according to embodiments of the present invention, it is electric first
Pressure modulation module is modulated three-phase output voltage according to voltage modulated algorithm to obtain the downlink half period of current PWM cycle
The PWM waveform corresponding three-phase comparison point time, secondly PWM phase shift blocks according to preset narrow spaces threshold limit to current
The PWM waveform corresponding three-phase comparison point time of the downlink half period of PWM cycle carries out narrow spaces limitation, and according to current sample
The three-phase comparison point time after window time limits narrow spaces carries out PWM phase shifts processing to obtain the three-phase uplink comparison point time
With the three-phase downlink comparison point time, when then PWM output modules are according to three-phase uplink comparison point time and three-phase downlink comparison point
Between export the PWM waveform of next PWM cycle, AD is sampled under triggering moment acquisition module obtains according to the three-phase downlink comparison point time
The first AD sampling triggering moments of one PWM cycle and the 2nd AD sample triggering moment, and last three-phase current reconstructed module is next
PWM cycle samples triggering moment according to the first AD and the 2nd AD sampling triggering moments correspond to and read the first DC bus sample rate current
With the second DC bus sample rate current, and electricity is reconstructed according to the first DC bus sample rate current and the second DC bus sample rate current
The three-phase current of machine.The device can move PWM waveform in such as three-phase modulations, the two-phase modulation of more modulation algorithm as a result,
Phase processor, and then motor three-phase phase current is accurately reconstructed by single current sensor, and can be subtracted by narrow spaces limitation
The switching loss of small power switch pipe.
In the description of the present invention, it is to be understood that, term " first ", " second " are used for description purposes only, and cannot
It is interpreted as indicating or implies relative importance or implicitly indicate the quantity of indicated technical characteristic.Define as a result, " the
One ", the feature of " second " can explicitly or implicitly include at least one of the features.In the description of the present invention, " multiple "
It is meant that at least two, such as two, three etc., unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；Can be that machinery connects
It connects, can also be electrical connection；It can be directly connected, can also can be indirectly connected through an intermediary in two elements
The interaction relationship of the connection in portion or two elements, unless otherwise restricted clearly.For those of ordinary skill in the art
For, the specific meanings of the above terms in the present invention can be understood according to specific conditions.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
It can be combined in any suitable manner in one or more embodiments or example.In addition, without conflicting with each other, the skill of this field
Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples
It closes and combines.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, changes, replacing and modification.
Claims (20)
1. a kind of three-phase current reconstructing method based on single current sensor, which is characterized in that the single current sensor is used for
DC bus current is detected, the described method comprises the following steps：
Vector controlled is carried out to obtain three-phase output voltage, and according to voltage modulated algorithm to institute to motor in current PWM cycle
State the corresponding three-phase comparison point of PWM waveform for the downlink half period that three-phase output voltage is modulated to obtain current PWM cycle
Time；
According to preset narrow spaces threshold limit to the corresponding three-phase of PWM waveform of the downlink half period of the current PWM cycle
The comparison point time carries out narrow spaces limitation, and according to current sample window time to the three-phase comparison point time after narrow spaces limitation
PWM phase shifts processing is carried out to obtain three-phase uplink comparison point time and three-phase downlink comparison point time；
The PWM waveform of next PWM cycle is exported according to the three-phase uplink comparison point time and three-phase downlink comparison point time, and
The first AD sampling triggering moments and the 2nd AD samplings of next PWM cycle are obtained according to the three-phase downlink comparison point time
Triggering moment；
Triggering moment is sampled according to the first AD in next PWM cycle and the 2nd AD sampling triggering moments are corresponded to and read
Take the first DC bus sample rate current and the second DC bus sample rate current, and according to the first DC bus sample rate current and
Second DC bus sample rate current reconstructs the three-phase current of the motor.
2. the three-phase current reconstructing method according to claim 1 based on single current sensor, which is characterized in that each
The PWM waveform corresponding three-phase comparison point time of the downlink half period of PWM cycle includes that maximum compares time Tmax, a centre
The time Tmid that compares compares a time Tmin with minimum, wherein Tmax >=Tmid >=Tmin.
3. the three-phase current reconstructing method according to claim 2 based on single current sensor, which is characterized in that described
According to preset narrow spaces threshold limit to the corresponding three-phase comparison point of the PWM waveform of the downlink half period of the current PWM cycle
Time carries out narrow spaces limitation, including：
As Tmax ＞ (Ts-Tm)/2, the PWM waveform corresponding three of the downlink half period of the current PWM cycle is compared
The maximum time Tmax that compares in the point time is limited to Ts/2, wherein Ts is the PWM cycle, and Tm is described preset
Narrow spaces threshold limit；
As Tmin ＜ Tm/2, by the PWM waveform of the downlink half period of the current PWM cycle corresponding three-phase comparison point time
In the minimum time Tmin that compares be limited to 0.
4. the three-phase current reconstructing method according to claim 3 based on single current sensor, which is characterized in that described
The three-phase comparison point time after being limited narrow spaces according to current sample window time carries out PWM phase shifts processing to obtain three-phase uplink
Comparison point time and three-phase downlink comparison point time, including：
As (Tmax-Tmid) ＜ Tw, the three-phase comparison point time after limiting the narrow spaces carries out maximum phase shift phase processor,
And minimum phase shift phase processor is carried out after maximum phase shift phase processor, and the three-phase is calculated after minimum phase shift phase processor
Uplink comparison point time and three-phase downlink comparison point time, wherein Tw is the current sample window time；
As (Tmax-Tmid) >=Tw and (Tmid-Tmin) ＜ Tw, the three-phase comparison point time after limiting the narrow spaces is straight
Row minimum phase shift phase processor is tapped into, and is calculated under the three-phase uplink comparison point time and three-phase after minimum phase shift phase processor
The row comparison point time；
As (Tmax-Tmid) >=Tw and (Tmid-Tmin) >=Tw, the three-phase uplink comparison point time and three-phase are directly calculated
The downlink comparison point time.
5. the three-phase current reconstructing method according to claim 4 based on single current sensor, which is characterized in that described
When the three-phase comparison point time after narrow spaces limitation carries out maximum phase shift phase processor, wherein
If (Tmid+Tw) >=Ts/2, δ max=(Ts/2-Tmax) are set, and δ mid=δ min=(Ts/2-Tw- are set
Tmin), wherein Tw is the current sample window time, and Ts is the PWM cycle, and δ max are maximum phase amount of phase shift, and δ mid are
Interphase amount of phase shift, δ min are minimum phase shift phasor；
If δ max=(Tmid+Tw-Tmax) are arranged in (Tmid+Tw) ＜ Ts/2, and δ mid=δ min=0 are arranged.
6. the three-phase current reconstructing method according to claim 4 or 5 based on single current sensor, which is characterized in that right
When the three-phase comparison point time after the narrow spaces limitation carries out minimum phase shift phase processor, wherein
If (Tmin-Tw)≤0, δ max=δ max+Tw-Tmin are set, and δ mid=δ mid+Tw-Tmin, Yi Jishe are set
Set δ min=δ min-Tmin, wherein Tw is the current sample window time, and δ max are maximum phase amount of phase shift, and δ mid are centre
Phase amount of phase shift, δ min are minimum phase shift phasor；
If (Tmin-Tw) ＞ 0, δ min=δ min-(Tw-Tmin) is set, and keeps δ max and δ mid constant.
7. the three-phase current reconstructing method according to claim 6 based on single current sensor, which is characterized in that PWM weeks
The PWM waveform corresponding three-phase comparison point time of the downlink half period of phase calculates the three-phase uplink comparison point according to following formula
Time and three-phase downlink comparison point time：
Tmax_down=Tmax+ δ max,
Tmid_down=Tmid+ δ mid,
Tmin_down=Tmin+ δ min, wherein Tmax_down, Tmid_down and Tmin_down are respectively under the three-phase
When maximum phase downlink comparison point time, interphase downlink comparison point time in the row comparison point time and minimum phase downlink comparison point
Between, Tmax, Tmid and Tmin are respectively maximum phase downlink comparison point time before phase shift, interphase downlink comparison point time and most
The small phase downlink comparison point time；
Tmax_up=Tmax × 2-Tmax_down,
Tmid_up=Tmid × 2-Tmid_down,
Tmin_up=Tmax × 2-Tmin_down, wherein Tmax_up, Tmid_up and Tmin_up are respectively on the three-phase
When maximum phase uplink comparison point time, interphase uplink comparison point time in the row comparison point time and minimum phase uplink comparison point
Between.
8. the three-phase current reconstructing method according to claim 1 based on single current sensor, which is characterized in that obtaining
After the three-phase uplink comparison point time, amplitude limiting processing also is carried out to the three-phase uplink comparison point time.
9. the three-phase current reconstructing method according to claim 1 based on single current sensor, which is characterized in that the electricity
Pressure modulation algorithm is three-phase modulations algorithm, minimum phase two-phase modulation algorithm, maximum phase two-phase modulation algorithm and minimax phase two
Any one in phase modulation algorithm.
10. the three-phase current reconstructing method according to claim 1 based on single current sensor, which is characterized in that described
Current sample window time is that DC bus current signal rises the sum of stabilization time and sample conversion time when AD samplings.
11. a kind of three-phase current based on single current sensor reconstructs device, which is characterized in that the single current sensor is used for
DC bus current is detected, described device includes：
Voltage modulated module, for being modulated to three-phase output voltage according to voltage modulated algorithm to obtain current PWM cycle
The downlink half period the PWM waveform corresponding three-phase comparison point time, wherein the three-phase output voltage was according to current PWM weeks
Phase carries out vector controlled acquisition to motor；
PWM phase shift blocks, for according to preset narrow spaces threshold limit to downlink half period of the current PWM cycle
The PWM waveform corresponding three-phase comparison point time carries out narrow spaces limitation, and is limited narrow spaces according to current sample window time
When the three-phase comparison point time afterwards carries out PWM phase shifts processing to obtain three-phase uplink comparison point time and three-phase downlink comparison point
Between；
PWM output modules, for exporting next PWM according to the three-phase uplink comparison point time and three-phase downlink comparison point time
The PWM waveform in period；
AD samples triggering moment acquisition module, for obtaining next PWM cycle according to the three-phase downlink comparison point time
The first AD sampling triggering moment and the 2nd AD sample triggering moment；
Three-phase current reconstructed module, for sampling triggering moment and described the according to the first AD in next PWM cycle
Two AD sample triggering moment and correspond to the first DC bus sample rate current of reading and the second DC bus sample rate current, and according to described
First DC bus sample rate current and the second DC bus sample rate current reconstruct the three-phase current of the motor.
12. according to the devices described in claim 11, which is characterized in that the PWM waveform pair of the downlink half period of each PWM cycle
The three-phase comparison point time answered includes that compare a time Tmax, interphase comparison point time Tmid of maximum compares a little with minimum
Time Tmin, wherein Tmax >=Tmid >=Tmin.
13. device according to claim 12, which is characterized in that the PWM phase shift blocks are according to the preset narrow arteries and veins
Wide threshold limit carries out narrow arteries and veins to the PWM waveform of the downlink half period of the current PWM cycle corresponding three-phase comparison point time
When tolerance is processed, wherein
As Tmax ＞ (Ts-Tm)/2, the PWM phase shift blocks are by the PWM waveform of the downlink half period of the current PWM cycle
Maximum in the corresponding three-phase comparison point time time Tmax that compares is limited to Ts/2, wherein and Ts is the PWM cycle,
Tm is the preset narrow spaces threshold limit；
As Tmin ＜ Tm/2, the PWM phase shift blocks correspond to the PWM waveform of the downlink half period of the current PWM cycle
The three-phase comparison point time in the minimum time Tmin that compares be limited to 0.
14. device according to claim 13, which is characterized in that when the PWM phase shift blocks are according to current sample window
Between to narrow spaces limit after the three-phase comparison point time carry out PWM phase shifts processing to obtain three-phase uplink comparison point time and three-phase
When the downlink comparison point time, wherein
As (Tmax-Tmid) ＜ Tw, the three-phase comparison point time after the PWM phase shift blocks limit the narrow spaces carries out
Maximum phase shift phase processor, and minimum phase shift phase processor is carried out after maximum phase shift phase processor, and in minimum phase shift phase processor
The three-phase uplink comparison point time and three-phase downlink comparison point time are calculated later, wherein Tw is the current sample window
Time；
As (Tmax-Tmid) >=Tw and (Tmid-Tmin) ＜ Tw, after the PWM phase shift blocks limit the narrow spaces
The three-phase comparison point time directly carries out minimum phase shift phase processor, and the three-phase uplink ratio is calculated after minimum phase shift phase processor
Compared with time and three-phase downlink comparison point time；
As (Tmax-Tmid) >=Tw and (Tmid-Tmin) >=Tw, the PWM phase shift blocks directly calculate the three-phase uplink
Comparison point time and three-phase downlink comparison point time.
15. device according to claim 14, which is characterized in that after the PWM phase shift blocks limit the narrow spaces
Three-phase comparison point time when carrying out maximum phase shift phase processor, wherein
If (Tmid+Tw) >=Ts/2, δ max=(Ts/2-Tmax) are arranged in PWM phase shift blocks ifs, and δ mid=δ are arranged
Min=(Ts/2-Tw-Tmin), wherein Tw is the current sample window time, and Ts is the PWM cycle, and δ max are maximum
Phase amount of phase shift, δ mid are interphase amount of phase shift, and δ min are minimum phase shift phasor；
If (Tmid+Tw) ＜ Ts/2, δ max=(Tmid+Tw-Tmax) are arranged in PWM phase shift blocks ifs, and δ mid are arranged
=δ min=0.
16. the device according to claims 14 or 15, which is characterized in that the PWM phase shift blocks limit the narrow spaces
When the three-phase comparison point time after system carries out minimum phase shift phase processor, wherein
If (Tmin-Tw)≤0, δ max=δ max+Tw-Tmin are arranged in PWM phase shift blocks ifs, and δ mid=δ mid are arranged
+ Tw-Tmin, and setting δ min=δ min-Tmin, wherein Tw is the current sample window time, and δ max are maximum phase shift
Phasor, δ mid are interphase amount of phase shift, and δ min are minimum phase shift phasor；
If (Tmin-Tw) ＞ 0, δ min=δ min-(Tw-Tmin) is arranged in PWM phase shift blocks ifs, and keeps δ max and δ
Mid is constant.
17. device according to claim 16, which is characterized in that the PWM phase shift blocks calculate institute according to following formula
State three-phase uplink comparison point time and three-phase downlink comparison point time：
Tmax_down=Tmax+ δ max,
Tmid_down=Tmid+ δ mid,
Tmin_down=Tmin+ δ min, wherein Tmax_down, Tmid_down and Tmin_down are respectively under the three-phase
When maximum phase downlink comparison point time, interphase downlink comparison point time in the row comparison point time and minimum phase downlink comparison point
Between, Tmax, Tmid and Tmin are respectively maximum phase downlink comparison point time before phase shift, interphase downlink comparison point time and most
The small phase downlink comparison point time；
Tmax_up=Tmax × 2-Tmax_down,
Tmid_up=Tmid × 2-Tmid_down,
Tmin_up=Tmax × 2-Tmin_down, wherein Tmax_up, Tmid_up and Tmin_up are respectively on the three-phase
When maximum phase uplink comparison point time, interphase uplink comparison point time in the row comparison point time and minimum phase uplink comparison point
Between.
18. device according to claim 12, which is characterized in that after obtaining the three-phase uplink comparison point time,
The PWM phase shift blocks also carry out amplitude limiting processing to the three-phase uplink comparison point time.
19. device according to claim 12, which is characterized in that the voltage modulated algorithm is three-phase modulations algorithm, most
Any one in small phase two-phase modulation algorithm, maximum phase two-phase modulation algorithm and minimax phase two-phase modulation algorithm.
20. device according to claim 12, which is characterized in that the current sample window time is DC bus current
Signal rises the sum of stabilization time and sample conversion time when AD samplings.
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| CN110855215B (en) * | 2018-08-21 | 2021-06-04 | 广东威灵汽车部件有限公司 | PWM phase shifting method and PWM phase shifting device of permanent magnet motor |
| CN109412445B (en) * | 2018-09-19 | 2020-08-14 | 中南大学 | Hybrid modulation method based on O-HERIC single-phase inverter with narrow pulse width limit compensation |
| CN109639210B (en) * | 2018-12-25 | 2021-06-25 | 哈尔滨工业大学 | Topology capable of realizing multi-phase current reconstruction algorithm |
| CN110034712B (en) * | 2019-05-21 | 2020-09-08 | 四川虹美智能科技有限公司 | Single-resistor sampling control method and device |
| CN111525868B (en) * | 2020-05-09 | 2021-09-24 | 苏俊 | Phase shifting method and system for three-phase inverter and readable storage medium |
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| WO2022099637A1 (en) * | 2020-11-13 | 2022-05-19 | 深圳市汇顶科技股份有限公司 | Phase shift compensation and phase current reconstruction methods, chip, electronic device, and storage medium |
| CN112436773B (en) * | 2020-11-17 | 2022-04-01 | 北京理工大学 | Improved dead-beat prediction control method for permanent magnet synchronous motor single current sensor |
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