CN105679772B - 低温多晶硅tft基板的制作方法及低温多晶硅tft基板 - Google Patents

低温多晶硅tft基板的制作方法及低温多晶硅tft基板 Download PDF

Info

Publication number
CN105679772B
CN105679772B CN201610066225.6A CN201610066225A CN105679772B CN 105679772 B CN105679772 B CN 105679772B CN 201610066225 A CN201610066225 A CN 201610066225A CN 105679772 B CN105679772 B CN 105679772B
Authority
CN
China
Prior art keywords
layer
doped region
heavily doped
photoresist pattern
low temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610066225.6A
Other languages
English (en)
Other versions
CN105679772A (zh
Inventor
虞晓江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to CN201610066225.6A priority Critical patent/CN105679772B/zh
Priority to US15/138,183 priority patent/US20170221929A1/en
Publication of CN105679772A publication Critical patent/CN105679772A/zh
Application granted granted Critical
Publication of CN105679772B publication Critical patent/CN105679772B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明提供一种低温多晶硅TFT基板的制作方法及低温多晶硅TFT基板。本发明的低温多晶硅TFT基板的制作方法，通过先采用倾斜离子束对多晶硅层进行高剂量的离子植入，以形成重掺杂区，再采用垂直离子束进行低剂量的离子植入，以形成轻掺杂区，简便的制作出具有单边LDD区的薄膜晶体管，从而可以减小薄膜晶体管的热载流子效应及漏电，简化了低温多晶硅TFT基板的制作过程并降低了低温多晶硅TFT基板的制作成本。本发明的低温多晶硅TFT基板，其薄膜晶体管具有单边LDD区，可以减小薄膜晶体管的热载流子效应及漏电，且制作工艺简单，制作成本低。

Description

低温多晶硅TFT基板的制作方法及低温多晶硅TFT基板
技术领域
本发明涉及显示技术领域，尤其涉及一种低温多晶硅TFT基板的制作方法及低温多晶硅TFT基板。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜(CF，Color Filter)基板、薄膜晶体管(TFT，Thin FilmTransistor)基板、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成，其成型工艺一般包括：前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(TFT基板与CF基板贴合)及后段模组组装制程(驱动IC与印刷电路板压合)。其中，前段Array制程主要是形成TFT基板，以便于控制液晶分子的运动；中段Cell制程主要是在TFT基板与CF基板之间添加液晶；后段模组组装制程主要是驱动IC压合与印刷电路板的整合，进而驱动液晶分子转动，显示图像。
LTPS(Low Temperature Poly-Silicon，低温多晶硅)显示面板在高端手机、平板电脑上已获得广泛应用，IPHONE 6s手机、LG G4手机、Kindle Fire Hdx平板电脑等产品均使用LTPS显示面板。LTPS技术可以通过激光退火等方法在玻璃基板上形成高迁移率的低温多晶硅半导体层，使显示屏具有高分辨率、低功耗、高反应速度、高开口率等优点。但LTPS显示面板中的TFT基板的制造过程非常复杂，常常需要9道光罩以上的制程来生产，复杂的制造过程显著影响了LTPS显示面板的良率和价格。因此，简化TFT基板的制造过程对于LTPS显示面板的推广具有重要作用。
发明内容
本发明的目的在于提供一种低温多晶硅TFT基板的制作方法，可简便的制作出具有单边LDD区的薄膜晶体管，简化了低温多晶硅TFT基板的制作过程并降低了低温多晶硅TFT基板的制作成本。
本发明的目的还在于提供一种低温多晶硅TFT基板，其薄膜晶体管具有单边LDD区，可以减小薄膜晶体管的热载流子效应及漏电，且制作工艺简单，制作成本低。
为实现上述目的，本发明提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上依次形成缓冲层、多晶硅层、及栅极绝缘层；
步骤2、在所述栅极绝缘层上沉积第一金属层，在所述第一金属层上涂布光阻材料，利用光罩对所述光阻材料进行曝光、显影后，对剩余的光阻层进行硬烤，使显影液挥发，增强其稳定性；
步骤3、对所述第一金属层进行蚀刻，得到栅极、及位于栅极上方的光阻层；
步骤4、在所述光阻层、及栅极绝缘层上涂布光阻材料，曝光、显影后，得到位于栅极上方的第一光阻图案、以及分别距所述第一光阻图案左右两侧一段距离且位于所述栅极绝缘层上的第二光阻图案与第三光阻图案；
步骤5、以所述第一光阻图案、第二光阻图案、第三光阻图案为遮挡层，采用倾斜离子束对所述多晶硅层进行高剂量的离子掺杂，离子束倾斜穿过第一光阻图案与第二光阻图案之间、及第一光阻图案与第三光阻图案之间，在所述多晶硅层上分别形成第一重掺杂区、及第二重掺杂区；
步骤6、以所述第一光阻图案、第二光阻图案、第三光阻图案为遮挡层，采用垂直离子束对所述多晶硅层进行低剂量的离子掺杂，离子束垂直穿过第一光阻图案与第二光阻图案之间、及第一光阻图案与第三光阻图案之间，在所述多晶硅层上分别形成邻接所述第一重掺杂区的第一轻掺杂区、以及邻接所述第二重掺杂区的第二轻掺杂区，并在所述第二重掺杂区与第一轻掺杂区之间形成未掺杂的沟道区；
步骤7、剥离所述第一光阻图案、第二光阻图案、及第三光阻图案，在所述栅极及栅极绝缘层上形成层间绝缘层，通过光刻制程在所述层间绝缘层、及栅极绝缘层上形成分别对应于所述第一重掺杂区、及第二重掺杂区上方的过孔；
步骤8、在所述层间绝缘层上沉积第二金属层，通过光刻制程对所述第二金属层进行图形化处理，得到源极与漏极，所述源极与漏极分别经由过孔与第一重掺杂区、及第二重掺杂区相接触。
所述步骤1中，所述多晶硅层的制作过程为：在所述缓冲层上沉积非晶硅层，采用低温结晶工艺将所述非晶硅层转化为多晶硅层，所述低温结晶工艺为固相晶化、准分子激光晶化、快速热退火、或金属横向诱导法。
所述第一重掺杂区、及第二重掺杂区的剖面结构为平行四边形；所述第一轻掺杂区、及第二轻掺杂区的剖面结构为直角梯形。
所述第一重掺杂区、第二重掺杂区、第一轻掺杂区、及第二轻掺杂区中掺入的离子均为硼离子或者磷离子。
所述基板为玻璃基板；所述缓冲层、栅极绝缘层、及层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一金属层、第二金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明还提供一种低温多晶硅TFT基板，包括基板、设于基板上的缓冲层、设于缓冲层上的多晶硅层、设于多晶硅层上的栅极绝缘层、设于栅极绝缘层上的栅极、设于所述栅极及栅极绝缘层上的层间绝缘层、以及设于层间绝缘层上的源极与漏极；
所述多晶硅层上设有第一重掺杂区、第二重掺杂区、第一轻掺杂区、第二轻掺杂区、及未掺杂的沟道区，所述第一轻掺杂区、第二轻掺杂区分别邻接于所述第一重掺杂区、及第二重掺杂区相同的一侧，且所述沟道区位于所述第二重掺杂区与第一轻掺杂区之间；
所述层间绝缘层及栅极绝缘层上设有分别对应于所述第一重掺杂区、及第二重掺杂区上方的过孔，所述源极与漏极分别经由过孔与第一重掺杂区、及第二重掺杂区相接触。
所述第一重掺杂区、及第二重掺杂区的剖面结构为平行四边形；所述第一轻掺杂区、及第二轻掺杂区的剖面结构为直角梯形。
所述第一重掺杂区、第二重掺杂区、第一轻掺杂区、及第二轻掺杂区中掺入的离子均为硼离子或者磷离子。
所述基板为玻璃基板；所述缓冲层、栅极绝缘层、及层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述栅极、源极、漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明的有益效果：本发明的低温多晶硅TFT基板的制作方法，通过先采用倾斜离子束对多晶硅层进行高剂量的离子植入，以形成重掺杂区，再采用垂直离子束进行低剂量的离子植入，以形成轻掺杂区，简便的制作出具有单边LDD区的薄膜晶体管，从而可以减小薄膜晶体管的热载流子效应及漏电，简化了低温多晶硅TFT基板的制作过程并降低了低温多晶硅TFT基板的制作成本。本发明的低温多晶硅TFT基板，其薄膜晶体管具有单边LDD区，可以减小薄膜晶体管的热载流子效应及漏电，且制作工艺简单，制作成本低。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的低温多晶硅TFT基板的制作方法的步骤1的示意图；
图2-3为本发明的低温多晶硅TFT基板的制作方法的步骤2的示意图；
图4为本发明的低温多晶硅TFT基板的制作方法的步骤3的示意图；
图5为本发明的低温多晶硅TFT基板的制作方法的步骤4的示意图；
图6为本发明的低温多晶硅TFT基板的制作方法的步骤5的示意图；
图7为本发明的低温多晶硅TFT基板的制作方法的步骤6的示意图；
图8-9为本发明的低温多晶硅TFT基板的制作方法的步骤7的示意图；
图10为本发明的低温多晶硅TFT基板的制作方法的步骤8的示意图暨本发明的低温多晶硅TFT基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1-10，本发明提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、如图1所示，提供一基板10，在所述基板10上依次形成缓冲层20、多晶硅层30、及栅极绝缘层40。
具体的，所述基板10为透明基板，优选为玻璃基板。
具体的，所述多晶硅层30的制作过程为：在所述缓冲层20上沉积非晶硅层，采用低温结晶工艺将所述非晶硅层转化为多晶硅层30，所述低温结晶工艺可以为固相晶化(SPC)、准分子激光晶化(ELA)、快速热退火(RTA)、或金属横向诱导法(MILC)等等。
步骤2、如图2-3所示，在所述栅极绝缘层40上沉积第一金属层41，在所述第一金属层41上涂布光阻材料42，利用光罩45对所述光阻材料42进行曝光、显影后，对剩余的光阻层51进行硬烤(hard bake)，使显影液挥发，增强其稳定性。
步骤3、如图4所示，对所述第一金属层41进行蚀刻，得到栅极50、及位于栅极50上方的光阻层51。
正常制程中，一般还需要对栅极50上方的光阻层51进行剥离后才能进行下一制程，而本发明中，不需要对光阻层51进行剥离，即可进行下一制程，从而节约了一道光阻剥离制程，简化了低温多晶硅TFT基板的制造过程并降低了低温多晶硅TFT基板的制造成本。
步骤4、如图5所示，在所述光阻层51、及栅极绝缘层40上涂布光阻材料，曝光、显影后，得到位于栅极50上方的第一光阻图案61、以及分别距所述第一光阻图案61左右两侧一段距离且位于所述栅极绝缘层40上的第二光阻图案62与第三光阻图案63。
具体的，所述第一光阻图案61可以为步骤3中的光阻层51、也可以为步骤4中在光阻层51上新涂布的光阻材料和光阻层51的复合层。
步骤5、如图6所示，以所述第一光阻图案61、第二光阻图案62、第三光阻图案63为遮挡层，采用倾斜离子束对所述多晶硅层30进行高剂量的离子掺杂，离子束倾斜穿过第一光阻图案61与第二光阻图案62之间、及第一光阻图案61与第三光阻图案63之间，在所述多晶硅层30上形成第一重掺杂区31、及第二重掺杂区32。
具体的，由于采用倾斜离子束对所述多晶硅层30进行高剂量的离子掺杂，因此，得到的所述第一重掺杂区31、及第二重掺杂区32的剖面结构为如图6所示的平行四边形。
步骤6、如图7所示，以所述第一光阻图案61、第二光阻图案62、第三光阻图案63为遮挡层，采用垂直离子束对所述多晶硅层30进行低剂量的离子掺杂，离子束倾斜穿过第一光阻图案61与第二光阻图案62之间、及第一光阻图案61与第三光阻图案63之间，在所述多晶硅层30上形成邻接所述第一重掺杂区31的第一轻掺杂区33、以及邻接所述第二重掺杂区32的第二轻掺杂区34，并在所述第二重掺杂区32与第一轻掺杂区34之间形成未掺杂的沟道区35。
具体的，由于采用垂直离子束对所述多晶硅层30进行低剂量的离子掺杂，因此，得到的所述第一轻掺杂区33、及第二轻掺杂区34的剖面结构为如图7所示的直角梯形。
具体的，所述第一重掺杂区31、第二重掺杂区31、第一轻掺杂区33、及第二轻掺杂区34中掺入的离子均为硼离子或者磷离子。
步骤7、如图8-9所示，剥离所述第一光阻图案61、第二光阻图案62、及第三光阻图案63，在所述栅极50、及栅极绝缘层40上形成层间绝缘层70，通过光刻制程在所述层间绝缘层70及栅极绝缘层40上形成分别对应于所述第一重掺杂区31、及第二重掺杂区32上方的过孔71。
步骤8、如图10所示，在所述层间绝缘层70上沉积第二金属层，通过光刻制程对所述第二金属层进行图形化处理，得到源极81与漏极82，所述源极81与漏极82分别经由过孔71与第一重掺杂区31、及第二重掺杂区32相接触。
具体的，所述第一金属层41、第二金属层的材料可以是钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
具体的，所述缓冲层20、栅极绝缘层40、及层间绝缘层70可以为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的，本发明制得的低温多晶硅TFT基板中，所述第一轻掺杂区33位于第一重掺杂区31与沟道区35之间，起到单边LDD(Lightly Doped Drain，轻掺杂漏区)的作用，所述第二轻掺杂区34位于第二重掺杂区32的外侧，不能起到LDD的作用。
上述低温多晶硅TFT基板的制作方法，通过先采用倾斜离子束对多晶硅层进行高剂量的离子植入，以形成重掺杂区，再采用垂直离子束进行低剂量的离子植入，以形成轻掺杂区，从而可简便的制作出具有单边LDD区的薄膜晶体管，减小薄膜晶体管的热载流子效应及漏电，简化了低温多晶硅TFT基板的制作过程并降低了低温多晶硅TFT基板的制作成本。
请参阅图10，本发明还提供一种低温多晶硅TFT基板，包括基板10、设于基板10上的缓冲层20、设于缓冲层20上的多晶硅层30、设于多晶硅层30上的栅极绝缘层40、设于栅极绝缘层40上的栅极50、设于所述栅极50及栅极绝缘层40上的层间绝缘层70、以及设于层间绝缘层70上的源极81与漏极82；
所述多晶硅层30上设有第一重掺杂区31、第二重掺杂区32、第一轻掺杂区33、第二轻掺杂区34、及未掺杂的沟道区35，所述第一轻掺杂区33、第二轻掺杂区34分别邻接于所述第一重掺杂区31、及第二重掺杂区32相同的一侧，且所述沟道区35位于所述第二重掺杂区32与第一轻掺杂区33之间；
所述层间绝缘层70及栅极绝缘层40上设有分别对应于所述第一重掺杂区31、及第二重掺杂区32上方的过孔71，所述源极81与漏极82分别经由过孔71与第一重掺杂区31、及第二重掺杂区32相接触。
具体的，所述基板10为透明基板，优选为玻璃基板。
具体的，所述缓冲层20、栅极绝缘层40、及层间绝缘层70可以为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的，所述栅极50、源极81、漏极82的材料可以是钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
具体的，所述第一重掺杂区31、及第二重掺杂区32的剖面结构为平行四边形。所述第一轻掺杂区33、及第二轻掺杂区34的剖面结构为直角梯形。
具体的，所述第一重掺杂区31、第二重掺杂区32、第一轻掺杂区33、及第二轻掺杂区34中掺入的离子均为硼离子或者磷离子。
上述低温多晶硅TFT基板，其薄膜晶体管具有单边LDD区(即第一轻掺杂区33)，可以减小薄膜晶体管的热载流子效应及漏电，且制作工艺简单，制作成本低。
综上所述，本发明提供一种低温多晶硅TFT基板的制作方法及低温多晶硅TFT基板。本发明的低温多晶硅TFT基板的制作方法，通过先采用倾斜离子束对多晶硅层进行高剂量的离子植入，以形成重掺杂区，再采用垂直离子束进行低剂量的离子植入，以形成轻掺杂区，简便的制作出具有单边LDD区的薄膜晶体管，从而可以减小薄膜晶体管的热载流子效应及漏电，简化了低温多晶硅TFT基板的制作过程并降低了低温多晶硅TFT基板的制作成本。本发明的低温多晶硅TFT基板，其薄膜晶体管具有单边LDD区，可以减小薄膜晶体管的热载流子效应及漏电，且制作工艺简单，制作成本低。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (8)

1.一种低温多晶硅TFT基板的制作方法，其特征在于，包括如下步骤：
步骤1、提供一基板(10)，在所述基板(10)上依次形成缓冲层(20)、多晶硅层(30)、及栅极绝缘层(40)；
步骤2、在所述栅极绝缘层(40)上沉积第一金属层(41)，在所述第一金属层(41)上涂布光阻材料(42)，利用光罩(45)对所述光阻材料(42)进行曝光、显影后，对剩余的光阻层(51)进行硬烤，使显影液挥发，增强其稳定性；
步骤3、对所述第一金属层(41)进行蚀刻，得到栅极(50)、及位于栅极(50)上方的光阻层(51)；
步骤4、在所述光阻层(51)、及栅极绝缘层(40)上涂布光阻材料，曝光、显影后，得到位于栅极(50)上方的第一光阻图案(61)、以及分别距所述第一光阻图案(61)左右两侧一段距离且位于所述栅极绝缘层(40)上的第二光阻图案(62)与第三光阻图案(63)；
步骤5、以所述第一光阻图案(61)、第二光阻图案(62)、第三光阻图案(63)为遮挡层，采用倾斜离子束对所述多晶硅层(30)进行高剂量的离子掺杂，离子束倾斜穿过第一光阻图案(61)与第二光阻图案(62)之间、及第一光阻图案(61)与第三光阻图案(63)之间，在所述多晶硅层(30)上分别形成第一重掺杂区(31)、及第二重掺杂区(32)；
步骤6、以所述第一光阻图案(61)、第二光阻图案(62)、第三光阻图案(63)为遮挡层，采用垂直离子束对所述多晶硅层(30)进行低剂量的离子掺杂，离子束垂直穿过第一光阻图案(61)与第二光阻图案(62)之间、及第一光阻图案(61)与第三光阻图案(63)之间，在所述多晶硅层(30)上分别形成邻接所述第一重掺杂区(31)的第一轻掺杂区(33)、以及邻接所述第二重掺杂区(32)的第二轻掺杂区(34)，并在所述第二重掺杂区(32)与第一轻掺杂区(33)之间形成未掺杂的沟道区(35)；
步骤7、剥离所述第一光阻图案(61)、第二光阻图案(62)、及第三光阻图案(63)，在所述栅极(50)、及栅极绝缘层(40)上形成层间绝缘层(70)，通过光刻制程在所述层间绝缘层(70)及栅极绝缘层(40)上形成分别对应于所述第一重掺杂区(31)、及第二重掺杂区(32)上方的过孔(71)；
步骤8、在所述层间绝缘层(70)上沉积第二金属层，通过光刻制程对所述第二金属层进行图形化处理，得到源极(81)与漏极(82)，所述源极(81)与漏极(82)分别经由过孔(71)与第一重掺杂区(31)、及第二重掺杂区(32)相接触。
2.如权利要求1所述的低温多晶硅TFT基板的制作方法，其特征在于，所述步骤1中，所述多晶硅层(30)的制作过程为：在所述缓冲层(20)上沉积非晶硅层，采用低温结晶工艺将所述非晶硅层转化为多晶硅层(30)，所述低温结晶工艺为固相晶化、准分子激光晶化、快速热退火、或金属横向诱导法。
3.如权利要求1所述的低温多晶硅TFT基板的制作方法，其特征在于，所述第一重掺杂区(31)、及第二重掺杂区(32)的剖面结构为平行四边形；所述第一轻掺杂区(33)、及第二轻掺杂区(34)的剖面结构为直角梯形。
4.如权利要求1所述的低温多晶硅TFT基板的制作方法，其特征在于，所述第一重掺杂区(31)、第二重掺杂区(32)、第一轻掺杂区(33)、及第二轻掺杂区(34)中掺入的离子均为硼离子或者磷离子。
5.如权利要求1所述的低温多晶硅TFT基板的制作方法，其特征在于，所述基板(10)为玻璃基板；所述缓冲层(20)、栅极绝缘层(40)、及层间绝缘层(70)为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一金属层(41)、第二金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
6.一种低温多晶硅TFT基板，其特征在于，包括基板(10)、设于基板(10)上的缓冲层(20)、设于缓冲层(20)上的多晶硅层(30)、设于多晶硅层(30)上的栅极绝缘层(40)、设于栅极绝缘层(40)上的栅极(50)、设于所述栅极(50)及栅极绝缘层(40)上的层间绝缘层(70)、以及设于层间绝缘层(70)上的源极(81)与漏极(82)；
所述多晶硅层(30)上设有第一重掺杂区(31)、第二重掺杂区(32)、第一轻掺杂区(33)、第二轻掺杂区(34)、及未掺杂的沟道区(35)，所述第一轻掺杂区(33)、第二轻掺杂区(34)分别邻接于所述第一重掺杂区(31)、及第二重掺杂区(32)相同的一侧，且所述沟道区(35)位于所述第二重掺杂区(32)与第一轻掺杂区(33)之间；
所述层间绝缘层(70)及栅极绝缘层(40)上设有分别对应于所述第一重掺杂区(31)、及第二重掺杂区(32)上方的过孔(71)，所述源极(81)与漏极(82)分别经由过孔(71)与第一重掺杂区(31)、及第二重掺杂区(32)相接触；
所述第一重掺杂区(31)、及第二重掺杂区(32)的剖面结构为平行四边形；所述第一轻掺杂区(33)、及第二轻掺杂区(34)的剖面结构为直角梯形。
7.如权利要求6所述的低温多晶硅TFT基板，其特征在于，所述第一重掺杂区(31)、第二重掺杂区(32)、第一轻掺杂区(33)、及第二轻掺杂区(34)中掺入的离子均为硼离子或者磷离子。
8.如权利要求6所述的低温多晶硅TFT基板，其特征在于，所述基板(10)为玻璃基板；所述缓冲层(20)、栅极绝缘层(40)、及层间绝缘层(70)为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述栅极(50)、源极(81)、漏极(82)的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
CN201610066225.6A 2016-01-29 2016-01-29 低温多晶硅tft基板的制作方法及低温多晶硅tft基板 Active CN105679772B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201610066225.6A CN105679772B (zh) 2016-01-29 2016-01-29 低温多晶硅tft基板的制作方法及低温多晶硅tft基板
US15/138,183 US20170221929A1 (en) 2016-01-29 2016-04-25 Manufacture method of low temperature poly-silicon tft substrate and low temperature poly-silicon tft substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610066225.6A CN105679772B (zh) 2016-01-29 2016-01-29 低温多晶硅tft基板的制作方法及低温多晶硅tft基板

Publications (2)

Publication Number Publication Date
CN105679772A CN105679772A (zh) 2016-06-15
CN105679772B true CN105679772B (zh) 2018-11-09

Family

ID=56303103

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610066225.6A Active CN105679772B (zh) 2016-01-29 2016-01-29 低温多晶硅tft基板的制作方法及低温多晶硅tft基板

Country Status (2)

Country Link
US (1) US20170221929A1 (zh)
CN (1) CN105679772B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10854455B2 (en) * 2016-11-21 2020-12-01 Marvell Asia Pte, Ltd. Methods and apparatus for fabricating IC chips with tilted patterning
CN107414289B (zh) * 2017-07-27 2019-05-17 京东方科技集团股份有限公司 一种激光剥离方法及激光剥离***
CN109888021A (zh) * 2019-02-27 2019-06-14 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
US11221359B2 (en) * 2019-03-15 2022-01-11 International Business Machines Corporation Determining device operability via metal-induced layer exchange

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6646287B1 (en) * 1999-11-19 2003-11-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with tapered gate and insulating film
US6573162B2 (en) * 1999-12-24 2003-06-03 Semiconductor Energy Laboratory Co., Ltd. Laser irradiation apparatus and method of fabricating a semiconductor device
US7064021B2 (en) * 2003-07-02 2006-06-20 Au Optronics Corp. Method for fomring a self-aligned LTPS TFT
US7588970B2 (en) * 2005-06-10 2009-09-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
KR100769433B1 (ko) * 2006-12-04 2007-10-22 삼성에스디아이 주식회사 박막 트랜지스터, 그의 제조 방법 및 박막 트랜지스터를구비하는 평판 표시 장치
JP5323604B2 (ja) * 2009-07-30 2013-10-23 株式会社ジャパンディスプレイ 表示装置及びその製造方法

Also Published As

Publication number Publication date
CN105679772A (zh) 2016-06-15
US20170221929A1 (en) 2017-08-03

Similar Documents

Publication Publication Date Title
CN105552027B (zh) 阵列基板的制作方法及阵列基板
US10473990B2 (en) Manufacture method of low temperature poly-silicon array substrate
US10103173B2 (en) Manufacture method of array substrate and array substrate manufactured by the method
CN105489552B (zh) Ltps阵列基板的制作方法
CN105390451A (zh) 低温多晶硅tft基板的制作方法
CN101656233B (zh) 薄膜晶体管基板的制造方法
CN105679772B (zh) 低温多晶硅tft基板的制作方法及低温多晶硅tft基板
CN105097675A (zh) 阵列基板及其制备方法
CN105470195B (zh) Tft基板的制作方法
CN105742292A (zh) 阵列基板的制作方法及制得的阵列基板
CN105655359A (zh) Tft基板的制作方法
CN105679705B (zh) 阵列基板的制作方法
JP2008042218A (ja) 薄膜トランジスタパネルの製造方法
CN105702622B (zh) 低温多晶硅tft基板的制作方法及低温多晶硅tft基板
CN108598086A (zh) Tft阵列基板的制作方法及tft阵列基板
CN104934439A (zh) Tft基板的制作方法及其结构
CN105514123B (zh) Ltps阵列基板的制作方法
CN105355593B (zh) Tft基板的制作方法及tft基板
CN105161458B (zh) Tft基板的制作方法
CN109616415A (zh) 低温多晶硅薄膜晶体管的制作方法
CN102856392B (zh) 薄膜晶体管主动装置及其制作方法
CN208738249U (zh) 显示面板
CN110047851A (zh) Tft阵列基板及其制作方法
CN108231794A (zh) 阵列基板的制备方法、阵列基板
CN100536117C (zh) 薄膜晶体管面板的制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant